Power Manager Appendix#
Glossary#
Active state: A power state where the microcontroller unit (MCU) core executes instructions and peripherals are available.
Clock scaling: The ability to adjust the system clock frequency to balance performance and power consumption.
Critical section: A code section protected by disabling interrupts to ensure atomic operations in multithreaded environments.
Deep sleep: An ultra-low-power operational state characterized by suspension of the system clock. Operation resumes only when triggered by designated wake-up sources.
Event callback: A user-defined function that runs when specific power-state transitions occur.
Interrupt service routine (ISR): A function that runs in response to a hardware interrupt.
ARM Cortex-M4 subsystem (M4SS): The main processing core and its associated peripherals.
Peripheral power gate: A hardware mechanism that selectively powers individual peripheral blocks on or off.
Power domain: A section of the chip that can be powered on or off independently.
Power requirement: A request to maintain a minimum power state, preventing the system from entering lower-power modes.
Power state: A defined operating mode with specific power consumption and performance characteristics (PS0–PS4, Sleep, Standby).
RAM retention: The ability to preserve memory contents during sleep modes by providing minimal power to RAM banks.
Sleep mode: A power state where the processor stops executing instructions but can be awakened by configured wake-up sources.
Standby mode: A power-saving state where the processor is clock-gated, with the ability to wake on any interrupt event.
Tickless idle: A power management feature that allows a microcontroller to enter a low-power, sleep mode when no tasks are ready to run, by stopping the periodic tick interrupt and resuming it later only when an event wakes the system.
Ultra-low-power subsystem (ULPSS): A collection of peripheral components designed for optimized power efficiency during the PS2 active state.
Wake-up source: A hardware event or peripheral that can trigger the system to exit sleep mode.
Acronyms#
Acronym | Full term | Description |
|---|---|---|
ADC | Analog-to-digital converter | Converts analog signals to digital values |
BOD | Brownout detector | Monitors supply voltage |
CMSIS | Cortex Microcontroller Software Interface Standard | ARM hardware abstraction layer |
DAC | Digital-to-analog converter | Converts digital values to analog signals |
DMA | Direct memory access | Enables efficient data transfer |
DST | Deep sleep timer | Timer that runs during sleep modes |
FreeRTOS | Free real-time operating system | Open-source real-time operating system kernel |
GPIO | General-purpose input/output | Configurable digital pins |
HP | High power | High-power peripheral domain |
I2C | Inter-integrated circuit | Serial communication protocol |
I2S | Inter-IC sound | Digital audio interface |
IDE | Integrated development environment | Software development environment |
ISR | Interrupt service routine | Function executed on interrupt |
M4SS | ARM Cortex-M4 subsystem | Cortex-M4 processor subsystem |
MCU | Microcontroller unit | Integrated circuit with processor, memory, and I/O |
NWP | Network wireless processor | Wireless communication processor |
PM | Power manager | Power management component |
PS | Power state | Defined power mode (PS0–PS4) |
RTC | Real-time clock | Time-keeping peripheral |
SPI | Serial peripheral interface | Synchronous serial communication |
SSI | Synchronous serial interface | Serial communication protocol |
SysRTC | System real-time clock | System-level time-keeping peripheral |
UART | Universal asynchronous receiver-transmitter | Serial communication interface |
UC | Universal Configurator | Simplicity Studio configuration tool |
ULP | Ultra-low power | Design optimized for minimal power consumption |
ULPSS | Ultra-low-power subsystem | Low-power peripheral subsystem |
UULP | Ultra-ultra-low power | Extremely low-power peripheral domain |
WDT | Watchdog timer | System monitoring and reset timer |
Extended Examples#
SL Si91x - Power Manager Tickless Idle
This example demonstrates the integration of FreeRTOS tickless idle mode with Si91x power management functionality. The implementation automatically manages transitions between active power states (PS4, PS3, PS2) and sleep/standby states while maintaining RAM retention during periods of task inactivity.
Example: sl_si91x_power_manager_tickless_idle
Next Steps (Further References)#
Official documentation
API references
Community resources
FAQ#
Q1. What is the Power Manager Service and why use it?
The Power Manager Service is a requirement-based power management system for Silicon Labs Si91x wireless SoCs. It transitions between power states on application request, automatically optimizing power consumption.
It integrates with FreeRTOS tickless idle mode to provide seamless sleep entry and wake-up management.
It helps extend battery life in applications.
Q2. What is the default power state when the system starts?
The system starts in PS3 PowerSave mode (40 MHz) by default.
This mode balances performance and power consumption.
Configuration and Setup#
Q3. How do I enable the Power Manager in my project?
Install the Power Manager component through Universal Configurator (UC) in Simplicity Studio.
Installation automatically includes the required initialization code.
The SI91X TICK-LESS MODE component is automatically installed with the Power Manager to support FreeRTOS tickless idle functionality.
Refer to the Initialization and Configuration section for comprehensive setup procedures and configuration parameters.
Q4. What is the difference between Power Manager Configuration and Advanced Configuration?
Basic configuration lets you choose which peripherals remain powered on or off by domain.
Advanced configuration offers enhanced peripheral control options, enabling users to selectively disable peripherals according to specific application requirements for optimized power consumption reduction.
Advanced mode provides finer control of power settings.
Q5. Do I need to initialize the Power Manager manually?
No, if you are using
sl_system, callsl_system_init().Otherwise, call
sl_si91x_power_manager_init()manually.The Power Manager component handles initialization when installed through UC.
Power State Management#
Q6. How does the requirement-based system work?
Software modules add power state requirements using
sl_si91x_power_manager_add_ps_requirement().The system transitions to the highest required power state.
When requirements are removed using
sl_si91x_power_manager_remove_ps_requirement(), the system transitions to the next highest requirement or the default state.
Q7. Can multiple requirements exist for the same power state?
Yes. Multiple modules can add requirements for the same state.
The system tracks the number of requirements and only transitions to a lower state when all higher-state requirements are removed.
Q8. What happens if PS4 and PS2 requirements are active at the same time?
The system runs in PS4 (the higher power state).
It transitions to PS2 only after the PS4 requirement is removed.
Sleep and Low-Power Modes#
Q9. How does FreeRTOS tickless idle work with the Power Manager?
When all FreeRTOS tasks are blocked and the idle time exceeds the configurable threshold (default: 100 ms), the system enters sleep mode automatically.
Use semaphores in your tasks. When
osSemaphoreAcquire()blocks all tasks, tickless idle activates.
Q10. Which peripherals can wake the system from sleep?
Wake-up sources include ultra-ultra-low-power (UULP) GPIO interrupts, the deep sleep timer, calendar, and wireless events.
Configure wake-up sources through the Wake-up Source Configuration component.
Q11. How do I configure wake-up sources?
Use the PM Wake-up Source Configuration component in UC to enable and configure calendar/alarm, GPIO, deep sleep timer, or wireless wake-up sources.
Ensure the corresponding UULP peripheral components are installed.
Peripheral Management#
Q12. Which peripherals operate in each power state?
PS4/PS3: All high-power (HP), ultra-low-power (ULP), and UULP peripherals.
PS2: Only ULP and UULP peripherals (Flash is disabled).
PS1: Only ULP peripherals at 32 kHz.
Sleep: Only UULP peripherals (used for wake-up).
For additional details, please refer to the following documentation:
Q13. How do I use ULP peripherals in PS2 state?
Install the PM PS2 Component and required ULP peripheral components.
Add preprocessor definitions:
SL_SI91X_ULP_STATE_ENABLE=1SLI_SI91X_MCU_ENABLE_RAM_BASED_EXECUTION=1
Since Flash is disabled in PS2, driver files are copied to RAM automatically by the driver.
Q14. How do I manage RAM retention during sleep?
Configure RAM retention in the Power Manager Configuration component by size (KB) or by bank number.
Use only one method. If both are enabled, size takes precedence.
Callbacks and Events#
Q15. How do I get notified of power state transitions?
Subscribe to transition events with
sl_si91x_power_manager_subscribe_ps_transition_event().Register callbacks for entering or leaving specific states to reconfigure peripherals.
Q16. What should transition callbacks do?
Keep callbacks fast and non-blocking because they run in interrupt context.
Use callbacks to:
Save or restore peripheral configurations.
Enable or disable clocks.
Perform housekeeping tasks required for safe transitions.
Performance and Optimization#
Q17. What is the difference between PowerSave and Performance modes?
PowerSave: Lower frequencies for reduced power use (PS4: 100 MHz, PS3: 40 MHz).
Performance: Higher frequencies for maximum performance (PS4: 160 MHz, PS3: 80 MHz).
Use
sl_si91x_power_manager_set_clock_scaling()to switch modes.
Troubleshooting#
Q18. Why doesn't the system enter sleep mode in tickless idle mode?
The system may fail to enter sleep mode in tickless idle mode due to the following potential causes:
Tasks are not properly blocked (verify semaphore usage and task synchronization).
The
app_is_ok_to_sleep()function is returning false. This function performs pre-sleep validation checks and must return true for sleep entry to proceed. The function may return false due to the following conditions:There are pending packets in the NWP.
The NWP is not configured to operate in RAM retention mode, which is required for tickless idle sleep.
There are active power state requirements in the power manager requirement table.
Q19. Why doesn’t the system wake up from sleep?
Check the following:
Wake-up sources are configured and enabled.
Required UULP peripheral components are installed.
GPIO polarity is configured for wake-up.
The deep sleep timer is configured correctly.