System Real-Time Clock (SYSRTC) Developer Guide#

This guide helps you plan, configure, and validate the System Real-Time Clock (SYSRTC) on SiWx917 devices.

Power-State Reference#

The following table summarizes SYSRTC behavior in each power state. Power state (PS) values refer to device-wide power modes.

Note:

• SYSRTC runs across all power states. For power-state compatibility and clock-stability details, see Low-power Integration.

• When FreeRTOS low-power mode (Tickless Mode) is enabled, the Sleep Timer Service is configured to support FreeRTOS tick timing. This service uses the SYSRTC driver to maintain the OS tick count during sleep. As a result, SYSRTC is reserved for OS timekeeping and cannot be used as a general-purpose peripheral in this mode.

Overview#

The SYSRTC is a low-frequency timer and counter designed for accurate timekeeping, low-power wake scheduling, general-purpose input/output (GPIO) waveform generation, and event timestamping. Its multi-group architecture allows multiple applications to share a common counter while maintaining independent compare, capture, and control functionality.

Key design principles#

The SYSRTC is built around three key design principles:

1. Power efficiency:
   A shared-counter architecture minimizes power consumption while maintaining functionality across different power states.

2. Timing accuracy:
   Operates from a 32 kHz reference clock with configurable division factors to meet diverse timing precision requirements.

3. Flexibility:
   Multiple independent groups enable concurrent timing operations without resource conflicts, supporting versatile use cases in low-power systems.

System integration#

The SYSRTC integrates seamlessly with other subsystems on the Si91x device to ensure accurate timekeeping and efficient low-power operation:

• Power management:
  Operates continuously across PS4, PS2, PS1, and PS0 power states, enabling reliable timing even in deep-sleep modes.

• Clock system:
  Runs in a dedicated low-frequency domain, independent of the main high-speed system clocks, to maintain stability and minimize jitter.

• Interrupts:
  Supports always-on interrupt handling, allowing the SYSRTC to trigger wake-up events or timestamp operations without requiring the CPU to remain active.

• GPIO integration:
  Provides direct pin routing for capture inputs and compare outputs, enabling precise external event timing.

What makes SYSRTC different#

All groups share a single 32-bit counter. This architecture lowers power, simplifies synchronization, and lets multiple timing workloads run in parallel without resource conflicts—ideal for complex embedded systems with concurrent timing needs.

Key Capabilities#

• Multi-group architecture: Two independent groups (0 and 1) with their own compare and capture channels.

• Shared counter: A single 32-bit counter drives all groups for efficiency and consistent timebase.

• Flexible clock sources: Supports a 32 kHz RC oscillator and 32 kHz crystal (XTAL) with configurable dividers.

• Sleep-mode operation: Continues running across low-power states (deep sleep included) for reliable wake scheduling.

• GPIO integration: Direct routing to GPIO for capture inputs and compare outputs (waveform generation).

• Interrupts: Per-group interrupt control for overflow, compare, and capture events.

• Debug support: Optional run-in-debug mode to keep timing active during development and test.

Note: For practical examples and integration tips, see Usage scenarios.

About this Guide#

Use this implementation-focused guide to go from initial setup to advanced multi-group operation and power management with SYSRTC. It includes practical examples, troubleshooting checklists, and best practices so you can deliver precise, low-power timekeeping with confidence.

Example Scenario#

You’re building an IoT device that must run several timing tasks concurrently:

• a 1-second heartbeat,

• a 100-ms sensor sampler, and

• a GPIO waveform for an external device.

With SYSRTC, you assign each function to its own group while sharing a single counter. The result: lower power, accurate timing, and continuous operation through sleep modes—without resource conflicts.

Audience#

This guide is written for firmware developers and system integrators who design timing-critical embedded systems on the Si91x platform. It is especially relevant for engineers working on battery-powered, multi-timing, or precision-synchronized applications such as IoT devices, industrial controls, medical instruments, and automotive systems.

Purpose#

This guide explains how to configure and operate the SYSRTC for precise timing in embedded applications. You’ll learn how to:

• Configure and select clock sources

• Set up multi-group timing for concurrent tasks

• Manage power-state transitions and wake-up scheduling

• Generate accurate GPIO waveforms and capture external events

• Validate timing accuracy through measurement and debugging tools

By following these steps, you can design energy-efficient, timing-reliable systems using SYSRTC on Si91x devices.

Scope#

This guide covers the following topics:

• The SYSRTC peripheral and its operating principles

• Driver application programming interfaces (APIs) in sl_si91x_sysrtc.h/.c

• Configuration parameters and usage options

• Example projects in examples/si91x_soc/peripheral/sl_si91x_sysrtc/

• Integration with power management, GPIO services, and the interrupt system