Clock Manager#

sl_si91x_m4_soc_clk_src_sel_t#

sl_si91x_m4_soc_clk_src_sel_t

Typedef to select the clock source for the M4 core in the Si91x SOC.

This typedef maps to the M4_SOC_CLK_SRC_SEL_T type, which defines the possible clock source selections for the M4 core. The clock source selection impacts the operating frequency and performance characteristics of the M4 processor within the Si91x SOC.

Users can configure the clock source to optimize power consumption or performance based on application requirements.

Note

• Ensure that the selected clock source is properly configured and stable before switching to avoid system instability.

sl_si91x_clock_manager_init#

sl_status_t sl_si91x_clock_manager_init (void )

Initializes the M4_SOC and other required clocks.

Returns

• sl_status_t Status code indicating the result:

  • SL_STATUS_OK - Success.

  • Corresponding error code on failure.

For more information on status codes, refer to SL STATUS DOCUMENTATION.

sl_si91x_clock_manager_m4_set_core_clk#

sl_status_t sl_si91x_clock_manager_m4_set_core_clk (M4_SOC_CLK_SRC_SEL_T clk_source, uint32_t pll_freq)

To configure the M4 core clock source and configure the PLL frequency if selected as source.

Returns

• sl_status_t Status code indicating the result:

  • SL_STATUS_OK - Success.

  • Corresponding error code on failure.

For more information on status codes, see SL STATUS DOCUMENTATION.

sl_si91x_clock_manager_set_pll_freq#

sl_status_t sl_si91x_clock_manager_set_pll_freq (PLL_TYPE_T pll_type, uint32_t pll_freq, uint32_t pll_ref_clk)

To set the selected PLL (Phase-Locked Loop) clock to the desired frequency.

Returns

• sl_status_t Status code indicating the result:

  • SL_STATUS_OK - Success.

  • Corresponding error code on failure.

For more information on status codes, see SL STATUS DOCUMENTATION.

sl_si91x_clock_manager_m4_get_core_clk_src_freq#

sl_si91x_m4_soc_clk_src_sel_t sl_si91x_clock_manager_m4_get_core_clk_src_freq (uint32_t * m4_core_clk_freq)

To read the currently active M4 core clock source and its frequency.

Returns

• sl_si91x_m4_soc_clk_src_sel_t The currently active core clock source:

  • 0: M4_ULPREFCLK

  • 2: M4_SOCPLLCLK

  • 3: M4_MODEMPLLCLK1

  • 4: M4_INTFPLLCLK

  • 5: M4_SLEEPCLK

sl_si91x_clock_manager_get_pll_freq#

uint32_t sl_si91x_clock_manager_get_pll_freq (PLL_TYPE_T pll_type)

Gets the selected PLL (Phase-Locked Loop) clock to the desired frequency.

Returns

• uint32_t PLL frequency value in MHz.

sl_si91x_clock_manager_control_pll#

sl_status_t sl_si91x_clock_manager_control_pll (PLL_TYPE_T pll_type, bool enable)

Controls the selected PLL (Phase-Locked Loop) clock.

Returns

• sl_status_t Status code indicating the result:

  • SL_STATUS_OK - Success.

  • Corresponding error code on failure.

For more information on status codes, see SL STATUS DOCUMENTATION.

sl_si91x_delay_ms#

void sl_si91x_delay_ms (uint32_t milli_seconds)

Delays execution for the specified number of milliseconds.

Note

• This function provides a blocking delay.The delay is calibrated based on the SystemCoreClock frequency. If SystemCoreClock < CLOCK_THRESHOLD, the delay is calibrated with a division factor of LOW_FREQ_CLK_DIV_FAC. If SystemCoreClock >= CLOCK_THRESHOLD, the delay is calibrated with a division factor of HIGH_FREQ_CLK_DIV_FAC. This function uses __NOP() instructions for the delay loop.

For more information on status codes, see SL STATUS DOCUMENTATION.

PLL_REF_CLK_VAL_XTAL#

#define PLL_REF_CLK_VAL_XTAL

(40000000UL)

PLL reference clock frequency value of XTAL CLK.