EUSART_SpiAdvancedInit_TypeDef Struct Reference
SPI Advanced initialization structure.
#include <em_eusart.h>
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| EUSART_CsPolarity_TypeDef | csPolarity |
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Chip select polarity.
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| EUSART_InvertIO_TypeDef | invertIO |
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Enable inversion of RX and/or TX signals.
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| bool | autoCsEnable |
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Enable automatic chip select. CS is managed by the peripheral.
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| bool | msbFirst |
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If true, data will be send with most significant bit first.
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| uint8_t | autoCsSetupTime |
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Auto CS setup time (before transmission) in baud cycles. Acceptable value ( 0 to 7 baud cycle).
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| uint8_t | autoCsHoldTime |
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Auto CS hold time (after transmission) in baud cycles. Acceptable value ( 0 to 7 baud cycle).
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| uint8_t | autoInterFrameTime |
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Inter-frame time in baud cycles. Acceptable value ( 0 to 7 baud cycle).
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| bool | autoTxEnable |
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Enable AUTOTX mode.
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| uint16_t | defaultTxData |
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Default transmitted data when the TXFIFO is empty.
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| bool | dmaWakeUpOnRx |
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Enable the automatic wake up from EM2 to EM1 for DMA RX operation.
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| bool | prsRxEnable |
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Enable EUSART capability to use a PRS channel as an input data line for the receiver.
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| EUSART_PrsChannel_TypeDef | prsRxChannel |
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PRS Channel used to transmit data from PRS to the EUSART.
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| bool | prsClockEnable |
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Enable EUSART capability to use a PRS channel as an input SPI Clock.
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| EUSART_PrsChannel_TypeDef | prsClockChannel |
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PRS Channel used to transmit SCLK from PRS to the EUSART.
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| EUSART_RxFifoWatermark_TypeDef | RxFifoWatermark |
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Interrupt and status level of the Receive FIFO.
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| EUSART_TxFifoWatermark_TypeDef | TxFifoWatermark |
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Interrupt and status level of the Receive FIFO.
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| bool | forceLoad |
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Force load the first FIFO value.
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| uint8_t | setupWindow |
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Setup window in bus clock cycles before the sampling edge of SCLK at word-boundary to avoid force load error.
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SPI Advanced initialization structure.
Field Documentation
◆ csPolarity
| EUSART_CsPolarity_TypeDef EUSART_SpiAdvancedInit_TypeDef::csPolarity |
Chip select polarity.
◆ invertIO
| EUSART_InvertIO_TypeDef EUSART_SpiAdvancedInit_TypeDef::invertIO |
Enable inversion of RX and/or TX signals.
◆ autoCsEnable
| bool EUSART_SpiAdvancedInit_TypeDef::autoCsEnable |
Enable automatic chip select. CS is managed by the peripheral.
◆ msbFirst
| bool EUSART_SpiAdvancedInit_TypeDef::msbFirst |
If true, data will be send with most significant bit first.
◆ autoCsSetupTime
| uint8_t EUSART_SpiAdvancedInit_TypeDef::autoCsSetupTime |
Auto CS setup time (before transmission) in baud cycles. Acceptable value ( 0 to 7 baud cycle).
◆ autoCsHoldTime
| uint8_t EUSART_SpiAdvancedInit_TypeDef::autoCsHoldTime |
Auto CS hold time (after transmission) in baud cycles. Acceptable value ( 0 to 7 baud cycle).
◆ autoInterFrameTime
| uint8_t EUSART_SpiAdvancedInit_TypeDef::autoInterFrameTime |
Inter-frame time in baud cycles. Acceptable value ( 0 to 7 baud cycle).
◆ autoTxEnable
| bool EUSART_SpiAdvancedInit_TypeDef::autoTxEnable |
Enable AUTOTX mode.
Transmits as long as the RX FIFO is not full. Generates underflow interrupt if the TX FIFO is empty.
◆ defaultTxData
| uint16_t EUSART_SpiAdvancedInit_TypeDef::defaultTxData |
Default transmitted data when the TXFIFO is empty.
◆ dmaWakeUpOnRx
| bool EUSART_SpiAdvancedInit_TypeDef::dmaWakeUpOnRx |
Enable the automatic wake up from EM2 to EM1 for DMA RX operation.
Only applicable to EM2 (low frequency) capable EUSART instances.
◆ prsRxEnable
| bool EUSART_SpiAdvancedInit_TypeDef::prsRxEnable |
Enable EUSART capability to use a PRS channel as an input data line for the receiver.
The configured RX GPIO signal won't be routed to the EUSART receiver.
◆ prsRxChannel
| EUSART_PrsChannel_TypeDef EUSART_SpiAdvancedInit_TypeDef::prsRxChannel |
PRS Channel used to transmit data from PRS to the EUSART.
◆ prsClockEnable
| bool EUSART_SpiAdvancedInit_TypeDef::prsClockEnable |
Enable EUSART capability to use a PRS channel as an input SPI Clock.
Slave mode only.
◆ prsClockChannel
| EUSART_PrsChannel_TypeDef EUSART_SpiAdvancedInit_TypeDef::prsClockChannel |
PRS Channel used to transmit SCLK from PRS to the EUSART.
◆ RxFifoWatermark
| EUSART_RxFifoWatermark_TypeDef EUSART_SpiAdvancedInit_TypeDef::RxFifoWatermark |
Interrupt and status level of the Receive FIFO.
◆ TxFifoWatermark
| EUSART_TxFifoWatermark_TypeDef EUSART_SpiAdvancedInit_TypeDef::TxFifoWatermark |
Interrupt and status level of the Receive FIFO.
◆ forceLoad
| bool EUSART_SpiAdvancedInit_TypeDef::forceLoad |
Force load the first FIFO value.
◆ setupWindow
| uint8_t EUSART_SpiAdvancedInit_TypeDef::setupWindow |
Setup window in bus clock cycles before the sampling edge of SCLK at word-boundary to avoid force load error.