An SPI driver instance initialization structure.
Contains a number of SPIDRV configuration options. This structure is passed to SPIDRV_Init() when initializing a SPIDRV instance. Some common initialization data sets are predefined in Init Configuration Data.
Public Attributes#
The USART used for SPI.
Tx port.
Rx port.
Clock port.
Chip select port.
Tx pin.
Rx pin.
Clock pin.
Chip select pin.
An SPI bitrate.
An SPI framelength, valid numbers are 4..16.
The value to transmit when using SPI receive API functions.
An SPI type, master or slave.
A bit order on the SPI bus, MSB or LSB first.
SPI mode, CLKPOL/CLKPHASE setting.
A select master mode chip select (CS) control scheme.
A slave mode transfer start scheme.
Public Attribute Documentation#
port#
void* SPIDRV_Init_t::port
The USART used for SPI.
159 of file platform/emdrv/spidrv/inc/spidrv.hportTx#
sl_gpio_port_t SPIDRV_Init_t::portTx
Tx port.
166 of file platform/emdrv/spidrv/inc/spidrv.hportRx#
sl_gpio_port_t SPIDRV_Init_t::portRx
Rx port.
167 of file platform/emdrv/spidrv/inc/spidrv.hportClk#
sl_gpio_port_t SPIDRV_Init_t::portClk
Clock port.
168 of file platform/emdrv/spidrv/inc/spidrv.hportCs#
sl_gpio_port_t SPIDRV_Init_t::portCs
Chip select port.
169 of file platform/emdrv/spidrv/inc/spidrv.hpinTx#
uint8_t SPIDRV_Init_t::pinTx
Tx pin.
171 of file platform/emdrv/spidrv/inc/spidrv.hpinRx#
uint8_t SPIDRV_Init_t::pinRx
Rx pin.
172 of file platform/emdrv/spidrv/inc/spidrv.hpinClk#
uint8_t SPIDRV_Init_t::pinClk
Clock pin.
173 of file platform/emdrv/spidrv/inc/spidrv.hpinCs#
uint8_t SPIDRV_Init_t::pinCs
Chip select pin.
174 of file platform/emdrv/spidrv/inc/spidrv.hbitRate#
uint32_t SPIDRV_Init_t::bitRate
An SPI bitrate.
175 of file platform/emdrv/spidrv/inc/spidrv.hframeLength#
uint32_t SPIDRV_Init_t::frameLength
An SPI framelength, valid numbers are 4..16.
176 of file platform/emdrv/spidrv/inc/spidrv.hdummyTxValue#
uint32_t SPIDRV_Init_t::dummyTxValue
The value to transmit when using SPI receive API functions.
177 of file platform/emdrv/spidrv/inc/spidrv.htype#
SPIDRV_Type_t SPIDRV_Init_t::type
An SPI type, master or slave.
178 of file platform/emdrv/spidrv/inc/spidrv.hbitOrder#
SPIDRV_BitOrder_t SPIDRV_Init_t::bitOrder
A bit order on the SPI bus, MSB or LSB first.
179 of file platform/emdrv/spidrv/inc/spidrv.hclockMode#
SPIDRV_ClockMode_t SPIDRV_Init_t::clockMode
SPI mode, CLKPOL/CLKPHASE setting.
180 of file platform/emdrv/spidrv/inc/spidrv.hcsControl#
SPIDRV_CsControl_t SPIDRV_Init_t::csControl
A select master mode chip select (CS) control scheme.
181 of file platform/emdrv/spidrv/inc/spidrv.hslaveStartMode#
SPIDRV_SlaveStart_t SPIDRV_Init_t::slaveStartMode
A slave mode transfer start scheme.
182 of file platform/emdrv/spidrv/inc/spidrv.h