Asynchronous mode initialization structure.
Public Attributes#
Specifies whether TX and/or RX is enabled when initialization is completed.
USART/UART reference clock assumed when configuring baud rate setup.
Desired baud rate.
Oversampling used.
Number of data bits in frame.
Parity mode to use.
Number of stop bits to use.
Majority Vote Disable for 16x, 8x and 6x oversampling modes.
Enable USART Rx via PRS.
Select PRS channel for USART Rx.
Auto CS enabling.
Enable CS invert.
Auto CS hold time in baud cycles.
Auto CS setup time in baud cycles.
Hardware flow control mode.
Public Attribute Documentation#
enable#
USART_Enable_TypeDef USART_InitAsync_TypeDef::enable
Specifies whether TX and/or RX is enabled when initialization is completed.
refFreq#
uint32_t USART_InitAsync_TypeDef::refFreq
USART/UART reference clock assumed when configuring baud rate setup.
Set to 0 to use the currently configured reference clock.
databits#
USART_Databits_TypeDef USART_InitAsync_TypeDef::databits
Number of data bits in frame.
Notice that UART modules only support 8 or 9 data bits.
mvdis#
bool USART_InitAsync_TypeDef::mvdis
Majority Vote Disable for 16x, 8x and 6x oversampling modes.
prsRxCh#
USART_PRS_Channel_t USART_InitAsync_TypeDef::prsRxCh
Select PRS channel for USART Rx.
(Only valid if prsRxEnable is true).
csInv#
bool USART_InitAsync_TypeDef::csInv
Enable CS invert.
By default, chip select is active low. Set to true to make chip select active high.
hwFlowControl#
USART_HwFlowControl_TypeDef USART_InitAsync_TypeDef::hwFlowControl
Hardware flow control mode.