CMU - Clock Management Unit#

CMU_HFRCODPLLFreq_TypeDef#

CMU_HFRCODPLLFreq_TypeDef

HFRCODPLL frequency bands.

CMU_HFRCOEM23Freq_TypeDef#

CMU_HFRCOEM23Freq_TypeDef

HFRCOEM23 frequency bands.

CMU_Clock_TypeDef#

CMU_Clock_TypeDef

Clock points in CMU clock-tree.

CMU_Osc_TypeDef#

CMU_Osc_TypeDef

Oscillator types.

CMU_Select_TypeDef#

CMU_Select_TypeDef

Selectable clock sources.

CMU_DPLLEdgeSel_TypeDef#

CMU_DPLLEdgeSel_TypeDef

DPLL reference clock edge detect selector.

CMU_DPLLLockMode_TypeDef#

CMU_DPLLLockMode_TypeDef

DPLL lock mode selector.

CMU_LfxoOscMode_TypeDef#

CMU_LfxoOscMode_TypeDef

LFXO oscillator modes.

CMU_LfxoStartupDelay_TypeDef#

CMU_LfxoStartupDelay_TypeDef

LFXO start-up timeout delay.

CMU_HfxoOscMode_TypeDef#

CMU_HfxoOscMode_TypeDef

HFXO oscillator modes.

CMU_HfxoCbLsbTimeout_TypeDef#

CMU_HfxoCbLsbTimeout_TypeDef

HFXO core bias LSB change timeout.

CMU_HfxoSteadyStateTimeout_TypeDef#

CMU_HfxoSteadyStateTimeout_TypeDef

HFXO steady state timeout.

CMU_HfxoCoreDegen_TypeDef#

CMU_HfxoCoreDegen_TypeDef

HFXO core degeneration control.

CMU_HfxoCtuneFixCap_TypeDef#

CMU_HfxoCtuneFixCap_TypeDef

HFXO XI and XO pin fixed capacitor control.

CMU_Precision_TypeDef#

CMU_Precision_TypeDef

Oscillator precision modes.

CMU_BufoutTimeoutStartup_TypeDef#

CMU_BufoutTimeoutStartup_TypeDef

Crystal sharing timeout start up timeout.

CMU_PRS_Status_Output_Select_TypeDef#

CMU_PRS_Status_Output_Select_TypeDef

PRS status select output signal.

CMU_ClkDiv_TypeDef#

typedef uint32_t CMU_ClkDiv_TypeDef

Clock divider configuration.

CMU_Calibrate#

uint32_t CMU_Calibrate (uint32_t cycles, CMU_Select_TypeDef ref)

Calibrate an oscillator.

Run a calibration of a selectable reference clock againt HCLK. Please refer to the reference manual, CMU chapter, for further details.

Note

• This function will not return until calibration measurement is completed.

Returns

• The number of ticks the selected reference clock ticked while running cycles ticks of the HCLK clock.

CMU_CalibrateConfig#

void CMU_CalibrateConfig (uint32_t downCycles, CMU_Select_TypeDef downSel, CMU_Select_TypeDef upSel)

Configure clock calibration.

Configure a calibration for a selectable clock source against another selectable reference clock. Refer to the reference manual, CMU chapter, for further details.

Note

• After configuration, a call to CMU_CalibrateStart() is required, and the resulting calibration value can be read with the CMU_CalibrateCountGet() function call.

CMU_CalibrateCountGet#

uint32_t CMU_CalibrateCountGet (void )

Get calibration count value.

Note

• If continuous calibration mode is active, calibration busy will almost always be off, and reading the value will be just needed, where the normal case would be that this function call has been triggered by the CALRDY interrupt flag.

Returns

• Calibration count, the number of UPSEL clocks (see CMU_CalibrateConfig()) in the period of DOWNSEL oscillator clock cycles configured by a previous write operation to CMU->CALCNT.

CMU_ClkOutPinConfig#

void CMU_ClkOutPinConfig (uint32_t clkNo, CMU_Select_TypeDef sel, CMU_ClkDiv_TypeDef clkDiv, GPIO_Port_TypeDef port, unsigned int pin)

Direct a clock to a GPIO pin.

Note

• Refer to the reference manual and the datasheet for details on which GPIO port/pins that are available.

CMU_ClockDivGet#

CMU_ClkDiv_TypeDef CMU_ClockDivGet (CMU_Clock_TypeDef clock)

Get clock divisor.

Returns

• The current clock point divisor. 1 is returned if clock specifies a clock point without divisor.

CMU_ClockDivSet#

void CMU_ClockDivSet (CMU_Clock_TypeDef clock, CMU_ClkDiv_TypeDef div)

Set clock divisor.

CMU_ClockEnable#

void CMU_ClockEnable (CMU_Clock_TypeDef clock, bool enable)

Enable/disable a clock.

Module clocks sre disabled after reset. If a module clock is disabled, the registers of that module are not accessible and accessing such registers will hardfault the Cortex core.

CMU_ClockFreqGet#

uint32_t CMU_ClockFreqGet (CMU_Clock_TypeDef clock)

Get clock frequency for a clock point.

Returns

• The current frequency in Hz.

CMU_ClockSelectGet#

CMU_Select_TypeDef CMU_ClockSelectGet (CMU_Clock_TypeDef clock)

Get currently selected reference clock used for a clock branch.

Returns

• Reference clock used for clocking selected branch, cmuSelect_Error if invalid clock provided.

CMU_ClockSelectSet#

void CMU_ClockSelectSet (CMU_Clock_TypeDef clock, CMU_Select_TypeDef ref)

Select reference clock/oscillator used for a clock branch.

CMU_LF_ClockPrecisionGet#

uint16_t CMU_LF_ClockPrecisionGet (CMU_Clock_TypeDef clock)

Gets the precision (in PPM) of the specified low frequency clock branch.

Returns

• Precision, in PPM, of the specified clock branch.

Note

• This function is only for internal usage.

• The current implementation of this function is used to determine if the clock has a precision <= 500 ppm or not (which is the minimum required for BLE). Future version of this function should provide more accurate precision numbers to allow for further optimizations from the stacks.

CMU_HF_ClockPrecisionGet#

uint16_t CMU_HF_ClockPrecisionGet (CMU_Clock_TypeDef clock)

Gets the precision (in PPM) of the specified high frequency clock branch.

Returns

• Precision, in PPM, of the specified clock branch.

Note

• This function is only for internal usage.

• The current implementation of this function is used to determine if the clock has a precision <= 500 ppm or not (which is the minimum required for BLE). Future version of this function should provide more accurate precision numbers to allow for further optimizations from the stacks.

CMU_HFRCODPLLBandGet#

CMU_HFRCODPLLFreq_TypeDef CMU_HFRCODPLLBandGet (void )

Get HFRCODPLL band in use.

Returns

• HFRCODPLL band in use.

CMU_HFRCODPLLBandSet#

void CMU_HFRCODPLLBandSet (CMU_HFRCODPLLFreq_TypeDef freq)

Set HFRCODPLL band and the tuning value based on the value in the calibration table made during production.

CMU_DPLLLock#

bool CMU_DPLLLock (const CMU_DPLLInit_TypeDef * init)

Lock the DPLL to a given frequency.

The frequency is given by: Fout = Fref * (N+1) / (M+1).

Note

• This function does not check if the given N & M values will actually produce the desired target frequency.
  N & M limitations:
  300 < N <= 4095
  0 <= M <= 4095
  Any peripheral running off HFRCODPLL should be switched to a lower frequency clock (if possible) prior to calling this function to avoid over-clocking.

Returns

• Returns false on invalid target frequency or DPLL locking error.

CMU_HFXOInit#

void CMU_HFXOInit (const CMU_HFXOInit_TypeDef * hfxoInit)

Initialize all HFXO control registers.

Note

• HFXO configuration should be obtained from a configuration tool, app note or crystal datasheet. This function returns early if HFXO is already selected as SYSCLK.

CMU_HFXOStartCrystalSharingLeader#

void CMU_HFXOStartCrystalSharingLeader (const CMU_BUFOUTLeaderInit_TypeDef * bufoutInit, GPIO_Port_TypeDef port, unsigned int pin)

Initialize HFXO Bufout (Crystal sharing) leader control registers.

Configure the bufout request input GPIO as a clock request signal to add the crystal sharing follower chip as a source of clock request.

Warnings

• If EM2 capabilities are needed, a GPIO that fully retains its capabilities while in EM2 must be selected.

CMU_HFXOCrystalSharingFollowerInit#

void CMU_HFXOCrystalSharingFollowerInit (CMU_PRS_Status_Output_Select_TypeDef prsStatusSelectOutput, unsigned int prsAsyncCh, GPIO_Port_TypeDef port, unsigned int pin)

Initialize HFXO Bufout (Crystal sharing) follower control registers.

Configure the clock request signal to a specified GPIO to automatically request the high frequency crystal oscillator sine wave clock. This function must be used in conjunction with CMU_HFXOInit() configured with EXTERNAL_SINE or EXTERNAL_SINEPKDET mode.

Warnings

• If EM2 capabilities are needed, a GPIO that fully retains its capabilities while in EM2 must be selected.

Note

• This function can be emulated on XG21/XG22 chips by controlling the clock request GPIO to ask the crystal sharing leader clock when needed.

CMU_HFXOCTuneSet#

sl_status_t CMU_HFXOCTuneSet (uint32_t ctune)

Set the HFXO crystal tuning capacitance.

Returns

• SL_STATUS_OK if initialization parameter is valid. SL_STATUS_INVALID_PARAMETER if initialization parameter is invalid.

Note

• While the oscillator is running in steady operation state, it may be desirable to modify the tuning capacitance via CTUNEXIANA and CTUNEXOANA fields in the HFXO_XTALCTRL register. When tuning, care should be taken to make small changes to the CTUNE registers. Ideally, change the CTUNE registers by one LSB at a time and alternate between the XI and XO registers. Sufficient wait time for settling, on the order of TIMEOUTSTEADY, should pass before new frequency measurement is taken.

CMU_HFXOCTuneGet#

uint32_t CMU_HFXOCTuneGet (void )

Get the HFXO crystal tuning capacitance.

Returns

• The HFXO crystal tuning capacitance.

Note

• This function only returns the CTUNE XI value. The XO value can be different and can be found using the delta (difference between XI and XO). See CMU_HFXOCTuneCurrentDeltaGet to retrieve the delta value.

CMU_HFXOCTuneDeltaSet#

void CMU_HFXOCTuneDeltaSet (int32_t delta)

Set the HFXO crystal tuning delta.

Note

• The delta between XI and XO is applicable for the series 2 EFR32xG2x devices only. Neither XI nor XO is actually modified by this function, CMU_HFXOCTuneSet() needs to be called for the change to be propagated.

CMU_HFXOCTuneDeltaGet#

int32_t CMU_HFXOCTuneDeltaGet (void )

Get the HFXO crystal tuning delta.

It can be default recommended delta value or value set by CMU_HFXOCTuneDeltaSet.

Returns

• Chip dependent crystal capacitor bank tuning delta.

CMU_HFXOCTuneCurrentDeltaGet#

int32_t CMU_HFXOCTuneCurrentDeltaGet (void )

Get the current delta between HFXO XI and XO.

Returns

• the current delta between HFXO XI and XO.

CMU_HFXOCoreBiasCurrentCalibrate#

void CMU_HFXOCoreBiasCurrentCalibrate (void )

Recalibrate the HFXO's Core Bias Current.

Note

• Care should be taken when using this function as it can cause disturbance on the HFXO frequency while the optimization is underway. It's recommended to only use this function when HFXO isn't being used. It's also a blocking function that can be time consuming.

CMU_LFXOInit#

void CMU_LFXOInit (const CMU_LFXOInit_TypeDef * lfxoInit)

Initialize LFXO control registers.

Note

• LFXO configuration should be obtained from a configuration tool, app note or crystal datasheet. This function disables the LFXO to ensure a valid state before update.

CMU_LFXOPrecisionSet#

void CMU_LFXOPrecisionSet (uint16_t precision)

Sets LFXO's crystal precision, in PPM.

Note

• LFXO precision should be obtained from a crystal datasheet.

CMU_LFXOPrecisionGet#

uint16_t CMU_LFXOPrecisionGet (void )

Gets LFXO's crystal precision, in PPM.

CMU_HFXOPrecisionSet#

void CMU_HFXOPrecisionSet (uint16_t precision)

Sets HFXO's crystal precision, in PPM.

Note

• HFXO precision should be obtained from a crystal datasheet.

CMU_HFXOPrecisionGet#

uint16_t CMU_HFXOPrecisionGet (void )

Gets HFXO's crystal precision, in PPM.

CMU_OscillatorTuningGet#

uint32_t CMU_OscillatorTuningGet (CMU_Osc_TypeDef osc)

Get oscillator frequency tuning setting.

Returns

• The oscillator frequency tuning setting in use.

CMU_OscillatorTuningSet#

void CMU_OscillatorTuningSet (CMU_Osc_TypeDef osc, uint32_t val)

Set the oscillator frequency tuning control.

Note

• Oscillator tuning is done during production, and the tuning value is automatically loaded after a reset. Changing the tuning value from the calibrated value is for more advanced use. Certain oscillators also have build-in tuning optimization.

CMU_UpdateWaitStates#

void CMU_UpdateWaitStates (uint32_t freq, int vscale)

Configure wait state settings necessary to switch to a given core clock frequency at a certain voltage scale level.

This function will set up the necessary flash wait states. Updating the wait state configuration must be done before increasing the clock frequency and it must be done after decreasing the clock frequency. Updating the wait state configuration must be done before core voltage is decreased and it must be done after a core voltage is increased.

CMU_PCNTClockExternalSet#

void CMU_PCNTClockExternalSet (unsigned int instance, bool external)

Select the PCNTn clock.

CMU_HFRCOEM23BandGet#

CMU_HFRCOEM23Freq_TypeDef CMU_HFRCOEM23BandGet (void )

Get HFRCOEM23 band in use.

Returns

• HFRCOEM23 band in use.

CMU_HFRCOEM23BandSet#

void CMU_HFRCOEM23BandSet (CMU_HFRCOEM23Freq_TypeDef freq)

Set HFRCOEM23 band and the tuning value based on the value in the calibration table made during production.

CMU_CalibrateCont#

void CMU_CalibrateCont (bool enable)

Configure continuous calibration mode.

CMU_CalibrateStart#

void CMU_CalibrateStart (void )

Start calibration.

Note

• This call is usually invoked after CMU_CalibrateConfig() and possibly CMU_CalibrateCont().

CMU_CalibrateStop#

void CMU_CalibrateStop (void )

Stop calibration counters.

CMU_DPLLUnlock#

void CMU_DPLLUnlock (void )

Unlock the DPLL.

Note

• The HFRCODPLL oscillator is not turned off.

CMU_IntClear#

void CMU_IntClear (uint32_t flags)

Clear one or more pending CMU interrupt flags.

CMU_IntDisable#

void CMU_IntDisable (uint32_t flags)

Disable one or more CMU interrupt sources.

CMU_IntEnable#

void CMU_IntEnable (uint32_t flags)

Enable one or more CMU interrupt sources.

Note

• Depending on the use, a pending interrupt may already be set prior to enabling the interrupt. Consider using CMU_IntClear() prior to enabling if such a pending interrupt should be ignored.

CMU_IntGet#

uint32_t CMU_IntGet (void )

Get pending CMU interrupt sources.

Returns

• CMU interrupt sources pending.

CMU_IntGetEnabled#

uint32_t CMU_IntGetEnabled (void )

Get enabled and pending CMU interrupt flags.

Useful for handling more interrupt sources in the same interrupt handler.

Note

• The event bits are not cleared by the use of this function.

Returns

• Pending and enabled CMU interrupt sources. The return value is the bitwise AND of

  • the enabled interrupt sources in CMU_IEN and

  • the pending interrupt flags CMU_IF

CMU_IntSet#

void CMU_IntSet (uint32_t flags)

Set one or more pending CMU interrupt sources.

CMU_Lock#

void CMU_Lock (void )

Lock CMU register access in order to protect registers contents against unintended modification.

See the reference manual for CMU registers that will be locked.

Note

• If locking the CMU registers, they must be unlocked prior to using any CMU API functions modifying CMU registers protected by the lock.

CMU_OscillatorEnable#

void CMU_OscillatorEnable (CMU_Osc_TypeDef osc, bool enable, bool wait)

Enable/disable oscillator.

Note

• This is a dummy function to solve backward compatibility issues.

CMU_Unlock#

void CMU_Unlock (void )

Unlock CMU register access so that writing to registers is possible.

CMU_WdogLock#

void CMU_WdogLock (void )

Lock WDOG register access in order to protect registers contents against unintended modification.

Note

• If locking the WDOG registers, they must be unlocked prior to using any emlib API functions modifying registers protected by the lock.

CMU_WdogUnlock#

void CMU_WdogUnlock (void )

Unlock WDOG register access so that writing to registers is possible.

CMU_PrescToLog2#

uint32_t CMU_PrescToLog2 (uint32_t presc)

Convert prescaler divider to a logarithmic value.

It only works for even numbers equal to 2^n.

Returns

• Logarithm base 2 (binary) value, i.e. exponent as used by fixed 2^n prescalers.

CMU_CLOCK_SELECT_SET#

#define CMU_CLOCK_SELECT_SET

(clock, sel)

Macro to set clock sources in the clock tree.

_CMU_EM01GRPACLKCTRL_CLKSEL_DISABLED#

#define _CMU_EM01GRPACLKCTRL_CLKSEL_DISABLED

0x00000000UL

Disable clocks configuration.

Mode DISABLED for CMU_EM01GRPACLKCTRL

CMU_EM01GRPACLKCTRL_CLKSEL_DISABLED#

#define CMU_EM01GRPACLKCTRL_CLKSEL_DISABLED

(_CMU_EM01GRPACLKCTRL_CLKSEL_DISABLED  << 0)

Shifted mode DISABLED for CMU_EM01GRPACLKCTRL.

_CMU_EM01GRPBCLKCTRL_CLKSEL_DISABLED#

#define _CMU_EM01GRPBCLKCTRL_CLKSEL_DISABLED

0x00000000UL

Mode DISABLED for CMU_EM01GRPBCLKCTRL

CMU_EM01GRPBCLKCTRL_CLKSEL_DISABLED#

#define CMU_EM01GRPBCLKCTRL_CLKSEL_DISABLED

(_CMU_EM01GRPBCLKCTRL_CLKSEL_DISABLED  << 0)

Shifted mode DISABLED for CMU_EM01GRPBCLKCTRL.

_CMU_EM23GRPACLKCTRL_CLKSEL_DISABLED#

#define _CMU_EM23GRPACLKCTRL_CLKSEL_DISABLED

0x00000000UL

Mode DISABLED for CMU_EM23GRPACLKCTRL

CMU_EM23GRPACLKCTRL_CLKSEL_DISABLED#

#define CMU_EM23GRPACLKCTRL_CLKSEL_DISABLED

(_CMU_EM23GRPACLKCTRL_CLKSEL_DISABLED << 0)

Shifted mode DISABLED for CMU_EM23GRPACLKCTRL.

_CMU_EM4GRPACLKCTRL_CLKSEL_DISABLED#

#define _CMU_EM4GRPACLKCTRL_CLKSEL_DISABLED

0x00000000UL

Mode DISABLED for CMU_EM4GRPACLKCTRL

CMU_EM4GRPACLKCTRL_CLKSEL_DISABLED#

#define CMU_EM4GRPACLKCTRL_CLKSEL_DISABLED

(_CMU_EM4GRPACLKCTRL_CLKSEL_DISABLED << 0)

Shifted mode DISABLED for CMU_EM4GRPACLKCTRL.

_CMU_WDOG0CLKCTRL_CLKSEL_DISABLED#

#define _CMU_WDOG0CLKCTRL_CLKSEL_DISABLED

0x00000000UL

Mode DISABLED for CMU_WDOG0CLKCTRL

CMU_WDOG0CLKCTRL_CLKSEL_DISABLED#

#define CMU_WDOG0CLKCTRL_CLKSEL_DISABLED

(_CMU_WDOG0CLKCTRL_CLKSEL_DISABLED << 0)

Shifted mode DISABLED for CMU_WDOG0CLKCTRL

_CMU_WDOG1CLKCTRL_CLKSEL_DISABLED#

#define _CMU_WDOG1CLKCTRL_CLKSEL_DISABLED

0x00000000UL

Mode DISABLED for CMU_WDOG1CLKCTRL

CMU_WDOG1CLKCTRL_CLKSEL_DISABLED#

#define CMU_WDOG1CLKCTRL_CLKSEL_DISABLED

(_CMU_WDOG1CLKCTRL_CLKSEL_DISABLED << 0)

Shifted mode DISABLED for CMU_WDOG1CLKCTRL

_CMU_EUSART0CLKCTRL_CLKSEL_DISABLED#

#define _CMU_EUSART0CLKCTRL_CLKSEL_DISABLED

0x00000000UL

Mode DISABLED for CMU_EUSART0CLKCTRL

CMU_EUSART0CLKCTRL_CLKSEL_DISABLED#

#define CMU_EUSART0CLKCTRL_CLKSEL_DISABLED

(_CMU_EUSART0CLKCTRL_CLKSEL_DISABLED << 0)

Shifted mode DISABLED for CMU_EUSART0CLKCTRL.

_CMU_SYSRTC0CLKCTRL_CLKSEL_DISABLED#

#define _CMU_SYSRTC0CLKCTRL_CLKSEL_DISABLED

0x00000000UL

Mode DISABLED for CMU_SYSRTC0CLKCTRL

CMU_SYSRTC0CLKCTRL_CLKSEL_DISABLED#

#define CMU_SYSRTC0CLKCTRL_CLKSEL_DISABLED

(_CMU_SYSRTC0CLKCTRL_CLKSEL_DISABLED << 0)

Shifted mode DISABLED for CMU_SYSRTC0CLKCTRL.

CMU_HFRCODPLL_MIN#

#define CMU_HFRCODPLL_MIN

cmuHFRCODPLLFreq_1M0Hz

HFRCODPLL maximum frequency.

CMU_HFRCODPLL_MAX#

#define CMU_HFRCODPLL_MAX

cmuHFRCODPLLFreq_80M0Hz

HFRCODPLL minimum frequency.

CMU_HFRCOEM23_MIN#

#define CMU_HFRCOEM23_MIN

cmuHFRCOEM23Freq_1M0Hz

HFRCOEM23 maximum frequency.

CMU_HFRCOEM23_MAX#

#define CMU_HFRCOEM23_MAX

cmuHFRCOEM23Freq_40M0Hz

HFRCOEM23 minimum frequency.

CMU_LFXOINIT_DEFAULT#

#define CMU_LFXOINIT_DEFAULT

Default LFXO initialization values for XTAL mode.

CMU_LFXOINIT_EXTERNAL_CLOCK#

#define CMU_LFXOINIT_EXTERNAL_CLOCK

Default LFXO initialization values for external clock mode.

CMU_LFXOINIT_EXTERNAL_SINE#

#define CMU_LFXOINIT_EXTERNAL_SINE

Default LFXO initialization values for external sine mode.

CMU_HFXOINIT_CTUNEFIXANA_DEFAULT#

#define CMU_HFXOINIT_CTUNEFIXANA_DEFAULT

cmuHfxoCtuneFixCap_Xo

Default configuration of fixed tuning capacitance on XI or XO for EFR32XG23 and EFR32XG28.

CMU_HFXOINIT_DEFAULT#

#define CMU_HFXOINIT_DEFAULT

Default HFXO initialization values for XTAL mode.

CMU_HFXOINIT_EXTERNAL_SINE#

#define CMU_HFXOINIT_EXTERNAL_SINE

Default HFXO initialization values for external sine mode.

CMU_HFXOINIT_EXTERNAL_SINEPKDET#

#define CMU_HFXOINIT_EXTERNAL_SINEPKDET

Default HFXO initialization values for external sine mode with peak detector.

CMU_HFXO_CRYSTAL_INIT_LEADER_DEFAULT#

#define CMU_HFXO_CRYSTAL_INIT_LEADER_DEFAULT

Default crystal sharing master initialization values.

CMU_HFXO_CRYSTAL_INIT_Follower_DEFAULT#

#define CMU_HFXO_CRYSTAL_INIT_Follower_DEFAULT

Default crystal sharing follower initialization values.

CMU_DPLL_LFXO_TO_40MHZ#

#define CMU_DPLL_LFXO_TO_40MHZ

DPLL initialization values for 39,998,805 Hz using LFXO as reference clock, M=2 and N=3661.

CMU_DPLL_HFXO_TO_76_8MHZ#

#define CMU_DPLL_HFXO_TO_76_8MHZ

DPLL initialization values for 76,800,000 Hz using HFXO as reference clock, M = 1919, N = 3839.

CMU_DPLL_HFXO_TO_80MHZ#

#define CMU_DPLL_HFXO_TO_80MHZ

DPLL initialization values for 80,000,000 Hz using HFXO as reference clock, M = 1919, N = 3999.

CMU_DPLLINIT_DEFAULT#

#define CMU_DPLLINIT_DEFAULT

Default configurations for DPLL initialization.

When using this macro you need to modify the N and M factor and the desired frequency to match the components placed on the board.