IADC init structure, common for single conversion and scan sequence.
Public Attributes#
Suspend IADC_CLK when in scan mode until PRS trigger.
Suspend IADC_CLK when in single mode until PRS trigger.
Halt IADC during debug mode.
IADC warmup mode.
IADC clock cycles (timebase+1) corresponding to 1us.
User requested source clock divider (prescale+1) which will be used if the calculated prescaler value is less.
Number of ADC_CLK cycles per TIMER event.
Digital window comparator greater-than or equal threshold.
Digital window comparator less-than or equal threshold.
IADC configurations.
Public Attribute Documentation#
iadc_clk_suspend0#
bool sl_hal_iadc_init_t::iadc_clk_suspend0
Suspend IADC_CLK when in scan mode until PRS trigger.
iadc_clk_suspend1#
bool sl_hal_iadc_init_t::iadc_clk_suspend1
Suspend IADC_CLK when in single mode until PRS trigger.
timebase#
uint8_t sl_hal_iadc_init_t::timebase
IADC clock cycles (timebase+1) corresponding to 1us.
Used as time reference for IADC delays, e.g. warmup. If the user sets timebase to 0, then sl_hal_iadc_init() will calculate the timebase using the currently defined CMU clock setting for the IADC.
src_clk_prescale#
uint8_t sl_hal_iadc_init_t::src_clk_prescale
User requested source clock divider (prescale+1) which will be used if the calculated prescaler value is less.
greater_than_equal_thres#
uint16_t sl_hal_iadc_init_t::greater_than_equal_thres
Digital window comparator greater-than or equal threshold.
less_than_equal_thres#
uint16_t sl_hal_iadc_init_t::less_than_equal_thres
Digital window comparator less-than or equal threshold.