PartDevices > EFR32MG13P932F512GM48
Macros |
|
| #define | __CM4_REV 0x0001U |
| #define | _EFR32_MIGHTY_FAMILY 1 |
| #define | _EFR_DEVICE |
| #define | _SILICON_LABS_32B_PLATFORM 2 |
| #define | _SILICON_LABS_32B_PLATFORM_2 |
| #define | _SILICON_LABS_32B_PLATFORM_2_GEN 3 |
| #define | _SILICON_LABS_32B_PLATFORM_2_GEN_3 |
| #define | _SILICON_LABS_32B_SERIES 1 |
| #define | _SILICON_LABS_32B_SERIES_1 |
| #define | _SILICON_LABS_32B_SERIES_1_CONFIG 3 |
| #define | _SILICON_LABS_32B_SERIES_1_CONFIG_3 |
| #define | _SILICON_LABS_EFR32_RADIO_2G4HZ 2 |
| #define | _SILICON_LABS_EFR32_RADIO_DUALBAND 3 |
| #define | _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 |
| #define | _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ |
| #define | _SILICON_LABS_GECKO_INTERNAL_SDID 89 |
| #define | _SILICON_LABS_GECKO_INTERNAL_SDID_89 |
| #define | ACMP_COUNT 2 |
| #define | ACMP_PRESENT |
| #define | ADC_COUNT 1 |
| #define | ADC_PRESENT |
| #define | AFACHAN_MAX 118U |
| #define | AFCHAN_MAX 118U |
| #define | AFCHANLOC_MAX 32U |
| #define | BITBAND_PER_BASE ((uint32_t) 0x42000000UL) |
| #define | BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) |
| #define | BOOTLOADER_COUNT 1 |
| #define | BOOTLOADER_PRESENT |
| #define | CMU_COUNT 1 |
| #define | CMU_PRESENT |
| #define | CRYOTIMER_COUNT 1 |
| #define | CRYOTIMER_PRESENT |
| #define | CRYPTO0_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) |
| #define | CRYPTO0_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) |
| #define | CRYPTO0_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) |
| #define | CRYPTO0_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) |
| #define | CRYPTO0_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) |
| #define | CRYPTO0_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) |
| #define | CRYPTO0_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) |
| #define | CRYPTO0_BITSET_MEM_SIZE ((uint32_t) 0x400UL) |
| #define | CRYPTO0_MEM_BASE ((uint32_t) 0x400F0000UL) |
| #define | CRYPTO0_MEM_BITS ((uint32_t) 0x0000000AUL) |
| #define | CRYPTO0_MEM_END ((uint32_t) 0x400F03FFUL) |
| #define | CRYPTO0_MEM_SIZE ((uint32_t) 0x400UL) |
| #define | CRYPTO1_BITCLR_MEM_BASE ((uint32_t) 0x440F0400UL) |
| #define | CRYPTO1_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) |
| #define | CRYPTO1_BITCLR_MEM_END ((uint32_t) 0x440F07FFUL) |
| #define | CRYPTO1_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) |
| #define | CRYPTO1_BITSET_MEM_BASE ((uint32_t) 0x460F0400UL) |
| #define | CRYPTO1_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) |
| #define | CRYPTO1_BITSET_MEM_END ((uint32_t) 0x460F07FFUL) |
| #define | CRYPTO1_BITSET_MEM_SIZE ((uint32_t) 0x400UL) |
| #define | CRYPTO1_MEM_BASE ((uint32_t) 0x400F0400UL) |
| #define | CRYPTO1_MEM_BITS ((uint32_t) 0x0000000AUL) |
| #define | CRYPTO1_MEM_END ((uint32_t) 0x400F07FFUL) |
| #define | CRYPTO1_MEM_SIZE ((uint32_t) 0x400UL) |
| #define | CRYPTO_BITCLR_MEM_BASE CRYPTO0_BITCLR_MEM_BASE |
| #define | CRYPTO_BITCLR_MEM_BITS CRYPTO0_BITCLR_MEM_BITS |
| #define | CRYPTO_BITCLR_MEM_END CRYPTO0_BITCLR_MEM_END |
| #define | CRYPTO_BITCLR_MEM_SIZE CRYPTO0_BITCLR_MEM_SIZE |
| #define | CRYPTO_BITSET_MEM_BASE CRYPTO0_BITSET_MEM_BASE |
| #define | CRYPTO_BITSET_MEM_BITS CRYPTO0_BITSET_MEM_BITS |
| #define | CRYPTO_BITSET_MEM_END CRYPTO0_BITSET_MEM_END |
| #define | CRYPTO_BITSET_MEM_SIZE CRYPTO0_BITSET_MEM_SIZE |
| #define | CRYPTO_COUNT 2 |
| #define | CRYPTO_MEM_BASE CRYPTO0_MEM_BASE |
| #define | CRYPTO_MEM_BITS CRYPTO0_MEM_BITS |
| #define | CRYPTO_MEM_END CRYPTO0_MEM_END |
| #define | CRYPTO_MEM_SIZE CRYPTO0_MEM_SIZE |
| #define | CRYPTO_PRESENT |
| #define | DCDC_COUNT 1 |
| #define | DCDC_PRESENT |
| #define | DMA_CHAN_COUNT 8 |
| #define | EMU_COUNT 1 |
| #define | EMU_PRESENT |
| #define | ETM_COUNT 1 |
| #define | ETM_PRESENT |
| #define | EXT_IRQ_COUNT 47 |
| #define | FLASH_BASE (0x00000000UL) |
| #define | FLASH_MEM_BASE ((uint32_t) 0x00000000UL) |
| #define | FLASH_MEM_BITS ((uint32_t) 0x0000001CUL) |
| #define | FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) |
| #define | FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) |
| #define | FLASH_PAGE_SIZE 2048U |
| #define | FLASH_SIZE (0x00080000UL) |
| #define | FPUEH_COUNT 1 |
| #define | FPUEH_PRESENT |
| #define | GPCRC_COUNT 1 |
| #define | GPCRC_PRESENT |
| #define | GPIO_COUNT 1 |
| #define | GPIO_PRESENT |
| #define | I2C_COUNT 2 |
| #define | I2C_PRESENT |
| #define | LDMA_COUNT 1 |
| #define | LDMA_PRESENT |
| #define | LESENSE_COUNT 1 |
| #define | LESENSE_PRESENT |
| #define | LETIMER_COUNT 1 |
| #define | LETIMER_PRESENT |
| #define | LEUART_COUNT 1 |
| #define | LEUART_PRESENT |
| #define | MSC_COUNT 1 |
| #define | MSC_PRESENT |
| #define | PART_NUMBER "EFR32MG13P932F512GM48" |
| #define | PCNT_COUNT 1 |
| #define | PCNT_PRESENT |
| #define | PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) |
| #define | PER_BITCLR_MEM_BITS ((uint32_t) 0x00000014UL) |
| #define | PER_BITCLR_MEM_END ((uint32_t) 0x440EFFFFUL) |
| #define | PER_BITCLR_MEM_SIZE ((uint32_t) 0xF0000UL) |
| #define | PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) |
| #define | PER_BITSET_MEM_BITS ((uint32_t) 0x00000014UL) |
| #define | PER_BITSET_MEM_END ((uint32_t) 0x460EFFFFUL) |
| #define | PER_BITSET_MEM_SIZE ((uint32_t) 0xF0000UL) |
| #define | PER_MEM_BASE ((uint32_t) 0x40000000UL) |
| #define | PER_MEM_BITS ((uint32_t) 0x00000014UL) |
| #define | PER_MEM_END ((uint32_t) 0x400EFFFFUL) |
| #define | PER_MEM_SIZE ((uint32_t) 0xF0000UL) |
| #define | PRS_CHAN_COUNT 12 |
| #define | PRS_COUNT 1 |
| #define | PRS_PRESENT |
| #define | RAM0_CODE_MEM_BASE ((uint32_t) 0x10000000UL) |
| #define | RAM0_CODE_MEM_BITS ((uint32_t) 0x0000000FUL) |
| #define | RAM0_CODE_MEM_END ((uint32_t) 0x10007FFFUL) |
| #define | RAM0_CODE_MEM_SIZE ((uint32_t) 0x8000UL) |
| #define | RAM1_CODE_MEM_BASE ((uint32_t) 0x10008000UL) |
| #define | RAM1_CODE_MEM_BITS ((uint32_t) 0x0000000FUL) |
| #define | RAM1_CODE_MEM_END ((uint32_t) 0x1000FFFFUL) |
| #define | RAM1_CODE_MEM_SIZE ((uint32_t) 0x8000UL) |
| #define | RAM1_MEM_BASE ((uint32_t) 0x20008000UL) |
| #define | RAM1_MEM_BITS ((uint32_t) 0x0000000FUL) |
| #define | RAM1_MEM_END ((uint32_t) 0x2000FFFFUL) |
| #define | RAM1_MEM_SIZE ((uint32_t) 0x8000UL) |
| #define | RAM2_CODE_MEM_BASE ((uint32_t) 0x10010000UL) |
| #define | RAM2_CODE_MEM_BITS ((uint32_t) 0x0000000BUL) |
| #define | RAM2_CODE_MEM_END ((uint32_t) 0x100107FFUL) |
| #define | RAM2_CODE_MEM_SIZE ((uint32_t) 0x800UL) |
| #define | RAM2_MEM_BASE ((uint32_t) 0x20010000UL) |
| #define | RAM2_MEM_BITS ((uint32_t) 0x0000000BUL) |
| #define | RAM2_MEM_END ((uint32_t) 0x200107FFUL) |
| #define | RAM2_MEM_SIZE ((uint32_t) 0x800UL) |
| #define | RAM_MEM_BASE ((uint32_t) 0x20000000UL) |
| #define | RAM_MEM_BITS ((uint32_t) 0x0000000FUL) |
| #define | RAM_MEM_END ((uint32_t) 0x20007FFFUL) |
| #define | RAM_MEM_SIZE ((uint32_t) 0x8000UL) |
| #define | RMU_COUNT 1 |
| #define | RMU_PRESENT |
| #define | RTCC_COUNT 1 |
| #define | RTCC_PRESENT |
| #define | SMU_COUNT 1 |
| #define | SMU_PRESENT |
| #define | SRAM_BASE (0x20000000UL) |
| #define | SRAM_SIZE (0x00010000UL) |
| #define | TIMER_COUNT 2 |
| #define | TIMER_PRESENT |
| #define | TRNG_COUNT 1 |
| #define | TRNG_PRESENT |
| #define | USART_COUNT 3 |
| #define | USART_PRESENT |
| #define | WDOG_COUNT 2 |
| #define | WDOG_PRESENT |
| #define | WTIMER_COUNT 1 |
| #define | WTIMER_PRESENT |
Macro Definition Documentation
| #define __CM4_REV 0x0001U |
Cortex-M4 Core revision r0p1
Definition at line
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| #define _EFR32_MIGHTY_FAMILY 1 |
Part family MIGHTY Gecko RF SoC Family
Definition at line
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| #define _EFR_DEVICE |
Silicon Labs EFR-type RF SoC
Definition at line
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| #define _SILICON_LABS_32B_PLATFORM 2 |
-
Deprecated: - Silicon Labs platform name
Definition at line
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| #define _SILICON_LABS_32B_PLATFORM_2 |
-
Deprecated: - Silicon Labs platform name
Definition at line
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| #define _SILICON_LABS_32B_PLATFORM_2_GEN 3 |
-
Deprecated: - Platform 2, generation 3
Definition at line
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| #define _SILICON_LABS_32B_PLATFORM_2_GEN_3 |
-
Deprecated: - Platform 2, generation 3
Definition at line
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| #define _SILICON_LABS_32B_SERIES 1 |
Silicon Labs series number
Definition at line
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| #define _SILICON_LABS_32B_SERIES_1 |
Silicon Labs series number
Definition at line
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| #define _SILICON_LABS_32B_SERIES_1_CONFIG 3 |
Series 1, Configuration 3
Definition at line
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| #define _SILICON_LABS_32B_SERIES_1_CONFIG_3 |
Series 1, Configuration 3
Definition at line
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| #define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 |
Radio supports 2.4 GHz
Definition at line
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| #define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 |
Radio supports dual band
Definition at line
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| #define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 |
Radio supports Sub-GHz
Definition at line
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| #define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ |
Radio type
Definition at line
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| #define _SILICON_LABS_GECKO_INTERNAL_SDID 89 |
Silicon Labs internal use only, may change any time
Definition at line
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| #define _SILICON_LABS_GECKO_INTERNAL_SDID_89 |
Silicon Labs internal use only, may change any time
Definition at line
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| #define ACMP_COUNT 2 |
2 ACMPs available
Definition at line
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| #define ACMP_PRESENT |
ACMP is available in this part
Definition at line
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| #define ADC_COUNT 1 |
1 ADCs available
Definition at line
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| #define ADC_PRESENT |
ADC is available in this part
Definition at line
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| #define AFACHAN_MAX 118U |
Analog AF channels
Definition at line
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| #define AFCHAN_MAX 118U |
AF channels connect the different on-chip peripherals with the af-mux
Definition at line
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| #define AFCHANLOC_MAX 32U |
AF channel maximum location number
Definition at line
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Referenced by DBG_SWOEnable() , and GPIO_DbgLocationSet() .
| #define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) |
Bit banding area Peripheral Address Space bit-band area
Definition at line
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Referenced by BUS_RegBitRead() , and BUS_RegBitWrite() .
| #define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) |
SRAM Address Space bit-band area
Definition at line
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Referenced by BUS_RamBitRead() , and BUS_RamBitWrite() .
| #define BOOTLOADER_COUNT 1 |
1 BOOTLOADER available
Definition at line
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| #define BOOTLOADER_PRESENT |
BOOTLOADER is available in this part
Definition at line
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| #define CMU_COUNT 1 |
1 CMU available
Definition at line
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| #define CMU_PRESENT |
CMU is available in this part
Definition at line
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| #define CRYOTIMER_COUNT 1 |
1 CRYOTIMER available
Definition at line
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| #define CRYOTIMER_PRESENT |
CRYOTIMER is available in this part
Definition at line
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| #define CRYPTO0_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) |
CRYPTO0_BITCLR base address
Definition at line
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| #define CRYPTO0_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) |
CRYPTO0_BITCLR used bits
Definition at line
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| #define CRYPTO0_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) |
CRYPTO0_BITCLR end address
Definition at line
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| #define CRYPTO0_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) |
CRYPTO0_BITCLR available address space
Definition at line
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| #define CRYPTO0_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) |
CRYPTO0_BITSET base address
Definition at line
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| #define CRYPTO0_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) |
CRYPTO0_BITSET used bits
Definition at line
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| #define CRYPTO0_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) |
CRYPTO0_BITSET end address
Definition at line
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| #define CRYPTO0_BITSET_MEM_SIZE ((uint32_t) 0x400UL) |
CRYPTO0_BITSET available address space
Definition at line
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| #define CRYPTO0_MEM_BASE ((uint32_t) 0x400F0000UL) |
CRYPTO0 base address
Definition at line
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| #define CRYPTO0_MEM_BITS ((uint32_t) 0x0000000AUL) |
CRYPTO0 used bits
Definition at line
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| #define CRYPTO0_MEM_END ((uint32_t) 0x400F03FFUL) |
CRYPTO0 end address
Definition at line
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| #define CRYPTO0_MEM_SIZE ((uint32_t) 0x400UL) |
CRYPTO0 available address space
Definition at line
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| #define CRYPTO1_BITCLR_MEM_BASE ((uint32_t) 0x440F0400UL) |
CRYPTO1_BITCLR base address
Definition at line
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| #define CRYPTO1_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) |
CRYPTO1_BITCLR used bits
Definition at line
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| #define CRYPTO1_BITCLR_MEM_END ((uint32_t) 0x440F07FFUL) |
CRYPTO1_BITCLR end address
Definition at line
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| #define CRYPTO1_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) |
CRYPTO1_BITCLR available address space
Definition at line
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| #define CRYPTO1_BITSET_MEM_BASE ((uint32_t) 0x460F0400UL) |
CRYPTO1_BITSET base address
Definition at line
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| #define CRYPTO1_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) |
CRYPTO1_BITSET used bits
Definition at line
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| #define CRYPTO1_BITSET_MEM_END ((uint32_t) 0x460F07FFUL) |
CRYPTO1_BITSET end address
Definition at line
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| #define CRYPTO1_BITSET_MEM_SIZE ((uint32_t) 0x400UL) |
CRYPTO1_BITSET available address space
Definition at line
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| #define CRYPTO1_MEM_BASE ((uint32_t) 0x400F0400UL) |
CRYPTO1 base address
Definition at line
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| #define CRYPTO1_MEM_BITS ((uint32_t) 0x0000000AUL) |
CRYPTO1 used bits
Definition at line
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| #define CRYPTO1_MEM_END ((uint32_t) 0x400F07FFUL) |
CRYPTO1 end address
Definition at line
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| #define CRYPTO1_MEM_SIZE ((uint32_t) 0x400UL) |
CRYPTO1 available address space
Definition at line
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| #define CRYPTO_BITCLR_MEM_BASE CRYPTO0_BITCLR_MEM_BASE |
Alias for CRYPTO0_BITCLR_MEM_BASE
Definition at line
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| #define CRYPTO_BITCLR_MEM_BITS CRYPTO0_BITCLR_MEM_BITS |
Alias for CRYPTO0_BITCLR_MEM_BITS
Definition at line
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| #define CRYPTO_BITCLR_MEM_END CRYPTO0_BITCLR_MEM_END |
Alias for CRYPTO0_BITCLR_MEM_END
Definition at line
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| #define CRYPTO_BITCLR_MEM_SIZE CRYPTO0_BITCLR_MEM_SIZE |
Alias for CRYPTO0_BITCLR_MEM_SIZE
Definition at line
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| #define CRYPTO_BITSET_MEM_BASE CRYPTO0_BITSET_MEM_BASE |
Alias for CRYPTO0_BITSET_MEM_BASE
Definition at line
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| #define CRYPTO_BITSET_MEM_BITS CRYPTO0_BITSET_MEM_BITS |
Alias for CRYPTO0_BITSET_MEM_BITS
Definition at line
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| #define CRYPTO_BITSET_MEM_END CRYPTO0_BITSET_MEM_END |
Alias for CRYPTO0_BITSET_MEM_END
Definition at line
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| #define CRYPTO_BITSET_MEM_SIZE CRYPTO0_BITSET_MEM_SIZE |
Alias for CRYPTO0_BITSET_MEM_SIZE
Definition at line
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| #define CRYPTO_COUNT 2 |
2 CRYPTOs available
Definition at line
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| #define CRYPTO_MEM_BASE CRYPTO0_MEM_BASE |
Alias for CRYPTO0_MEM_BASE
Definition at line
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| #define CRYPTO_MEM_BITS CRYPTO0_MEM_BITS |
Alias for CRYPTO0_MEM_BITS
Definition at line
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| #define CRYPTO_MEM_END CRYPTO0_MEM_END |
Alias for CRYPTO0_MEM_END
Definition at line
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| #define CRYPTO_MEM_SIZE CRYPTO0_MEM_SIZE |
Alias for CRYPTO0_MEM_SIZE
Definition at line
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| #define CRYPTO_PRESENT |
CRYPTO is available in this part
Definition at line
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| #define DCDC_COUNT 1 |
1 DCDC available
Definition at line
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| #define DCDC_PRESENT |
DCDC is available in this part
Definition at line
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efr32mg13p932f512gm48.h
.
| #define DMA_CHAN_COUNT 8 |
Number of DMA channels
Definition at line
253
of file
efr32mg13p932f512gm48.h
.
Referenced by NANDFLASH_Init() .
| #define EMU_COUNT 1 |
1 EMU available
Definition at line
292
of file
efr32mg13p932f512gm48.h
.
| #define EMU_PRESENT |
EMU is available in this part
Definition at line
291
of file
efr32mg13p932f512gm48.h
.
| #define ETM_COUNT 1 |
1 ETM available
Definition at line
314
of file
efr32mg13p932f512gm48.h
.
| #define ETM_PRESENT |
ETM is available in this part
Definition at line
313
of file
efr32mg13p932f512gm48.h
.
| #define EXT_IRQ_COUNT 47 |
Number of External (NVIC) interrupts
Definition at line
254
of file
efr32mg13p932f512gm48.h
.
Referenced by CORE_GetNvicRamTableHandler() , CORE_IrqIsBlocked() , CORE_NvicIRQDisabled() , CORE_NvicMaskClearIRQ() , CORE_NvicMaskSetIRQ() , and CORE_SetNvicRamTableHandler() .
| #define FLASH_BASE (0x00000000UL) |
Flash and SRAM limits for EFR32MG13P932F512GM48 Flash Base Address
Definition at line
246
of file
efr32mg13p932f512gm48.h
.
| #define FLASH_MEM_BASE ((uint32_t) 0x00000000UL) |
FLASH base address
Definition at line
192
of file
efr32mg13p932f512gm48.h
.
| #define FLASH_MEM_BITS ((uint32_t) 0x0000001CUL) |
FLASH used bits
Definition at line
195
of file
efr32mg13p932f512gm48.h
.
| #define FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) |
FLASH end address
Definition at line
194
of file
efr32mg13p932f512gm48.h
.
| #define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) |
FLASH available address space
Definition at line
193
of file
efr32mg13p932f512gm48.h
.
| #define FLASH_PAGE_SIZE 2048U |
Flash Memory page size
Definition at line
248
of file
efr32mg13p932f512gm48.h
.
Referenced by MSC_ErasePage() , and SYSTEM_GetFlashPageSize() .
| #define FLASH_SIZE (0x00080000UL) |
Available Flash Memory
Definition at line
247
of file
efr32mg13p932f512gm48.h
.
| #define FPUEH_COUNT 1 |
1 FPUEH available
Definition at line
304
of file
efr32mg13p932f512gm48.h
.
| #define FPUEH_PRESENT |
FPUEH is available in this part
Definition at line
303
of file
efr32mg13p932f512gm48.h
.
| #define GPCRC_COUNT 1 |
1 GPCRC available
Definition at line
306
of file
efr32mg13p932f512gm48.h
.
| #define GPCRC_PRESENT |
GPCRC is available in this part
Definition at line
305
of file
efr32mg13p932f512gm48.h
.
| #define GPIO_COUNT 1 |
1 GPIO available
Definition at line
298
of file
efr32mg13p932f512gm48.h
.
| #define GPIO_PRESENT |
GPIO is available in this part
Definition at line
297
of file
efr32mg13p932f512gm48.h
.
| #define I2C_COUNT 2 |
2 I2Cs available
Definition at line
280
of file
efr32mg13p932f512gm48.h
.
| #define I2C_PRESENT |
I2C is available in this part
Definition at line
279
of file
efr32mg13p932f512gm48.h
.
| #define LDMA_COUNT 1 |
1 LDMA available
Definition at line
302
of file
efr32mg13p932f512gm48.h
.
| #define LDMA_PRESENT |
LDMA is available in this part
Definition at line
301
of file
efr32mg13p932f512gm48.h
.
| #define LESENSE_COUNT 1 |
1 LESENSE available
Definition at line
310
of file
efr32mg13p932f512gm48.h
.
| #define LESENSE_PRESENT |
LESENSE is available in this part
Definition at line
309
of file
efr32mg13p932f512gm48.h
.
| #define LETIMER_COUNT 1 |
1 LETIMERs available
Definition at line
276
of file
efr32mg13p932f512gm48.h
.
| #define LETIMER_PRESENT |
LETIMER is available in this part
Definition at line
275
of file
efr32mg13p932f512gm48.h
.
| #define LEUART_COUNT 1 |
1 LEUARTs available
Definition at line
274
of file
efr32mg13p932f512gm48.h
.
| #define LEUART_PRESENT |
LEUART is available in this part
Definition at line
273
of file
efr32mg13p932f512gm48.h
.
| #define MSC_COUNT 1 |
1 MSC available
Definition at line
290
of file
efr32mg13p932f512gm48.h
.
| #define MSC_PRESENT |
MSC is available in this part
Definition at line
289
of file
efr32mg13p932f512gm48.h
.
| #define PART_NUMBER "EFR32MG13P932F512GM48" |
Configure part number Part Number
Definition at line
161
of file
efr32mg13p932f512gm48.h
.
| #define PCNT_COUNT 1 |
1 PCNTs available
Definition at line
278
of file
efr32mg13p932f512gm48.h
.
Referenced by CMU_PCNTClockExternalSet() .
| #define PCNT_PRESENT |
PCNT is available in this part
Definition at line
277
of file
efr32mg13p932f512gm48.h
.
| #define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) |
PER_BITCLR base address
Definition at line
204
of file
efr32mg13p932f512gm48.h
.
Referenced by BUS_RegMaskedClear() .
| #define PER_BITCLR_MEM_BITS ((uint32_t) 0x00000014UL) |
PER_BITCLR used bits
Definition at line
207
of file
efr32mg13p932f512gm48.h
.
| #define PER_BITCLR_MEM_END ((uint32_t) 0x440EFFFFUL) |
PER_BITCLR end address
Definition at line
206
of file
efr32mg13p932f512gm48.h
.
| #define PER_BITCLR_MEM_SIZE ((uint32_t) 0xF0000UL) |
PER_BITCLR available address space
Definition at line
205
of file
efr32mg13p932f512gm48.h
.
| #define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) |
PER_BITSET base address
Definition at line
224
of file
efr32mg13p932f512gm48.h
.
Referenced by BUS_RegMaskedSet() .
| #define PER_BITSET_MEM_BITS ((uint32_t) 0x00000014UL) |
PER_BITSET used bits
Definition at line
227
of file
efr32mg13p932f512gm48.h
.
| #define PER_BITSET_MEM_END ((uint32_t) 0x460EFFFFUL) |
PER_BITSET end address
Definition at line
226
of file
efr32mg13p932f512gm48.h
.
| #define PER_BITSET_MEM_SIZE ((uint32_t) 0xF0000UL) |
PER_BITSET available address space
Definition at line
225
of file
efr32mg13p932f512gm48.h
.
| #define PER_MEM_BASE ((uint32_t) 0x40000000UL) |
PER base address
Definition at line
180
of file
efr32mg13p932f512gm48.h
.
Referenced by BUS_RegBitRead() , BUS_RegBitWrite() , BUS_RegMaskedClear() , and BUS_RegMaskedSet() .
| #define PER_MEM_BITS ((uint32_t) 0x00000014UL) |
PER used bits
Definition at line
183
of file
efr32mg13p932f512gm48.h
.
| #define PER_MEM_END ((uint32_t) 0x400EFFFFUL) |
PER end address
Definition at line
182
of file
efr32mg13p932f512gm48.h
.
| #define PER_MEM_SIZE ((uint32_t) 0xF0000UL) |
PER available address space
Definition at line
181
of file
efr32mg13p932f512gm48.h
.
| #define PRS_CHAN_COUNT 12 |
Number of PRS channels
Definition at line
252
of file
efr32mg13p932f512gm48.h
.
Referenced by PRS_GpioOutputLocation() , PRS_Reset() , and PRS_SourceSignalSet() .
| #define PRS_COUNT 1 |
1 PRS available
Definition at line
300
of file
efr32mg13p932f512gm48.h
.
| #define PRS_PRESENT |
PRS is available in this part
Definition at line
299
of file
efr32mg13p932f512gm48.h
.
| #define RAM0_CODE_MEM_BASE ((uint32_t) 0x10000000UL) |
Memory Base addresses and limits RAM0_CODE base address
Definition at line
164
of file
efr32mg13p932f512gm48.h
.
| #define RAM0_CODE_MEM_BITS ((uint32_t) 0x0000000FUL) |
RAM0_CODE used bits
Definition at line
167
of file
efr32mg13p932f512gm48.h
.
| #define RAM0_CODE_MEM_END ((uint32_t) 0x10007FFFUL) |
RAM0_CODE end address
Definition at line
166
of file
efr32mg13p932f512gm48.h
.
| #define RAM0_CODE_MEM_SIZE ((uint32_t) 0x8000UL) |
RAM0_CODE available address space
Definition at line
165
of file
efr32mg13p932f512gm48.h
.
| #define RAM1_CODE_MEM_BASE ((uint32_t) 0x10008000UL) |
RAM1_CODE base address
Definition at line
184
of file
efr32mg13p932f512gm48.h
.
| #define RAM1_CODE_MEM_BITS ((uint32_t) 0x0000000FUL) |
RAM1_CODE used bits
Definition at line
187
of file
efr32mg13p932f512gm48.h
.
| #define RAM1_CODE_MEM_END ((uint32_t) 0x1000FFFFUL) |
RAM1_CODE end address
Definition at line
186
of file
efr32mg13p932f512gm48.h
.
| #define RAM1_CODE_MEM_SIZE ((uint32_t) 0x8000UL) |
RAM1_CODE available address space
Definition at line
185
of file
efr32mg13p932f512gm48.h
.
| #define RAM1_MEM_BASE ((uint32_t) 0x20008000UL) |
RAM1 base address
Definition at line
172
of file
efr32mg13p932f512gm48.h
.
Referenced by EMU_RamPowerDown() .
| #define RAM1_MEM_BITS ((uint32_t) 0x0000000FUL) |
RAM1 used bits
Definition at line
175
of file
efr32mg13p932f512gm48.h
.
| #define RAM1_MEM_END ((uint32_t) 0x2000FFFFUL) |
RAM1 end address
Definition at line
174
of file
efr32mg13p932f512gm48.h
.
Referenced by EMU_RamPowerDown() .
| #define RAM1_MEM_SIZE ((uint32_t) 0x8000UL) |
RAM1 available address space
Definition at line
173
of file
efr32mg13p932f512gm48.h
.
| #define RAM2_CODE_MEM_BASE ((uint32_t) 0x10010000UL) |
RAM2_CODE base address
Definition at line
232
of file
efr32mg13p932f512gm48.h
.
| #define RAM2_CODE_MEM_BITS ((uint32_t) 0x0000000BUL) |
RAM2_CODE used bits
Definition at line
235
of file
efr32mg13p932f512gm48.h
.
| #define RAM2_CODE_MEM_END ((uint32_t) 0x100107FFUL) |
RAM2_CODE end address
Definition at line
234
of file
efr32mg13p932f512gm48.h
.
| #define RAM2_CODE_MEM_SIZE ((uint32_t) 0x800UL) |
RAM2_CODE available address space
Definition at line
233
of file
efr32mg13p932f512gm48.h
.
| #define RAM2_MEM_BASE ((uint32_t) 0x20010000UL) |
RAM2 base address
Definition at line
168
of file
efr32mg13p932f512gm48.h
.
Referenced by EMU_RamPowerDown() .
| #define RAM2_MEM_BITS ((uint32_t) 0x0000000BUL) |
RAM2 used bits
Definition at line
171
of file
efr32mg13p932f512gm48.h
.
| #define RAM2_MEM_END ((uint32_t) 0x200107FFUL) |
RAM2 end address
Definition at line
170
of file
efr32mg13p932f512gm48.h
.
Referenced by EMU_RamPowerDown() .
| #define RAM2_MEM_SIZE ((uint32_t) 0x800UL) |
RAM2 available address space
Definition at line
169
of file
efr32mg13p932f512gm48.h
.
| #define RAM_MEM_BASE ((uint32_t) 0x20000000UL) |
RAM base address
Definition at line
236
of file
efr32mg13p932f512gm48.h
.
Referenced by EMU_RamPowerDown() .
| #define RAM_MEM_BITS ((uint32_t) 0x0000000FUL) |
RAM used bits
Definition at line
239
of file
efr32mg13p932f512gm48.h
.
| #define RAM_MEM_END ((uint32_t) 0x20007FFFUL) |
RAM end address
Definition at line
238
of file
efr32mg13p932f512gm48.h
.
| #define RAM_MEM_SIZE ((uint32_t) 0x8000UL) |
RAM available address space
Definition at line
237
of file
efr32mg13p932f512gm48.h
.
| #define RMU_COUNT 1 |
1 RMU available
Definition at line
294
of file
efr32mg13p932f512gm48.h
.
| #define RMU_PRESENT |
RMU is available in this part
Definition at line
293
of file
efr32mg13p932f512gm48.h
.
| #define RTCC_COUNT 1 |
1 RTCC available
Definition at line
312
of file
efr32mg13p932f512gm48.h
.
| #define RTCC_PRESENT |
RTCC is available in this part
Definition at line
311
of file
efr32mg13p932f512gm48.h
.
| #define SMU_COUNT 1 |
1 SMU available
Definition at line
318
of file
efr32mg13p932f512gm48.h
.
| #define SMU_PRESENT |
SMU is available in this part
Definition at line
317
of file
efr32mg13p932f512gm48.h
.
| #define SRAM_BASE (0x20000000UL) |
SRAM Base Address
Definition at line
249
of file
efr32mg13p932f512gm48.h
.
Referenced by BUS_RamBitRead() , BUS_RamBitWrite() , CORE_InitNvicVectorTable() , and EMU_RamPowerDown() .
| #define SRAM_SIZE (0x00010000UL) |
Available SRAM Memory
Definition at line
250
of file
efr32mg13p932f512gm48.h
.
Referenced by CORE_InitNvicVectorTable() , and EMU_RamPowerDown() .
| #define TIMER_COUNT 2 |
2 TIMERs available
Definition at line
268
of file
efr32mg13p932f512gm48.h
.
| #define TIMER_PRESENT |
TIMER is available in this part
Definition at line
267
of file
efr32mg13p932f512gm48.h
.
| #define TRNG_COUNT 1 |
1 TRNGs available
Definition at line
288
of file
efr32mg13p932f512gm48.h
.
| #define TRNG_PRESENT |
TRNG is available in this part
Definition at line
287
of file
efr32mg13p932f512gm48.h
.
| #define USART_COUNT 3 |
3 USARTs available
Definition at line
272
of file
efr32mg13p932f512gm48.h
.
| #define USART_PRESENT |
USART is available in this part
Definition at line
271
of file
efr32mg13p932f512gm48.h
.
| #define WDOG_COUNT 2 |
2 WDOGs available
Definition at line
286
of file
efr32mg13p932f512gm48.h
.
| #define WDOG_PRESENT |
WDOG is available in this part
Definition at line
285
of file
efr32mg13p932f512gm48.h
.
| #define WTIMER_COUNT 1 |
1 WTIMERs available
Definition at line
270
of file
efr32mg13p932f512gm48.h
.
| #define WTIMER_PRESENT |
WTIMER is available in this part
Definition at line
269
of file
efr32mg13p932f512gm48.h
.