Macros
#define	_DEVINFO_ADC0CAL0_GAIN1V25_MASK 0x7F00UL

#define	_DEVINFO_ADC0CAL0_GAIN1V25_SHIFT 8

#define	_DEVINFO_ADC0CAL0_GAIN2V5_MASK 0x7F000000UL

#define	_DEVINFO_ADC0CAL0_GAIN2V5_SHIFT 24

#define	_DEVINFO_ADC0CAL0_MASK 0x7FFF7FFFUL

#define	_DEVINFO_ADC0CAL0_NEGSEOFFSET1V25_MASK 0xF0UL

#define	_DEVINFO_ADC0CAL0_NEGSEOFFSET1V25_SHIFT 4

#define	_DEVINFO_ADC0CAL0_NEGSEOFFSET2V5_MASK 0xF00000UL

#define	_DEVINFO_ADC0CAL0_NEGSEOFFSET2V5_SHIFT 20

#define	_DEVINFO_ADC0CAL0_OFFSET1V25_MASK 0xFUL

#define	_DEVINFO_ADC0CAL0_OFFSET1V25_SHIFT 0

#define	_DEVINFO_ADC0CAL0_OFFSET2V5_MASK 0xF0000UL

#define	_DEVINFO_ADC0CAL0_OFFSET2V5_SHIFT 16

#define	_DEVINFO_ADC0CAL1_GAIN5VDIFF_MASK 0x7F000000UL

#define	_DEVINFO_ADC0CAL1_GAIN5VDIFF_SHIFT 24

#define	_DEVINFO_ADC0CAL1_GAINVDD_MASK 0x7F00UL

#define	_DEVINFO_ADC0CAL1_GAINVDD_SHIFT 8

#define	_DEVINFO_ADC0CAL1_MASK 0x7FFF7FFFUL

#define	_DEVINFO_ADC0CAL1_NEGSEOFFSET5VDIFF_MASK 0xF00000UL

#define	_DEVINFO_ADC0CAL1_NEGSEOFFSET5VDIFF_SHIFT 20

#define	_DEVINFO_ADC0CAL1_NEGSEOFFSETVDD_MASK 0xF0UL

#define	_DEVINFO_ADC0CAL1_NEGSEOFFSETVDD_SHIFT 4

#define	_DEVINFO_ADC0CAL1_OFFSET5VDIFF_MASK 0xF0000UL

#define	_DEVINFO_ADC0CAL1_OFFSET5VDIFF_SHIFT 16

#define	_DEVINFO_ADC0CAL1_OFFSETVDD_MASK 0xFUL

#define	_DEVINFO_ADC0CAL1_OFFSETVDD_SHIFT 0

#define	_DEVINFO_ADC0CAL2_MASK 0x000000FFUL

#define	_DEVINFO_ADC0CAL2_NEGSEOFFSET2XVDD_MASK 0xF0UL

#define	_DEVINFO_ADC0CAL2_NEGSEOFFSET2XVDD_SHIFT 4

#define	_DEVINFO_ADC0CAL2_OFFSET2XVDD_MASK 0xFUL

#define	_DEVINFO_ADC0CAL2_OFFSET2XVDD_SHIFT 0

#define	_DEVINFO_ADC0CAL3_MASK 0x0000FFF0UL

#define	_DEVINFO_ADC0CAL3_TEMPREAD1V25_MASK 0xFFF0UL

#define	_DEVINFO_ADC0CAL3_TEMPREAD1V25_SHIFT 4

#define	_DEVINFO_AUXHFRCOCAL0_CLKDIV_MASK 0x6000000UL

#define	_DEVINFO_AUXHFRCOCAL0_CLKDIV_SHIFT 25

#define	_DEVINFO_AUXHFRCOCAL0_CMPBIAS_MASK 0xE00000UL

#define	_DEVINFO_AUXHFRCOCAL0_CMPBIAS_SHIFT 21

#define	_DEVINFO_AUXHFRCOCAL0_FINETUNING_MASK 0x3F00UL

#define	_DEVINFO_AUXHFRCOCAL0_FINETUNING_SHIFT 8

#define	_DEVINFO_AUXHFRCOCAL0_FINETUNINGEN_MASK 0x8000000UL

#define	_DEVINFO_AUXHFRCOCAL0_FINETUNINGEN_SHIFT 27

#define	_DEVINFO_AUXHFRCOCAL0_FREQRANGE_MASK 0x1F0000UL

#define	_DEVINFO_AUXHFRCOCAL0_FREQRANGE_SHIFT 16

#define	_DEVINFO_AUXHFRCOCAL0_LDOHP_MASK 0x1000000UL

#define	_DEVINFO_AUXHFRCOCAL0_LDOHP_SHIFT 24

#define	_DEVINFO_AUXHFRCOCAL0_MASK 0xFFFF3F7FUL

#define	_DEVINFO_AUXHFRCOCAL0_TUNING_MASK 0x7FUL

#define	_DEVINFO_AUXHFRCOCAL0_TUNING_SHIFT 0

#define	_DEVINFO_AUXHFRCOCAL0_VREFTC_MASK 0xF0000000UL

#define	_DEVINFO_AUXHFRCOCAL0_VREFTC_SHIFT 28

#define	_DEVINFO_AUXHFRCOCAL10_CLKDIV_MASK 0x6000000UL

#define	_DEVINFO_AUXHFRCOCAL10_CLKDIV_SHIFT 25

#define	_DEVINFO_AUXHFRCOCAL10_CMPBIAS_MASK 0xE00000UL

#define	_DEVINFO_AUXHFRCOCAL10_CMPBIAS_SHIFT 21

#define	_DEVINFO_AUXHFRCOCAL10_FINETUNING_MASK 0x3F00UL

#define	_DEVINFO_AUXHFRCOCAL10_FINETUNING_SHIFT 8

#define	_DEVINFO_AUXHFRCOCAL10_FINETUNINGEN_MASK 0x8000000UL

#define	_DEVINFO_AUXHFRCOCAL10_FINETUNINGEN_SHIFT 27

#define	_DEVINFO_AUXHFRCOCAL10_FREQRANGE_MASK 0x1F0000UL

#define	_DEVINFO_AUXHFRCOCAL10_FREQRANGE_SHIFT 16

#define	_DEVINFO_AUXHFRCOCAL10_LDOHP_MASK 0x1000000UL

#define	_DEVINFO_AUXHFRCOCAL10_LDOHP_SHIFT 24

#define	_DEVINFO_AUXHFRCOCAL10_MASK 0xFFFF3F7FUL

#define	_DEVINFO_AUXHFRCOCAL10_TUNING_MASK 0x7FUL

#define	_DEVINFO_AUXHFRCOCAL10_TUNING_SHIFT 0

#define	_DEVINFO_AUXHFRCOCAL10_VREFTC_MASK 0xF0000000UL

#define	_DEVINFO_AUXHFRCOCAL10_VREFTC_SHIFT 28

#define	_DEVINFO_AUXHFRCOCAL11_CLKDIV_MASK 0x6000000UL

#define	_DEVINFO_AUXHFRCOCAL11_CLKDIV_SHIFT 25

#define	_DEVINFO_AUXHFRCOCAL11_CMPBIAS_MASK 0xE00000UL

#define	_DEVINFO_AUXHFRCOCAL11_CMPBIAS_SHIFT 21

#define	_DEVINFO_AUXHFRCOCAL11_FINETUNING_MASK 0x3F00UL

#define	_DEVINFO_AUXHFRCOCAL11_FINETUNING_SHIFT 8

#define	_DEVINFO_AUXHFRCOCAL11_FINETUNINGEN_MASK 0x8000000UL

#define	_DEVINFO_AUXHFRCOCAL11_FINETUNINGEN_SHIFT 27

#define	_DEVINFO_AUXHFRCOCAL11_FREQRANGE_MASK 0x1F0000UL

#define	_DEVINFO_AUXHFRCOCAL11_FREQRANGE_SHIFT 16

#define	_DEVINFO_AUXHFRCOCAL11_LDOHP_MASK 0x1000000UL

#define	_DEVINFO_AUXHFRCOCAL11_LDOHP_SHIFT 24

#define	_DEVINFO_AUXHFRCOCAL11_MASK 0xFFFF3F7FUL

#define	_DEVINFO_AUXHFRCOCAL11_TUNING_MASK 0x7FUL

#define	_DEVINFO_AUXHFRCOCAL11_TUNING_SHIFT 0

#define	_DEVINFO_AUXHFRCOCAL11_VREFTC_MASK 0xF0000000UL

#define	_DEVINFO_AUXHFRCOCAL11_VREFTC_SHIFT 28

#define	_DEVINFO_AUXHFRCOCAL12_CLKDIV_MASK 0x6000000UL

#define	_DEVINFO_AUXHFRCOCAL12_CLKDIV_SHIFT 25

#define	_DEVINFO_AUXHFRCOCAL12_CMPBIAS_MASK 0xE00000UL

#define	_DEVINFO_AUXHFRCOCAL12_CMPBIAS_SHIFT 21

#define	_DEVINFO_AUXHFRCOCAL12_FINETUNING_MASK 0x3F00UL

#define	_DEVINFO_AUXHFRCOCAL12_FINETUNING_SHIFT 8

#define	_DEVINFO_AUXHFRCOCAL12_FINETUNINGEN_MASK 0x8000000UL

#define	_DEVINFO_AUXHFRCOCAL12_FINETUNINGEN_SHIFT 27

#define	_DEVINFO_AUXHFRCOCAL12_FREQRANGE_MASK 0x1F0000UL

#define	_DEVINFO_AUXHFRCOCAL12_FREQRANGE_SHIFT 16

#define	_DEVINFO_AUXHFRCOCAL12_LDOHP_MASK 0x1000000UL

#define	_DEVINFO_AUXHFRCOCAL12_LDOHP_SHIFT 24

#define	_DEVINFO_AUXHFRCOCAL12_MASK 0xFFFF3F7FUL

#define	_DEVINFO_AUXHFRCOCAL12_TUNING_MASK 0x7FUL

#define	_DEVINFO_AUXHFRCOCAL12_TUNING_SHIFT 0

#define	_DEVINFO_AUXHFRCOCAL12_VREFTC_MASK 0xF0000000UL

#define	_DEVINFO_AUXHFRCOCAL12_VREFTC_SHIFT 28

#define	_DEVINFO_AUXHFRCOCAL3_CLKDIV_MASK 0x6000000UL

#define	_DEVINFO_AUXHFRCOCAL3_CLKDIV_SHIFT 25

#define	_DEVINFO_AUXHFRCOCAL3_CMPBIAS_MASK 0xE00000UL

#define	_DEVINFO_AUXHFRCOCAL3_CMPBIAS_SHIFT 21

#define	_DEVINFO_AUXHFRCOCAL3_FINETUNING_MASK 0x3F00UL

#define	_DEVINFO_AUXHFRCOCAL3_FINETUNING_SHIFT 8

#define	_DEVINFO_AUXHFRCOCAL3_FINETUNINGEN_MASK 0x8000000UL

#define	_DEVINFO_AUXHFRCOCAL3_FINETUNINGEN_SHIFT 27

#define	_DEVINFO_AUXHFRCOCAL3_FREQRANGE_MASK 0x1F0000UL

#define	_DEVINFO_AUXHFRCOCAL3_FREQRANGE_SHIFT 16

#define	_DEVINFO_AUXHFRCOCAL3_LDOHP_MASK 0x1000000UL

#define	_DEVINFO_AUXHFRCOCAL3_LDOHP_SHIFT 24

#define	_DEVINFO_AUXHFRCOCAL3_MASK 0xFFFF3F7FUL

#define	_DEVINFO_AUXHFRCOCAL3_TUNING_MASK 0x7FUL

#define	_DEVINFO_AUXHFRCOCAL3_TUNING_SHIFT 0

#define	_DEVINFO_AUXHFRCOCAL3_VREFTC_MASK 0xF0000000UL

#define	_DEVINFO_AUXHFRCOCAL3_VREFTC_SHIFT 28

#define	_DEVINFO_AUXHFRCOCAL6_CLKDIV_MASK 0x6000000UL

#define	_DEVINFO_AUXHFRCOCAL6_CLKDIV_SHIFT 25

#define	_DEVINFO_AUXHFRCOCAL6_CMPBIAS_MASK 0xE00000UL

#define	_DEVINFO_AUXHFRCOCAL6_CMPBIAS_SHIFT 21

#define	_DEVINFO_AUXHFRCOCAL6_FINETUNING_MASK 0x3F00UL

#define	_DEVINFO_AUXHFRCOCAL6_FINETUNING_SHIFT 8

#define	_DEVINFO_AUXHFRCOCAL6_FINETUNINGEN_MASK 0x8000000UL

#define	_DEVINFO_AUXHFRCOCAL6_FINETUNINGEN_SHIFT 27

#define	_DEVINFO_AUXHFRCOCAL6_FREQRANGE_MASK 0x1F0000UL

#define	_DEVINFO_AUXHFRCOCAL6_FREQRANGE_SHIFT 16

#define	_DEVINFO_AUXHFRCOCAL6_LDOHP_MASK 0x1000000UL

#define	_DEVINFO_AUXHFRCOCAL6_LDOHP_SHIFT 24

#define	_DEVINFO_AUXHFRCOCAL6_MASK 0xFFFF3F7FUL

#define	_DEVINFO_AUXHFRCOCAL6_TUNING_MASK 0x7FUL

#define	_DEVINFO_AUXHFRCOCAL6_TUNING_SHIFT 0

#define	_DEVINFO_AUXHFRCOCAL6_VREFTC_MASK 0xF0000000UL

#define	_DEVINFO_AUXHFRCOCAL6_VREFTC_SHIFT 28

#define	_DEVINFO_AUXHFRCOCAL7_CLKDIV_MASK 0x6000000UL

#define	_DEVINFO_AUXHFRCOCAL7_CLKDIV_SHIFT 25

#define	_DEVINFO_AUXHFRCOCAL7_CMPBIAS_MASK 0xE00000UL

#define	_DEVINFO_AUXHFRCOCAL7_CMPBIAS_SHIFT 21

#define	_DEVINFO_AUXHFRCOCAL7_FINETUNING_MASK 0x3F00UL

#define	_DEVINFO_AUXHFRCOCAL7_FINETUNING_SHIFT 8

#define	_DEVINFO_AUXHFRCOCAL7_FINETUNINGEN_MASK 0x8000000UL

#define	_DEVINFO_AUXHFRCOCAL7_FINETUNINGEN_SHIFT 27

#define	_DEVINFO_AUXHFRCOCAL7_FREQRANGE_MASK 0x1F0000UL

#define	_DEVINFO_AUXHFRCOCAL7_FREQRANGE_SHIFT 16

#define	_DEVINFO_AUXHFRCOCAL7_LDOHP_MASK 0x1000000UL

#define	_DEVINFO_AUXHFRCOCAL7_LDOHP_SHIFT 24

#define	_DEVINFO_AUXHFRCOCAL7_MASK 0xFFFF3F7FUL

#define	_DEVINFO_AUXHFRCOCAL7_TUNING_MASK 0x7FUL

#define	_DEVINFO_AUXHFRCOCAL7_TUNING_SHIFT 0

#define	_DEVINFO_AUXHFRCOCAL7_VREFTC_MASK 0xF0000000UL

#define	_DEVINFO_AUXHFRCOCAL7_VREFTC_SHIFT 28

#define	_DEVINFO_AUXHFRCOCAL8_CLKDIV_MASK 0x6000000UL

#define	_DEVINFO_AUXHFRCOCAL8_CLKDIV_SHIFT 25

#define	_DEVINFO_AUXHFRCOCAL8_CMPBIAS_MASK 0xE00000UL

#define	_DEVINFO_AUXHFRCOCAL8_CMPBIAS_SHIFT 21

#define	_DEVINFO_AUXHFRCOCAL8_FINETUNING_MASK 0x3F00UL

#define	_DEVINFO_AUXHFRCOCAL8_FINETUNING_SHIFT 8

#define	_DEVINFO_AUXHFRCOCAL8_FINETUNINGEN_MASK 0x8000000UL

#define	_DEVINFO_AUXHFRCOCAL8_FINETUNINGEN_SHIFT 27

#define	_DEVINFO_AUXHFRCOCAL8_FREQRANGE_MASK 0x1F0000UL

#define	_DEVINFO_AUXHFRCOCAL8_FREQRANGE_SHIFT 16

#define	_DEVINFO_AUXHFRCOCAL8_LDOHP_MASK 0x1000000UL

#define	_DEVINFO_AUXHFRCOCAL8_LDOHP_SHIFT 24

#define	_DEVINFO_AUXHFRCOCAL8_MASK 0xFFFF3F7FUL

#define	_DEVINFO_AUXHFRCOCAL8_TUNING_MASK 0x7FUL

#define	_DEVINFO_AUXHFRCOCAL8_TUNING_SHIFT 0

#define	_DEVINFO_AUXHFRCOCAL8_VREFTC_MASK 0xF0000000UL

#define	_DEVINFO_AUXHFRCOCAL8_VREFTC_SHIFT 28

#define	_DEVINFO_CAL_CRC_MASK 0xFFFFUL

#define	_DEVINFO_CAL_CRC_SHIFT 0

#define	_DEVINFO_CAL_MASK 0x00FFFFFFUL

#define	_DEVINFO_CAL_TEMP_MASK 0xFF0000UL

#define	_DEVINFO_CAL_TEMP_SHIFT 16

#define	_DEVINFO_CUSTOMINFO_MASK 0xFFFF0000UL

#define	_DEVINFO_CUSTOMINFO_PARTNO_MASK 0xFFFF0000UL

#define	_DEVINFO_CUSTOMINFO_PARTNO_SHIFT 16

#define	_DEVINFO_DCDCLNVCTRL0_1V2LNATT0_MASK 0xFFUL

#define	_DEVINFO_DCDCLNVCTRL0_1V2LNATT0_SHIFT 0

#define	_DEVINFO_DCDCLNVCTRL0_1V8LNATT0_MASK 0xFF00UL

#define	_DEVINFO_DCDCLNVCTRL0_1V8LNATT0_SHIFT 8

#define	_DEVINFO_DCDCLNVCTRL0_1V8LNATT1_MASK 0xFF0000UL

#define	_DEVINFO_DCDCLNVCTRL0_1V8LNATT1_SHIFT 16

#define	_DEVINFO_DCDCLNVCTRL0_3V0LNATT1_MASK 0xFF000000UL

#define	_DEVINFO_DCDCLNVCTRL0_3V0LNATT1_SHIFT 24

#define	_DEVINFO_DCDCLNVCTRL0_MASK 0xFFFFFFFFUL

#define	_DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT0_MASK 0xFFUL

#define	_DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT0_SHIFT 0

#define	_DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT1_MASK 0xFF00UL

#define	_DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT1_SHIFT 8

#define	_DEVINFO_DCDCLPCMPHYSSEL0_MASK 0x0000FFFFUL

#define	_DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS0_MASK 0xFFUL

#define	_DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS0_SHIFT 0

#define	_DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS1_MASK 0xFF00UL

#define	_DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS1_SHIFT 8

#define	_DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS2_MASK 0xFF0000UL

#define	_DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS2_SHIFT 16

#define	_DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS3_MASK 0xFF000000UL

#define	_DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS3_SHIFT 24

#define	_DEVINFO_DCDCLPCMPHYSSEL1_MASK 0xFFFFFFFFUL

#define	_DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS0_MASK 0xFFUL

#define	_DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS0_SHIFT 0

#define	_DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS1_MASK 0xFF0000UL

#define	_DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS1_SHIFT 16

#define	_DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS0_MASK 0xFF00UL

#define	_DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS0_SHIFT 8

#define	_DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS1_MASK 0xFF000000UL

#define	_DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS1_SHIFT 24

#define	_DEVINFO_DCDCLPVCTRL0_MASK 0xFFFFFFFFUL

#define	_DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS2_MASK 0xFFUL

#define	_DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS2_SHIFT 0

#define	_DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS3_MASK 0xFF0000UL

#define	_DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS3_SHIFT 16

#define	_DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS2_MASK 0xFF00UL

#define	_DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS2_SHIFT 8

#define	_DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS3_MASK 0xFF000000UL

#define	_DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS3_SHIFT 24

#define	_DEVINFO_DCDCLPVCTRL1_MASK 0xFFFFFFFFUL

#define	_DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS0_MASK 0xFFUL

#define	_DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS0_SHIFT 0

#define	_DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS1_MASK 0xFF0000UL

#define	_DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS1_SHIFT 16

#define	_DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS0_MASK 0xFF00UL

#define	_DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS0_SHIFT 8

#define	_DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS1_MASK 0xFF000000UL

#define	_DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS1_SHIFT 24

#define	_DEVINFO_DCDCLPVCTRL2_MASK 0xFFFFFFFFUL

#define	_DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS2_MASK 0xFFUL

#define	_DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS2_SHIFT 0

#define	_DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS3_MASK 0xFF0000UL

#define	_DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS3_SHIFT 16

#define	_DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS2_MASK 0xFF00UL

#define	_DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS2_SHIFT 8

#define	_DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS3_MASK 0xFF000000UL

#define	_DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS3_SHIFT 24

#define	_DEVINFO_DCDCLPVCTRL3_MASK 0xFFFFFFFFUL

#define	_DEVINFO_DEVINFOREV_DEVINFOREV_MASK 0xFFUL

#define	_DEVINFO_DEVINFOREV_DEVINFOREV_SHIFT 0

#define	_DEVINFO_DEVINFOREV_MASK 0x000000FFUL

#define	_DEVINFO_EMUTEMP_EMUTEMPROOM_MASK 0xFFUL

#define	_DEVINFO_EMUTEMP_EMUTEMPROOM_SHIFT 0

#define	_DEVINFO_EMUTEMP_MASK 0x000000FFUL

#define	_DEVINFO_EUI48H_MASK 0x0000FFFFUL

#define	_DEVINFO_EUI48H_OUI48H_MASK 0xFFFFUL

#define	_DEVINFO_EUI48H_OUI48H_SHIFT 0

#define	_DEVINFO_EUI48L_MASK 0xFFFFFFFFUL

#define	_DEVINFO_EUI48L_OUI48L_MASK 0xFF000000UL

#define	_DEVINFO_EUI48L_OUI48L_SHIFT 24

#define	_DEVINFO_EUI48L_UNIQUEID_MASK 0xFFFFFFUL

#define	_DEVINFO_EUI48L_UNIQUEID_SHIFT 0

#define	_DEVINFO_EXTINFO_CONNECTION_MASK 0xFF00UL

#define	_DEVINFO_EXTINFO_CONNECTION_NONE 0x000000FFUL

#define	_DEVINFO_EXTINFO_CONNECTION_SHIFT 8

#define	_DEVINFO_EXTINFO_CONNECTION_SPI 0x00000001UL

#define	_DEVINFO_EXTINFO_MASK 0x00FFFFFFUL

#define	_DEVINFO_EXTINFO_REV_MASK 0xFF0000UL

#define	_DEVINFO_EXTINFO_REV_NONE 0x000000FFUL

#define	_DEVINFO_EXTINFO_REV_REV1 0x00000001UL

#define	_DEVINFO_EXTINFO_REV_SHIFT 16

#define	_DEVINFO_EXTINFO_TYPE_AT25S041 0x00000002UL

#define	_DEVINFO_EXTINFO_TYPE_IS25LQ040B 0x00000001UL

#define	_DEVINFO_EXTINFO_TYPE_MASK 0xFFUL

#define	_DEVINFO_EXTINFO_TYPE_NONE 0x000000FFUL

#define	_DEVINFO_EXTINFO_TYPE_SHIFT 0

#define	_DEVINFO_HFRCOCAL0_CLKDIV_MASK 0x6000000UL

#define	_DEVINFO_HFRCOCAL0_CLKDIV_SHIFT 25

#define	_DEVINFO_HFRCOCAL0_CMPBIAS_MASK 0xE00000UL

#define	_DEVINFO_HFRCOCAL0_CMPBIAS_SHIFT 21

#define	_DEVINFO_HFRCOCAL0_FINETUNING_MASK 0x3F00UL

#define	_DEVINFO_HFRCOCAL0_FINETUNING_SHIFT 8

#define	_DEVINFO_HFRCOCAL0_FINETUNINGEN_MASK 0x8000000UL

#define	_DEVINFO_HFRCOCAL0_FINETUNINGEN_SHIFT 27

#define	_DEVINFO_HFRCOCAL0_FREQRANGE_MASK 0x1F0000UL

#define	_DEVINFO_HFRCOCAL0_FREQRANGE_SHIFT 16

#define	_DEVINFO_HFRCOCAL0_LDOHP_MASK 0x1000000UL

#define	_DEVINFO_HFRCOCAL0_LDOHP_SHIFT 24

#define	_DEVINFO_HFRCOCAL0_MASK 0xFFFF3F7FUL

#define	_DEVINFO_HFRCOCAL0_TUNING_MASK 0x7FUL

#define	_DEVINFO_HFRCOCAL0_TUNING_SHIFT 0

#define	_DEVINFO_HFRCOCAL0_VREFTC_MASK 0xF0000000UL

#define	_DEVINFO_HFRCOCAL0_VREFTC_SHIFT 28

#define	_DEVINFO_HFRCOCAL10_CLKDIV_MASK 0x6000000UL

#define	_DEVINFO_HFRCOCAL10_CLKDIV_SHIFT 25

#define	_DEVINFO_HFRCOCAL10_CMPBIAS_MASK 0xE00000UL

#define	_DEVINFO_HFRCOCAL10_CMPBIAS_SHIFT 21

#define	_DEVINFO_HFRCOCAL10_FINETUNING_MASK 0x3F00UL

#define	_DEVINFO_HFRCOCAL10_FINETUNING_SHIFT 8

#define	_DEVINFO_HFRCOCAL10_FINETUNINGEN_MASK 0x8000000UL

#define	_DEVINFO_HFRCOCAL10_FINETUNINGEN_SHIFT 27

#define	_DEVINFO_HFRCOCAL10_FREQRANGE_MASK 0x1F0000UL

#define	_DEVINFO_HFRCOCAL10_FREQRANGE_SHIFT 16

#define	_DEVINFO_HFRCOCAL10_LDOHP_MASK 0x1000000UL

#define	_DEVINFO_HFRCOCAL10_LDOHP_SHIFT 24

#define	_DEVINFO_HFRCOCAL10_MASK 0xFFFF3F7FUL

#define	_DEVINFO_HFRCOCAL10_TUNING_MASK 0x7FUL

#define	_DEVINFO_HFRCOCAL10_TUNING_SHIFT 0

#define	_DEVINFO_HFRCOCAL10_VREFTC_MASK 0xF0000000UL

#define	_DEVINFO_HFRCOCAL10_VREFTC_SHIFT 28

#define	_DEVINFO_HFRCOCAL11_CLKDIV_MASK 0x6000000UL

#define	_DEVINFO_HFRCOCAL11_CLKDIV_SHIFT 25

#define	_DEVINFO_HFRCOCAL11_CMPBIAS_MASK 0xE00000UL

#define	_DEVINFO_HFRCOCAL11_CMPBIAS_SHIFT 21

#define	_DEVINFO_HFRCOCAL11_FINETUNING_MASK 0x3F00UL

#define	_DEVINFO_HFRCOCAL11_FINETUNING_SHIFT 8

#define	_DEVINFO_HFRCOCAL11_FINETUNINGEN_MASK 0x8000000UL

#define	_DEVINFO_HFRCOCAL11_FINETUNINGEN_SHIFT 27

#define	_DEVINFO_HFRCOCAL11_FREQRANGE_MASK 0x1F0000UL

#define	_DEVINFO_HFRCOCAL11_FREQRANGE_SHIFT 16

#define	_DEVINFO_HFRCOCAL11_LDOHP_MASK 0x1000000UL

#define	_DEVINFO_HFRCOCAL11_LDOHP_SHIFT 24

#define	_DEVINFO_HFRCOCAL11_MASK 0xFFFF3F7FUL

#define	_DEVINFO_HFRCOCAL11_TUNING_MASK 0x7FUL

#define	_DEVINFO_HFRCOCAL11_TUNING_SHIFT 0

#define	_DEVINFO_HFRCOCAL11_VREFTC_MASK 0xF0000000UL

#define	_DEVINFO_HFRCOCAL11_VREFTC_SHIFT 28

#define	_DEVINFO_HFRCOCAL12_CLKDIV_MASK 0x6000000UL

#define	_DEVINFO_HFRCOCAL12_CLKDIV_SHIFT 25

#define	_DEVINFO_HFRCOCAL12_CMPBIAS_MASK 0xE00000UL

#define	_DEVINFO_HFRCOCAL12_CMPBIAS_SHIFT 21

#define	_DEVINFO_HFRCOCAL12_FINETUNING_MASK 0x3F00UL

#define	_DEVINFO_HFRCOCAL12_FINETUNING_SHIFT 8

#define	_DEVINFO_HFRCOCAL12_FINETUNINGEN_MASK 0x8000000UL

#define	_DEVINFO_HFRCOCAL12_FINETUNINGEN_SHIFT 27

#define	_DEVINFO_HFRCOCAL12_FREQRANGE_MASK 0x1F0000UL

#define	_DEVINFO_HFRCOCAL12_FREQRANGE_SHIFT 16

#define	_DEVINFO_HFRCOCAL12_LDOHP_MASK 0x1000000UL

#define	_DEVINFO_HFRCOCAL12_LDOHP_SHIFT 24

#define	_DEVINFO_HFRCOCAL12_MASK 0xFFFF3F7FUL

#define	_DEVINFO_HFRCOCAL12_TUNING_MASK 0x7FUL

#define	_DEVINFO_HFRCOCAL12_TUNING_SHIFT 0

#define	_DEVINFO_HFRCOCAL12_VREFTC_MASK 0xF0000000UL

#define	_DEVINFO_HFRCOCAL12_VREFTC_SHIFT 28

#define	_DEVINFO_HFRCOCAL3_CLKDIV_MASK 0x6000000UL

#define	_DEVINFO_HFRCOCAL3_CLKDIV_SHIFT 25

#define	_DEVINFO_HFRCOCAL3_CMPBIAS_MASK 0xE00000UL

#define	_DEVINFO_HFRCOCAL3_CMPBIAS_SHIFT 21

#define	_DEVINFO_HFRCOCAL3_FINETUNING_MASK 0x3F00UL

#define	_DEVINFO_HFRCOCAL3_FINETUNING_SHIFT 8

#define	_DEVINFO_HFRCOCAL3_FINETUNINGEN_MASK 0x8000000UL

#define	_DEVINFO_HFRCOCAL3_FINETUNINGEN_SHIFT 27

#define	_DEVINFO_HFRCOCAL3_FREQRANGE_MASK 0x1F0000UL

#define	_DEVINFO_HFRCOCAL3_FREQRANGE_SHIFT 16

#define	_DEVINFO_HFRCOCAL3_LDOHP_MASK 0x1000000UL

#define	_DEVINFO_HFRCOCAL3_LDOHP_SHIFT 24

#define	_DEVINFO_HFRCOCAL3_MASK 0xFFFF3F7FUL

#define	_DEVINFO_HFRCOCAL3_TUNING_MASK 0x7FUL

#define	_DEVINFO_HFRCOCAL3_TUNING_SHIFT 0

#define	_DEVINFO_HFRCOCAL3_VREFTC_MASK 0xF0000000UL

#define	_DEVINFO_HFRCOCAL3_VREFTC_SHIFT 28

#define	_DEVINFO_HFRCOCAL6_CLKDIV_MASK 0x6000000UL

#define	_DEVINFO_HFRCOCAL6_CLKDIV_SHIFT 25

#define	_DEVINFO_HFRCOCAL6_CMPBIAS_MASK 0xE00000UL

#define	_DEVINFO_HFRCOCAL6_CMPBIAS_SHIFT 21

#define	_DEVINFO_HFRCOCAL6_FINETUNING_MASK 0x3F00UL

#define	_DEVINFO_HFRCOCAL6_FINETUNING_SHIFT 8

#define	_DEVINFO_HFRCOCAL6_FINETUNINGEN_MASK 0x8000000UL

#define	_DEVINFO_HFRCOCAL6_FINETUNINGEN_SHIFT 27

#define	_DEVINFO_HFRCOCAL6_FREQRANGE_MASK 0x1F0000UL

#define	_DEVINFO_HFRCOCAL6_FREQRANGE_SHIFT 16

#define	_DEVINFO_HFRCOCAL6_LDOHP_MASK 0x1000000UL

#define	_DEVINFO_HFRCOCAL6_LDOHP_SHIFT 24

#define	_DEVINFO_HFRCOCAL6_MASK 0xFFFF3F7FUL

#define	_DEVINFO_HFRCOCAL6_TUNING_MASK 0x7FUL

#define	_DEVINFO_HFRCOCAL6_TUNING_SHIFT 0

#define	_DEVINFO_HFRCOCAL6_VREFTC_MASK 0xF0000000UL

#define	_DEVINFO_HFRCOCAL6_VREFTC_SHIFT 28

#define	_DEVINFO_HFRCOCAL7_CLKDIV_MASK 0x6000000UL

#define	_DEVINFO_HFRCOCAL7_CLKDIV_SHIFT 25

#define	_DEVINFO_HFRCOCAL7_CMPBIAS_MASK 0xE00000UL

#define	_DEVINFO_HFRCOCAL7_CMPBIAS_SHIFT 21

#define	_DEVINFO_HFRCOCAL7_FINETUNING_MASK 0x3F00UL

#define	_DEVINFO_HFRCOCAL7_FINETUNING_SHIFT 8

#define	_DEVINFO_HFRCOCAL7_FINETUNINGEN_MASK 0x8000000UL

#define	_DEVINFO_HFRCOCAL7_FINETUNINGEN_SHIFT 27

#define	_DEVINFO_HFRCOCAL7_FREQRANGE_MASK 0x1F0000UL

#define	_DEVINFO_HFRCOCAL7_FREQRANGE_SHIFT 16

#define	_DEVINFO_HFRCOCAL7_LDOHP_MASK 0x1000000UL

#define	_DEVINFO_HFRCOCAL7_LDOHP_SHIFT 24

#define	_DEVINFO_HFRCOCAL7_MASK 0xFFFF3F7FUL

#define	_DEVINFO_HFRCOCAL7_TUNING_MASK 0x7FUL

#define	_DEVINFO_HFRCOCAL7_TUNING_SHIFT 0

#define	_DEVINFO_HFRCOCAL7_VREFTC_MASK 0xF0000000UL

#define	_DEVINFO_HFRCOCAL7_VREFTC_SHIFT 28

#define	_DEVINFO_HFRCOCAL8_CLKDIV_MASK 0x6000000UL

#define	_DEVINFO_HFRCOCAL8_CLKDIV_SHIFT 25

#define	_DEVINFO_HFRCOCAL8_CMPBIAS_MASK 0xE00000UL

#define	_DEVINFO_HFRCOCAL8_CMPBIAS_SHIFT 21

#define	_DEVINFO_HFRCOCAL8_FINETUNING_MASK 0x3F00UL

#define	_DEVINFO_HFRCOCAL8_FINETUNING_SHIFT 8

#define	_DEVINFO_HFRCOCAL8_FINETUNINGEN_MASK 0x8000000UL

#define	_DEVINFO_HFRCOCAL8_FINETUNINGEN_SHIFT 27

#define	_DEVINFO_HFRCOCAL8_FREQRANGE_MASK 0x1F0000UL

#define	_DEVINFO_HFRCOCAL8_FREQRANGE_SHIFT 16

#define	_DEVINFO_HFRCOCAL8_LDOHP_MASK 0x1000000UL

#define	_DEVINFO_HFRCOCAL8_LDOHP_SHIFT 24

#define	_DEVINFO_HFRCOCAL8_MASK 0xFFFF3F7FUL

#define	_DEVINFO_HFRCOCAL8_TUNING_MASK 0x7FUL

#define	_DEVINFO_HFRCOCAL8_TUNING_SHIFT 0

#define	_DEVINFO_HFRCOCAL8_VREFTC_MASK 0xF0000000UL

#define	_DEVINFO_HFRCOCAL8_VREFTC_SHIFT 28

#define	_DEVINFO_IDAC0CAL0_MASK 0xFFFFFFFFUL

#define	_DEVINFO_IDAC0CAL0_SOURCERANGE0TUNING_MASK 0xFFUL

#define	_DEVINFO_IDAC0CAL0_SOURCERANGE0TUNING_SHIFT 0

#define	_DEVINFO_IDAC0CAL0_SOURCERANGE1TUNING_MASK 0xFF00UL

#define	_DEVINFO_IDAC0CAL0_SOURCERANGE1TUNING_SHIFT 8

#define	_DEVINFO_IDAC0CAL0_SOURCERANGE2TUNING_MASK 0xFF0000UL

#define	_DEVINFO_IDAC0CAL0_SOURCERANGE2TUNING_SHIFT 16

#define	_DEVINFO_IDAC0CAL0_SOURCERANGE3TUNING_MASK 0xFF000000UL

#define	_DEVINFO_IDAC0CAL0_SOURCERANGE3TUNING_SHIFT 24

#define	_DEVINFO_IDAC0CAL1_MASK 0xFFFFFFFFUL

#define	_DEVINFO_IDAC0CAL1_SINKRANGE0TUNING_MASK 0xFFUL

#define	_DEVINFO_IDAC0CAL1_SINKRANGE0TUNING_SHIFT 0

#define	_DEVINFO_IDAC0CAL1_SINKRANGE1TUNING_MASK 0xFF00UL

#define	_DEVINFO_IDAC0CAL1_SINKRANGE1TUNING_SHIFT 8

#define	_DEVINFO_IDAC0CAL1_SINKRANGE2TUNING_MASK 0xFF0000UL

#define	_DEVINFO_IDAC0CAL1_SINKRANGE2TUNING_SHIFT 16

#define	_DEVINFO_IDAC0CAL1_SINKRANGE3TUNING_MASK 0xFF000000UL

#define	_DEVINFO_IDAC0CAL1_SINKRANGE3TUNING_SHIFT 24

#define	_DEVINFO_MEMINFO_FLASH_PAGE_SIZE_MASK 0xFF000000UL

#define	_DEVINFO_MEMINFO_FLASH_PAGE_SIZE_SHIFT 24

#define	_DEVINFO_MEMINFO_MASK 0xFFFFFFFFUL

#define	_DEVINFO_MEMINFO_PINCOUNT_MASK 0xFF0000UL

#define	_DEVINFO_MEMINFO_PINCOUNT_SHIFT 16

#define	_DEVINFO_MEMINFO_PKGTYPE_BGA 0x0000004CUL

#define	_DEVINFO_MEMINFO_PKGTYPE_MASK 0xFF00UL

#define	_DEVINFO_MEMINFO_PKGTYPE_QFN 0x0000004DUL

#define	_DEVINFO_MEMINFO_PKGTYPE_QFP 0x00000051UL

#define	_DEVINFO_MEMINFO_PKGTYPE_SHIFT 8

#define	_DEVINFO_MEMINFO_PKGTYPE_WLCSP 0x0000004AUL

#define	_DEVINFO_MEMINFO_TEMPGRADE_MASK 0xFFUL

#define	_DEVINFO_MEMINFO_TEMPGRADE_N0TO70 0x00000003UL

#define	_DEVINFO_MEMINFO_TEMPGRADE_N40TO105 0x00000002UL

#define	_DEVINFO_MEMINFO_TEMPGRADE_N40TO125 0x00000001UL

#define	_DEVINFO_MEMINFO_TEMPGRADE_N40TO85 0x00000000UL

#define	_DEVINFO_MEMINFO_TEMPGRADE_SHIFT 0

#define	_DEVINFO_MODULEINFO_MASK 0xFFFFFFFFUL

#define	_DEVINFO_MODULEINFO_RESERVED1_MASK 0xFFFFFFFFUL

#define	_DEVINFO_MODULEINFO_RESERVED1_SHIFT 0

#define	_DEVINFO_MSIZE_FLASH_MASK 0xFFFFUL

#define	_DEVINFO_MSIZE_FLASH_SHIFT 0

#define	_DEVINFO_MSIZE_MASK 0xFFFFFFFFUL

#define	_DEVINFO_MSIZE_SRAM_MASK 0xFFFF0000UL

#define	_DEVINFO_MSIZE_SRAM_SHIFT 16

#define	_DEVINFO_OPA0CAL0_CM1_MASK 0xFUL

#define	_DEVINFO_OPA0CAL0_CM1_SHIFT 0

#define	_DEVINFO_OPA0CAL0_CM2_MASK 0x1E0UL

#define	_DEVINFO_OPA0CAL0_CM2_SHIFT 5

#define	_DEVINFO_OPA0CAL0_CM3_MASK 0xC00UL

#define	_DEVINFO_OPA0CAL0_CM3_SHIFT 10

#define	_DEVINFO_OPA0CAL0_GM3_MASK 0x60000UL

#define	_DEVINFO_OPA0CAL0_GM3_SHIFT 17

#define	_DEVINFO_OPA0CAL0_GM_MASK 0xE000UL

#define	_DEVINFO_OPA0CAL0_GM_SHIFT 13

#define	_DEVINFO_OPA0CAL0_MASK 0x7DF6EDEFUL

#define	_DEVINFO_OPA0CAL0_OFFSETN_MASK 0x7C000000UL

#define	_DEVINFO_OPA0CAL0_OFFSETN_SHIFT 26

#define	_DEVINFO_OPA0CAL0_OFFSETP_MASK 0x1F00000UL

#define	_DEVINFO_OPA0CAL0_OFFSETP_SHIFT 20

#define	_DEVINFO_OPA0CAL1_CM1_MASK 0xFUL

#define	_DEVINFO_OPA0CAL1_CM1_SHIFT 0

#define	_DEVINFO_OPA0CAL1_CM2_MASK 0x1E0UL

#define	_DEVINFO_OPA0CAL1_CM2_SHIFT 5

#define	_DEVINFO_OPA0CAL1_CM3_MASK 0xC00UL

#define	_DEVINFO_OPA0CAL1_CM3_SHIFT 10

#define	_DEVINFO_OPA0CAL1_GM3_MASK 0x60000UL

#define	_DEVINFO_OPA0CAL1_GM3_SHIFT 17

#define	_DEVINFO_OPA0CAL1_GM_MASK 0xE000UL

#define	_DEVINFO_OPA0CAL1_GM_SHIFT 13

#define	_DEVINFO_OPA0CAL1_MASK 0x7DF6EDEFUL

#define	_DEVINFO_OPA0CAL1_OFFSETN_MASK 0x7C000000UL

#define	_DEVINFO_OPA0CAL1_OFFSETN_SHIFT 26

#define	_DEVINFO_OPA0CAL1_OFFSETP_MASK 0x1F00000UL

#define	_DEVINFO_OPA0CAL1_OFFSETP_SHIFT 20

#define	_DEVINFO_OPA0CAL2_CM1_MASK 0xFUL

#define	_DEVINFO_OPA0CAL2_CM1_SHIFT 0

#define	_DEVINFO_OPA0CAL2_CM2_MASK 0x1E0UL

#define	_DEVINFO_OPA0CAL2_CM2_SHIFT 5

#define	_DEVINFO_OPA0CAL2_CM3_MASK 0xC00UL

#define	_DEVINFO_OPA0CAL2_CM3_SHIFT 10

#define	_DEVINFO_OPA0CAL2_GM3_MASK 0x60000UL

#define	_DEVINFO_OPA0CAL2_GM3_SHIFT 17

#define	_DEVINFO_OPA0CAL2_GM_MASK 0xE000UL

#define	_DEVINFO_OPA0CAL2_GM_SHIFT 13

#define	_DEVINFO_OPA0CAL2_MASK 0x7DF6EDEFUL

#define	_DEVINFO_OPA0CAL2_OFFSETN_MASK 0x7C000000UL

#define	_DEVINFO_OPA0CAL2_OFFSETN_SHIFT 26

#define	_DEVINFO_OPA0CAL2_OFFSETP_MASK 0x1F00000UL

#define	_DEVINFO_OPA0CAL2_OFFSETP_SHIFT 20

#define	_DEVINFO_OPA0CAL3_CM1_MASK 0xFUL

#define	_DEVINFO_OPA0CAL3_CM1_SHIFT 0

#define	_DEVINFO_OPA0CAL3_CM2_MASK 0x1E0UL

#define	_DEVINFO_OPA0CAL3_CM2_SHIFT 5

#define	_DEVINFO_OPA0CAL3_CM3_MASK 0xC00UL

#define	_DEVINFO_OPA0CAL3_CM3_SHIFT 10

#define	_DEVINFO_OPA0CAL3_GM3_MASK 0x60000UL

#define	_DEVINFO_OPA0CAL3_GM3_SHIFT 17

#define	_DEVINFO_OPA0CAL3_GM_MASK 0xE000UL

#define	_DEVINFO_OPA0CAL3_GM_SHIFT 13

#define	_DEVINFO_OPA0CAL3_MASK 0x7DF6EDEFUL

#define	_DEVINFO_OPA0CAL3_OFFSETN_MASK 0x7C000000UL

#define	_DEVINFO_OPA0CAL3_OFFSETN_SHIFT 26

#define	_DEVINFO_OPA0CAL3_OFFSETP_MASK 0x1F00000UL

#define	_DEVINFO_OPA0CAL3_OFFSETP_SHIFT 20

#define	_DEVINFO_OPA0CAL4_CM1_MASK 0xFUL

#define	_DEVINFO_OPA0CAL4_CM1_SHIFT 0

#define	_DEVINFO_OPA0CAL4_CM2_MASK 0x1E0UL

#define	_DEVINFO_OPA0CAL4_CM2_SHIFT 5

#define	_DEVINFO_OPA0CAL4_CM3_MASK 0xC00UL

#define	_DEVINFO_OPA0CAL4_CM3_SHIFT 10

#define	_DEVINFO_OPA0CAL4_GM3_MASK 0x60000UL

#define	_DEVINFO_OPA0CAL4_GM3_SHIFT 17

#define	_DEVINFO_OPA0CAL4_GM_MASK 0xE000UL

#define	_DEVINFO_OPA0CAL4_GM_SHIFT 13

#define	_DEVINFO_OPA0CAL4_MASK 0x7DF6EDEFUL

#define	_DEVINFO_OPA0CAL4_OFFSETN_MASK 0x7C000000UL

#define	_DEVINFO_OPA0CAL4_OFFSETN_SHIFT 26

#define	_DEVINFO_OPA0CAL4_OFFSETP_MASK 0x1F00000UL

#define	_DEVINFO_OPA0CAL4_OFFSETP_SHIFT 20

#define	_DEVINFO_OPA0CAL5_CM1_MASK 0xFUL

#define	_DEVINFO_OPA0CAL5_CM1_SHIFT 0

#define	_DEVINFO_OPA0CAL5_CM2_MASK 0x1E0UL

#define	_DEVINFO_OPA0CAL5_CM2_SHIFT 5

#define	_DEVINFO_OPA0CAL5_CM3_MASK 0xC00UL

#define	_DEVINFO_OPA0CAL5_CM3_SHIFT 10

#define	_DEVINFO_OPA0CAL5_GM3_MASK 0x60000UL

#define	_DEVINFO_OPA0CAL5_GM3_SHIFT 17

#define	_DEVINFO_OPA0CAL5_GM_MASK 0xE000UL

#define	_DEVINFO_OPA0CAL5_GM_SHIFT 13

#define	_DEVINFO_OPA0CAL5_MASK 0x7DF6EDEFUL

#define	_DEVINFO_OPA0CAL5_OFFSETN_MASK 0x7C000000UL

#define	_DEVINFO_OPA0CAL5_OFFSETN_SHIFT 26

#define	_DEVINFO_OPA0CAL5_OFFSETP_MASK 0x1F00000UL

#define	_DEVINFO_OPA0CAL5_OFFSETP_SHIFT 20

#define	_DEVINFO_OPA0CAL6_CM1_MASK 0xFUL

#define	_DEVINFO_OPA0CAL6_CM1_SHIFT 0

#define	_DEVINFO_OPA0CAL6_CM2_MASK 0x1E0UL

#define	_DEVINFO_OPA0CAL6_CM2_SHIFT 5

#define	_DEVINFO_OPA0CAL6_CM3_MASK 0xC00UL

#define	_DEVINFO_OPA0CAL6_CM3_SHIFT 10

#define	_DEVINFO_OPA0CAL6_GM3_MASK 0x60000UL

#define	_DEVINFO_OPA0CAL6_GM3_SHIFT 17

#define	_DEVINFO_OPA0CAL6_GM_MASK 0xE000UL

#define	_DEVINFO_OPA0CAL6_GM_SHIFT 13

#define	_DEVINFO_OPA0CAL6_MASK 0x7DF6EDEFUL

#define	_DEVINFO_OPA0CAL6_OFFSETN_MASK 0x7C000000UL

#define	_DEVINFO_OPA0CAL6_OFFSETN_SHIFT 26

#define	_DEVINFO_OPA0CAL6_OFFSETP_MASK 0x1F00000UL

#define	_DEVINFO_OPA0CAL6_OFFSETP_SHIFT 20

#define	_DEVINFO_OPA0CAL7_CM1_MASK 0xFUL

#define	_DEVINFO_OPA0CAL7_CM1_SHIFT 0

#define	_DEVINFO_OPA0CAL7_CM2_MASK 0x1E0UL

#define	_DEVINFO_OPA0CAL7_CM2_SHIFT 5

#define	_DEVINFO_OPA0CAL7_CM3_MASK 0xC00UL

#define	_DEVINFO_OPA0CAL7_CM3_SHIFT 10

#define	_DEVINFO_OPA0CAL7_GM3_MASK 0x60000UL

#define	_DEVINFO_OPA0CAL7_GM3_SHIFT 17

#define	_DEVINFO_OPA0CAL7_GM_MASK 0xE000UL

#define	_DEVINFO_OPA0CAL7_GM_SHIFT 13

#define	_DEVINFO_OPA0CAL7_MASK 0x7DF6EDEFUL

#define	_DEVINFO_OPA0CAL7_OFFSETN_MASK 0x7C000000UL

#define	_DEVINFO_OPA0CAL7_OFFSETN_SHIFT 26

#define	_DEVINFO_OPA0CAL7_OFFSETP_MASK 0x1F00000UL

#define	_DEVINFO_OPA0CAL7_OFFSETP_SHIFT 20

#define	_DEVINFO_OPA1CAL0_CM1_MASK 0xFUL

#define	_DEVINFO_OPA1CAL0_CM1_SHIFT 0

#define	_DEVINFO_OPA1CAL0_CM2_MASK 0x1E0UL

#define	_DEVINFO_OPA1CAL0_CM2_SHIFT 5

#define	_DEVINFO_OPA1CAL0_CM3_MASK 0xC00UL

#define	_DEVINFO_OPA1CAL0_CM3_SHIFT 10

#define	_DEVINFO_OPA1CAL0_GM3_MASK 0x60000UL

#define	_DEVINFO_OPA1CAL0_GM3_SHIFT 17

#define	_DEVINFO_OPA1CAL0_GM_MASK 0xE000UL

#define	_DEVINFO_OPA1CAL0_GM_SHIFT 13

#define	_DEVINFO_OPA1CAL0_MASK 0x7DF6EDEFUL

#define	_DEVINFO_OPA1CAL0_OFFSETN_MASK 0x7C000000UL

#define	_DEVINFO_OPA1CAL0_OFFSETN_SHIFT 26

#define	_DEVINFO_OPA1CAL0_OFFSETP_MASK 0x1F00000UL

#define	_DEVINFO_OPA1CAL0_OFFSETP_SHIFT 20

#define	_DEVINFO_OPA1CAL1_CM1_MASK 0xFUL

#define	_DEVINFO_OPA1CAL1_CM1_SHIFT 0

#define	_DEVINFO_OPA1CAL1_CM2_MASK 0x1E0UL

#define	_DEVINFO_OPA1CAL1_CM2_SHIFT 5

#define	_DEVINFO_OPA1CAL1_CM3_MASK 0xC00UL

#define	_DEVINFO_OPA1CAL1_CM3_SHIFT 10

#define	_DEVINFO_OPA1CAL1_GM3_MASK 0x60000UL

#define	_DEVINFO_OPA1CAL1_GM3_SHIFT 17

#define	_DEVINFO_OPA1CAL1_GM_MASK 0xE000UL

#define	_DEVINFO_OPA1CAL1_GM_SHIFT 13

#define	_DEVINFO_OPA1CAL1_MASK 0x7DF6EDEFUL

#define	_DEVINFO_OPA1CAL1_OFFSETN_MASK 0x7C000000UL

#define	_DEVINFO_OPA1CAL1_OFFSETN_SHIFT 26

#define	_DEVINFO_OPA1CAL1_OFFSETP_MASK 0x1F00000UL

#define	_DEVINFO_OPA1CAL1_OFFSETP_SHIFT 20

#define	_DEVINFO_OPA1CAL2_CM1_MASK 0xFUL

#define	_DEVINFO_OPA1CAL2_CM1_SHIFT 0

#define	_DEVINFO_OPA1CAL2_CM2_MASK 0x1E0UL

#define	_DEVINFO_OPA1CAL2_CM2_SHIFT 5

#define	_DEVINFO_OPA1CAL2_CM3_MASK 0xC00UL

#define	_DEVINFO_OPA1CAL2_CM3_SHIFT 10

#define	_DEVINFO_OPA1CAL2_GM3_MASK 0x60000UL

#define	_DEVINFO_OPA1CAL2_GM3_SHIFT 17

#define	_DEVINFO_OPA1CAL2_GM_MASK 0xE000UL

#define	_DEVINFO_OPA1CAL2_GM_SHIFT 13

#define	_DEVINFO_OPA1CAL2_MASK 0x7DF6EDEFUL

#define	_DEVINFO_OPA1CAL2_OFFSETN_MASK 0x7C000000UL

#define	_DEVINFO_OPA1CAL2_OFFSETN_SHIFT 26

#define	_DEVINFO_OPA1CAL2_OFFSETP_MASK 0x1F00000UL

#define	_DEVINFO_OPA1CAL2_OFFSETP_SHIFT 20

#define	_DEVINFO_OPA1CAL3_CM1_MASK 0xFUL

#define	_DEVINFO_OPA1CAL3_CM1_SHIFT 0

#define	_DEVINFO_OPA1CAL3_CM2_MASK 0x1E0UL

#define	_DEVINFO_OPA1CAL3_CM2_SHIFT 5

#define	_DEVINFO_OPA1CAL3_CM3_MASK 0xC00UL

#define	_DEVINFO_OPA1CAL3_CM3_SHIFT 10

#define	_DEVINFO_OPA1CAL3_GM3_MASK 0x60000UL

#define	_DEVINFO_OPA1CAL3_GM3_SHIFT 17

#define	_DEVINFO_OPA1CAL3_GM_MASK 0xE000UL

#define	_DEVINFO_OPA1CAL3_GM_SHIFT 13

#define	_DEVINFO_OPA1CAL3_MASK 0x7DF6EDEFUL

#define	_DEVINFO_OPA1CAL3_OFFSETN_MASK 0x7C000000UL

#define	_DEVINFO_OPA1CAL3_OFFSETN_SHIFT 26

#define	_DEVINFO_OPA1CAL3_OFFSETP_MASK 0x1F00000UL

#define	_DEVINFO_OPA1CAL3_OFFSETP_SHIFT 20

#define	_DEVINFO_OPA1CAL4_CM1_MASK 0xFUL

#define	_DEVINFO_OPA1CAL4_CM1_SHIFT 0

#define	_DEVINFO_OPA1CAL4_CM2_MASK 0x1E0UL

#define	_DEVINFO_OPA1CAL4_CM2_SHIFT 5

#define	_DEVINFO_OPA1CAL4_CM3_MASK 0xC00UL

#define	_DEVINFO_OPA1CAL4_CM3_SHIFT 10

#define	_DEVINFO_OPA1CAL4_GM3_MASK 0x60000UL

#define	_DEVINFO_OPA1CAL4_GM3_SHIFT 17

#define	_DEVINFO_OPA1CAL4_GM_MASK 0xE000UL

#define	_DEVINFO_OPA1CAL4_GM_SHIFT 13

#define	_DEVINFO_OPA1CAL4_MASK 0x7DF6EDEFUL

#define	_DEVINFO_OPA1CAL4_OFFSETN_MASK 0x7C000000UL

#define	_DEVINFO_OPA1CAL4_OFFSETN_SHIFT 26

#define	_DEVINFO_OPA1CAL4_OFFSETP_MASK 0x1F00000UL

#define	_DEVINFO_OPA1CAL4_OFFSETP_SHIFT 20

#define	_DEVINFO_OPA1CAL5_CM1_MASK 0xFUL

#define	_DEVINFO_OPA1CAL5_CM1_SHIFT 0

#define	_DEVINFO_OPA1CAL5_CM2_MASK 0x1E0UL

#define	_DEVINFO_OPA1CAL5_CM2_SHIFT 5

#define	_DEVINFO_OPA1CAL5_CM3_MASK 0xC00UL

#define	_DEVINFO_OPA1CAL5_CM3_SHIFT 10

#define	_DEVINFO_OPA1CAL5_GM3_MASK 0x60000UL

#define	_DEVINFO_OPA1CAL5_GM3_SHIFT 17

#define	_DEVINFO_OPA1CAL5_GM_MASK 0xE000UL

#define	_DEVINFO_OPA1CAL5_GM_SHIFT 13

#define	_DEVINFO_OPA1CAL5_MASK 0x7DF6EDEFUL

#define	_DEVINFO_OPA1CAL5_OFFSETN_MASK 0x7C000000UL

#define	_DEVINFO_OPA1CAL5_OFFSETN_SHIFT 26

#define	_DEVINFO_OPA1CAL5_OFFSETP_MASK 0x1F00000UL

#define	_DEVINFO_OPA1CAL5_OFFSETP_SHIFT 20

#define	_DEVINFO_OPA1CAL6_CM1_MASK 0xFUL

#define	_DEVINFO_OPA1CAL6_CM1_SHIFT 0

#define	_DEVINFO_OPA1CAL6_CM2_MASK 0x1E0UL

#define	_DEVINFO_OPA1CAL6_CM2_SHIFT 5

#define	_DEVINFO_OPA1CAL6_CM3_MASK 0xC00UL

#define	_DEVINFO_OPA1CAL6_CM3_SHIFT 10

#define	_DEVINFO_OPA1CAL6_GM3_MASK 0x60000UL

#define	_DEVINFO_OPA1CAL6_GM3_SHIFT 17

#define	_DEVINFO_OPA1CAL6_GM_MASK 0xE000UL

#define	_DEVINFO_OPA1CAL6_GM_SHIFT 13

#define	_DEVINFO_OPA1CAL6_MASK 0x7DF6EDEFUL

#define	_DEVINFO_OPA1CAL6_OFFSETN_MASK 0x7C000000UL

#define	_DEVINFO_OPA1CAL6_OFFSETN_SHIFT 26

#define	_DEVINFO_OPA1CAL6_OFFSETP_MASK 0x1F00000UL

#define	_DEVINFO_OPA1CAL6_OFFSETP_SHIFT 20

#define	_DEVINFO_OPA1CAL7_CM1_MASK 0xFUL

#define	_DEVINFO_OPA1CAL7_CM1_SHIFT 0

#define	_DEVINFO_OPA1CAL7_CM2_MASK 0x1E0UL

#define	_DEVINFO_OPA1CAL7_CM2_SHIFT 5

#define	_DEVINFO_OPA1CAL7_CM3_MASK 0xC00UL

#define	_DEVINFO_OPA1CAL7_CM3_SHIFT 10

#define	_DEVINFO_OPA1CAL7_GM3_MASK 0x60000UL

#define	_DEVINFO_OPA1CAL7_GM3_SHIFT 17

#define	_DEVINFO_OPA1CAL7_GM_MASK 0xE000UL

#define	_DEVINFO_OPA1CAL7_GM_SHIFT 13

#define	_DEVINFO_OPA1CAL7_MASK 0x7DF6EDEFUL

#define	_DEVINFO_OPA1CAL7_OFFSETN_MASK 0x7C000000UL

#define	_DEVINFO_OPA1CAL7_OFFSETN_SHIFT 26

#define	_DEVINFO_OPA1CAL7_OFFSETP_MASK 0x1F00000UL

#define	_DEVINFO_OPA1CAL7_OFFSETP_SHIFT 20

#define	_DEVINFO_PART_DEVICE_FAMILY_EFM32G 0x00000047UL

#define	_DEVINFO_PART_DEVICE_FAMILY_EFM32GG 0x00000048UL

#define	_DEVINFO_PART_DEVICE_FAMILY_EFM32GG11B 0x00000064UL

#define	_DEVINFO_PART_DEVICE_FAMILY_EFM32GG12B 0x0000006AUL

#define	_DEVINFO_PART_DEVICE_FAMILY_EFM32HG 0x0000004DUL

#define	_DEVINFO_PART_DEVICE_FAMILY_EFM32JG12B 0x00000057UL

#define	_DEVINFO_PART_DEVICE_FAMILY_EFM32JG1B 0x00000053UL

#define	_DEVINFO_PART_DEVICE_FAMILY_EFM32LG 0x0000004AUL

#define	_DEVINFO_PART_DEVICE_FAMILY_EFM32PG12B 0x00000055UL

#define	_DEVINFO_PART_DEVICE_FAMILY_EFM32PG1B 0x00000051UL

#define	_DEVINFO_PART_DEVICE_FAMILY_EFM32TG 0x00000049UL

#define	_DEVINFO_PART_DEVICE_FAMILY_EFM32TG11B 0x00000067UL

#define	_DEVINFO_PART_DEVICE_FAMILY_EFM32WG 0x0000004BUL

#define	_DEVINFO_PART_DEVICE_FAMILY_EFM32ZG 0x0000004CUL

#define	_DEVINFO_PART_DEVICE_FAMILY_EFR32BG12B 0x00000020UL

#define	_DEVINFO_PART_DEVICE_FAMILY_EFR32BG12P 0x0000001FUL

#define	_DEVINFO_PART_DEVICE_FAMILY_EFR32BG12V 0x00000021UL

#define	_DEVINFO_PART_DEVICE_FAMILY_EFR32BG13B 0x0000002CUL

#define	_DEVINFO_PART_DEVICE_FAMILY_EFR32BG13P 0x0000002BUL

#define	_DEVINFO_PART_DEVICE_FAMILY_EFR32BG13V 0x0000002DUL

#define	_DEVINFO_PART_DEVICE_FAMILY_EFR32BG14B 0x00000038UL

#define	_DEVINFO_PART_DEVICE_FAMILY_EFR32BG14P 0x00000037UL

#define	_DEVINFO_PART_DEVICE_FAMILY_EFR32BG14V 0x00000039UL

#define	_DEVINFO_PART_DEVICE_FAMILY_EFR32BG1B 0x00000014UL

#define	_DEVINFO_PART_DEVICE_FAMILY_EFR32BG1P 0x00000013UL

#define	_DEVINFO_PART_DEVICE_FAMILY_EFR32BG1V 0x00000015UL

#define	_DEVINFO_PART_DEVICE_FAMILY_EFR32FG12B 0x00000026UL

#define	_DEVINFO_PART_DEVICE_FAMILY_EFR32FG12P 0x00000025UL

#define	_DEVINFO_PART_DEVICE_FAMILY_EFR32FG12V 0x00000027UL

#define	_DEVINFO_PART_DEVICE_FAMILY_EFR32FG13B 0x00000032UL

#define	_DEVINFO_PART_DEVICE_FAMILY_EFR32FG13P 0x00000031UL

#define	_DEVINFO_PART_DEVICE_FAMILY_EFR32FG13V 0x00000033UL

#define	_DEVINFO_PART_DEVICE_FAMILY_EFR32FG14B 0x0000003EUL

#define	_DEVINFO_PART_DEVICE_FAMILY_EFR32FG14P 0x0000003DUL

#define	_DEVINFO_PART_DEVICE_FAMILY_EFR32FG14V 0x0000003FUL

#define	_DEVINFO_PART_DEVICE_FAMILY_EFR32FG1B 0x0000001AUL

#define	_DEVINFO_PART_DEVICE_FAMILY_EFR32FG1P 0x00000019UL

#define	_DEVINFO_PART_DEVICE_FAMILY_EFR32FG1V 0x0000001BUL

#define	_DEVINFO_PART_DEVICE_FAMILY_EFR32MG12B 0x0000001DUL

#define	_DEVINFO_PART_DEVICE_FAMILY_EFR32MG12P 0x0000001CUL

#define	_DEVINFO_PART_DEVICE_FAMILY_EFR32MG12V 0x0000001EUL

#define	_DEVINFO_PART_DEVICE_FAMILY_EFR32MG13B 0x00000029UL

#define	_DEVINFO_PART_DEVICE_FAMILY_EFR32MG13P 0x00000028UL

#define	_DEVINFO_PART_DEVICE_FAMILY_EFR32MG13V 0x0000002AUL

#define	_DEVINFO_PART_DEVICE_FAMILY_EFR32MG14B 0x00000035UL

#define	_DEVINFO_PART_DEVICE_FAMILY_EFR32MG14P 0x00000034UL

#define	_DEVINFO_PART_DEVICE_FAMILY_EFR32MG14V 0x00000036UL

#define	_DEVINFO_PART_DEVICE_FAMILY_EFR32MG1B 0x00000011UL

#define	_DEVINFO_PART_DEVICE_FAMILY_EFR32MG1P 0x00000010UL

#define	_DEVINFO_PART_DEVICE_FAMILY_EFR32MG1V 0x00000012UL

#define	_DEVINFO_PART_DEVICE_FAMILY_EFR32ZG13P 0x0000002EUL

#define	_DEVINFO_PART_DEVICE_FAMILY_EFR32ZG14P 0x0000003AUL

#define	_DEVINFO_PART_DEVICE_FAMILY_EZR32HG 0x0000007AUL

#define	_DEVINFO_PART_DEVICE_FAMILY_EZR32LG 0x00000078UL

#define	_DEVINFO_PART_DEVICE_FAMILY_EZR32WG 0x00000079UL

#define	_DEVINFO_PART_DEVICE_FAMILY_G 0x00000047UL

#define	_DEVINFO_PART_DEVICE_FAMILY_GG 0x00000048UL

#define	_DEVINFO_PART_DEVICE_FAMILY_HG 0x0000004DUL

#define	_DEVINFO_PART_DEVICE_FAMILY_LG 0x0000004AUL

#define	_DEVINFO_PART_DEVICE_FAMILY_MASK 0xFF0000UL

#define	_DEVINFO_PART_DEVICE_FAMILY_SHIFT 16

#define	_DEVINFO_PART_DEVICE_FAMILY_TG 0x00000049UL

#define	_DEVINFO_PART_DEVICE_FAMILY_WG 0x0000004BUL

#define	_DEVINFO_PART_DEVICE_FAMILY_ZG 0x0000004CUL

#define	_DEVINFO_PART_DEVICE_NUMBER_MASK 0xFFFFUL

#define	_DEVINFO_PART_DEVICE_NUMBER_SHIFT 0

#define	_DEVINFO_PART_MASK 0xFFFFFFFFUL

#define	_DEVINFO_PART_PROD_REV_MASK 0xFF000000UL

#define	_DEVINFO_PART_PROD_REV_SHIFT 24

#define	_DEVINFO_UNIQUEH_MASK 0xFFFFFFFFUL

#define	_DEVINFO_UNIQUEH_UNIQUEH_MASK 0xFFFFFFFFUL

#define	_DEVINFO_UNIQUEH_UNIQUEH_SHIFT 0

#define	_DEVINFO_UNIQUEL_MASK 0xFFFFFFFFUL

#define	_DEVINFO_UNIQUEL_UNIQUEL_MASK 0xFFFFFFFFUL

#define	_DEVINFO_UNIQUEL_UNIQUEL_SHIFT 0

#define	_DEVINFO_VDAC0ALTCAL_GAINERRTRIM1V25ALT_MASK 0x3F000UL

#define	_DEVINFO_VDAC0ALTCAL_GAINERRTRIM1V25ALT_SHIFT 12

#define	_DEVINFO_VDAC0ALTCAL_GAINERRTRIM1V25LNALT_MASK 0x3FUL

#define	_DEVINFO_VDAC0ALTCAL_GAINERRTRIM1V25LNALT_SHIFT 0

#define	_DEVINFO_VDAC0ALTCAL_GAINERRTRIM2V5ALT_MASK 0xFC0000UL

#define	_DEVINFO_VDAC0ALTCAL_GAINERRTRIM2V5ALT_SHIFT 18

#define	_DEVINFO_VDAC0ALTCAL_GAINERRTRIM2V5LNALT_MASK 0xFC0UL

#define	_DEVINFO_VDAC0ALTCAL_GAINERRTRIM2V5LNALT_SHIFT 6

#define	_DEVINFO_VDAC0ALTCAL_GAINERRTRIMVDDANAEXTPINALT_MASK 0x3F000000UL

#define	_DEVINFO_VDAC0ALTCAL_GAINERRTRIMVDDANAEXTPINALT_SHIFT 24

#define	_DEVINFO_VDAC0ALTCAL_MASK 0x3FFFFFFFUL

#define	_DEVINFO_VDAC0CH1CAL_GAINERRTRIMCH1A_MASK 0xF0UL

#define	_DEVINFO_VDAC0CH1CAL_GAINERRTRIMCH1A_SHIFT 4

#define	_DEVINFO_VDAC0CH1CAL_GAINERRTRIMCH1B_MASK 0xF00UL

#define	_DEVINFO_VDAC0CH1CAL_GAINERRTRIMCH1B_SHIFT 8

#define	_DEVINFO_VDAC0CH1CAL_MASK 0x00000FF7UL

#define	_DEVINFO_VDAC0CH1CAL_OFFSETTRIM_MASK 0x7UL

#define	_DEVINFO_VDAC0CH1CAL_OFFSETTRIM_SHIFT 0

#define	_DEVINFO_VDAC0MAINCAL_GAINERRTRIM1V25_MASK 0x3F000UL

#define	_DEVINFO_VDAC0MAINCAL_GAINERRTRIM1V25_SHIFT 12

#define	_DEVINFO_VDAC0MAINCAL_GAINERRTRIM1V25LN_MASK 0x3FUL

#define	_DEVINFO_VDAC0MAINCAL_GAINERRTRIM1V25LN_SHIFT 0

#define	_DEVINFO_VDAC0MAINCAL_GAINERRTRIM2V5_MASK 0xFC0000UL

#define	_DEVINFO_VDAC0MAINCAL_GAINERRTRIM2V5_SHIFT 18

#define	_DEVINFO_VDAC0MAINCAL_GAINERRTRIM2V5LN_MASK 0xFC0UL

#define	_DEVINFO_VDAC0MAINCAL_GAINERRTRIM2V5LN_SHIFT 6

#define	_DEVINFO_VDAC0MAINCAL_GAINERRTRIMVDDANAEXTPIN_MASK 0x3F000000UL

#define	_DEVINFO_VDAC0MAINCAL_GAINERRTRIMVDDANAEXTPIN_SHIFT 24

#define	_DEVINFO_VDAC0MAINCAL_MASK 0x3FFFFFFFUL

#define	_DEVINFO_VMONCAL0_ALTAVDD1V86THRESCOARSE_MASK 0xF00000UL

#define	_DEVINFO_VMONCAL0_ALTAVDD1V86THRESCOARSE_SHIFT 20

#define	_DEVINFO_VMONCAL0_ALTAVDD1V86THRESFINE_MASK 0xF0000UL

#define	_DEVINFO_VMONCAL0_ALTAVDD1V86THRESFINE_SHIFT 16

#define	_DEVINFO_VMONCAL0_ALTAVDD2V98THRESCOARSE_MASK 0xF0000000UL

#define	_DEVINFO_VMONCAL0_ALTAVDD2V98THRESCOARSE_SHIFT 28

#define	_DEVINFO_VMONCAL0_ALTAVDD2V98THRESFINE_MASK 0xF000000UL

#define	_DEVINFO_VMONCAL0_ALTAVDD2V98THRESFINE_SHIFT 24

#define	_DEVINFO_VMONCAL0_AVDD1V86THRESCOARSE_MASK 0xF0UL

#define	_DEVINFO_VMONCAL0_AVDD1V86THRESCOARSE_SHIFT 4

#define	_DEVINFO_VMONCAL0_AVDD1V86THRESFINE_MASK 0xFUL

#define	_DEVINFO_VMONCAL0_AVDD1V86THRESFINE_SHIFT 0

#define	_DEVINFO_VMONCAL0_AVDD2V98THRESCOARSE_MASK 0xF000UL

#define	_DEVINFO_VMONCAL0_AVDD2V98THRESCOARSE_SHIFT 12

#define	_DEVINFO_VMONCAL0_AVDD2V98THRESFINE_MASK 0xF00UL

#define	_DEVINFO_VMONCAL0_AVDD2V98THRESFINE_SHIFT 8

#define	_DEVINFO_VMONCAL0_MASK 0xFFFFFFFFUL

#define	_DEVINFO_VMONCAL1_DVDD1V86THRESCOARSE_MASK 0xF0UL

#define	_DEVINFO_VMONCAL1_DVDD1V86THRESCOARSE_SHIFT 4

#define	_DEVINFO_VMONCAL1_DVDD1V86THRESFINE_MASK 0xFUL

#define	_DEVINFO_VMONCAL1_DVDD1V86THRESFINE_SHIFT 0

#define	_DEVINFO_VMONCAL1_DVDD2V98THRESCOARSE_MASK 0xF000UL

#define	_DEVINFO_VMONCAL1_DVDD2V98THRESCOARSE_SHIFT 12

#define	_DEVINFO_VMONCAL1_DVDD2V98THRESFINE_MASK 0xF00UL

#define	_DEVINFO_VMONCAL1_DVDD2V98THRESFINE_SHIFT 8

#define	_DEVINFO_VMONCAL1_IO01V86THRESCOARSE_MASK 0xF00000UL

#define	_DEVINFO_VMONCAL1_IO01V86THRESCOARSE_SHIFT 20

#define	_DEVINFO_VMONCAL1_IO01V86THRESFINE_MASK 0xF0000UL

#define	_DEVINFO_VMONCAL1_IO01V86THRESFINE_SHIFT 16

#define	_DEVINFO_VMONCAL1_IO02V98THRESCOARSE_MASK 0xF0000000UL

#define	_DEVINFO_VMONCAL1_IO02V98THRESCOARSE_SHIFT 28

#define	_DEVINFO_VMONCAL1_IO02V98THRESFINE_MASK 0xF000000UL

#define	_DEVINFO_VMONCAL1_IO02V98THRESFINE_SHIFT 24

#define	_DEVINFO_VMONCAL1_MASK 0xFFFFFFFFUL

#define	_DEVINFO_VMONCAL2_FVDD1V86THRESCOARSE_MASK 0xF00000UL

#define	_DEVINFO_VMONCAL2_FVDD1V86THRESCOARSE_SHIFT 20

#define	_DEVINFO_VMONCAL2_FVDD1V86THRESFINE_MASK 0xF0000UL

#define	_DEVINFO_VMONCAL2_FVDD1V86THRESFINE_SHIFT 16

#define	_DEVINFO_VMONCAL2_FVDD2V98THRESCOARSE_MASK 0xF0000000UL

#define	_DEVINFO_VMONCAL2_FVDD2V98THRESCOARSE_SHIFT 28

#define	_DEVINFO_VMONCAL2_FVDD2V98THRESFINE_MASK 0xF000000UL

#define	_DEVINFO_VMONCAL2_FVDD2V98THRESFINE_SHIFT 24

#define	_DEVINFO_VMONCAL2_MASK 0xFFFFFFFFUL

#define	_DEVINFO_VMONCAL2_PAVDD1V86THRESCOARSE_MASK 0xF0UL

#define	_DEVINFO_VMONCAL2_PAVDD1V86THRESCOARSE_SHIFT 4

#define	_DEVINFO_VMONCAL2_PAVDD1V86THRESFINE_MASK 0xFUL

#define	_DEVINFO_VMONCAL2_PAVDD1V86THRESFINE_SHIFT 0

#define	_DEVINFO_VMONCAL2_PAVDD2V98THRESCOARSE_MASK 0xF000UL

#define	_DEVINFO_VMONCAL2_PAVDD2V98THRESCOARSE_SHIFT 12

#define	_DEVINFO_VMONCAL2_PAVDD2V98THRESFINE_MASK 0xF00UL

#define	_DEVINFO_VMONCAL2_PAVDD2V98THRESFINE_SHIFT 8

#define	DEVINFO_EXTINFO_CONNECTION_NONE ( _DEVINFO_EXTINFO_CONNECTION_NONE << 8)

#define	DEVINFO_EXTINFO_CONNECTION_SPI ( _DEVINFO_EXTINFO_CONNECTION_SPI << 8)

#define	DEVINFO_EXTINFO_REV_NONE ( _DEVINFO_EXTINFO_REV_NONE << 16)

#define	DEVINFO_EXTINFO_REV_REV1 ( _DEVINFO_EXTINFO_REV_REV1 << 16)

#define	DEVINFO_EXTINFO_TYPE_AT25S041 ( _DEVINFO_EXTINFO_TYPE_AT25S041 << 0)

#define	DEVINFO_EXTINFO_TYPE_IS25LQ040B ( _DEVINFO_EXTINFO_TYPE_IS25LQ040B << 0)

#define	DEVINFO_EXTINFO_TYPE_NONE ( _DEVINFO_EXTINFO_TYPE_NONE << 0)

#define	DEVINFO_MEMINFO_PKGTYPE_BGA ( _DEVINFO_MEMINFO_PKGTYPE_BGA << 8)

#define	DEVINFO_MEMINFO_PKGTYPE_QFN ( _DEVINFO_MEMINFO_PKGTYPE_QFN << 8)

#define	DEVINFO_MEMINFO_PKGTYPE_QFP ( _DEVINFO_MEMINFO_PKGTYPE_QFP << 8)

#define	DEVINFO_MEMINFO_PKGTYPE_WLCSP ( _DEVINFO_MEMINFO_PKGTYPE_WLCSP << 8)

#define	DEVINFO_MEMINFO_TEMPGRADE_N0TO70 ( _DEVINFO_MEMINFO_TEMPGRADE_N0TO70 << 0)

#define	DEVINFO_MEMINFO_TEMPGRADE_N40TO105 ( _DEVINFO_MEMINFO_TEMPGRADE_N40TO105 << 0)

#define	DEVINFO_MEMINFO_TEMPGRADE_N40TO125 ( _DEVINFO_MEMINFO_TEMPGRADE_N40TO125 << 0)

#define	DEVINFO_MEMINFO_TEMPGRADE_N40TO85 ( _DEVINFO_MEMINFO_TEMPGRADE_N40TO85 << 0)

#define	DEVINFO_PART_DEVICE_FAMILY_EFM32G ( _DEVINFO_PART_DEVICE_FAMILY_EFM32G << 16)

#define	DEVINFO_PART_DEVICE_FAMILY_EFM32GG ( _DEVINFO_PART_DEVICE_FAMILY_EFM32GG << 16)

#define	DEVINFO_PART_DEVICE_FAMILY_EFM32GG11B ( _DEVINFO_PART_DEVICE_FAMILY_EFM32GG11B << 16)

#define	DEVINFO_PART_DEVICE_FAMILY_EFM32GG12B ( _DEVINFO_PART_DEVICE_FAMILY_EFM32GG12B << 16)

#define	DEVINFO_PART_DEVICE_FAMILY_EFM32HG ( _DEVINFO_PART_DEVICE_FAMILY_EFM32HG << 16)

#define	DEVINFO_PART_DEVICE_FAMILY_EFM32JG12B ( _DEVINFO_PART_DEVICE_FAMILY_EFM32JG12B << 16)

#define	DEVINFO_PART_DEVICE_FAMILY_EFM32JG1B ( _DEVINFO_PART_DEVICE_FAMILY_EFM32JG1B << 16)

#define	DEVINFO_PART_DEVICE_FAMILY_EFM32LG ( _DEVINFO_PART_DEVICE_FAMILY_EFM32LG << 16)

#define	DEVINFO_PART_DEVICE_FAMILY_EFM32PG12B ( _DEVINFO_PART_DEVICE_FAMILY_EFM32PG12B << 16)

#define	DEVINFO_PART_DEVICE_FAMILY_EFM32PG1B ( _DEVINFO_PART_DEVICE_FAMILY_EFM32PG1B << 16)

#define	DEVINFO_PART_DEVICE_FAMILY_EFM32TG ( _DEVINFO_PART_DEVICE_FAMILY_EFM32TG << 16)

#define	DEVINFO_PART_DEVICE_FAMILY_EFM32TG11B ( _DEVINFO_PART_DEVICE_FAMILY_EFM32TG11B << 16)

#define	DEVINFO_PART_DEVICE_FAMILY_EFM32WG ( _DEVINFO_PART_DEVICE_FAMILY_EFM32WG << 16)

#define	DEVINFO_PART_DEVICE_FAMILY_EFM32ZG ( _DEVINFO_PART_DEVICE_FAMILY_EFM32ZG << 16)

#define	DEVINFO_PART_DEVICE_FAMILY_EFR32BG12B ( _DEVINFO_PART_DEVICE_FAMILY_EFR32BG12B << 16)

#define	DEVINFO_PART_DEVICE_FAMILY_EFR32BG12P ( _DEVINFO_PART_DEVICE_FAMILY_EFR32BG12P << 16)

#define	DEVINFO_PART_DEVICE_FAMILY_EFR32BG12V ( _DEVINFO_PART_DEVICE_FAMILY_EFR32BG12V << 16)

#define	DEVINFO_PART_DEVICE_FAMILY_EFR32BG13B ( _DEVINFO_PART_DEVICE_FAMILY_EFR32BG13B << 16)

#define	DEVINFO_PART_DEVICE_FAMILY_EFR32BG13P ( _DEVINFO_PART_DEVICE_FAMILY_EFR32BG13P << 16)

#define	DEVINFO_PART_DEVICE_FAMILY_EFR32BG13V ( _DEVINFO_PART_DEVICE_FAMILY_EFR32BG13V << 16)

#define	DEVINFO_PART_DEVICE_FAMILY_EFR32BG14B ( _DEVINFO_PART_DEVICE_FAMILY_EFR32BG14B << 16)

#define	DEVINFO_PART_DEVICE_FAMILY_EFR32BG14P ( _DEVINFO_PART_DEVICE_FAMILY_EFR32BG14P << 16)

#define	DEVINFO_PART_DEVICE_FAMILY_EFR32BG14V ( _DEVINFO_PART_DEVICE_FAMILY_EFR32BG14V << 16)

#define	DEVINFO_PART_DEVICE_FAMILY_EFR32BG1B ( _DEVINFO_PART_DEVICE_FAMILY_EFR32BG1B << 16)

#define	DEVINFO_PART_DEVICE_FAMILY_EFR32BG1P ( _DEVINFO_PART_DEVICE_FAMILY_EFR32BG1P << 16)

#define	DEVINFO_PART_DEVICE_FAMILY_EFR32BG1V ( _DEVINFO_PART_DEVICE_FAMILY_EFR32BG1V << 16)

#define	DEVINFO_PART_DEVICE_FAMILY_EFR32FG12B ( _DEVINFO_PART_DEVICE_FAMILY_EFR32FG12B << 16)

#define	DEVINFO_PART_DEVICE_FAMILY_EFR32FG12P ( _DEVINFO_PART_DEVICE_FAMILY_EFR32FG12P << 16)

#define	DEVINFO_PART_DEVICE_FAMILY_EFR32FG12V ( _DEVINFO_PART_DEVICE_FAMILY_EFR32FG12V << 16)

#define	DEVINFO_PART_DEVICE_FAMILY_EFR32FG13B ( _DEVINFO_PART_DEVICE_FAMILY_EFR32FG13B << 16)

#define	DEVINFO_PART_DEVICE_FAMILY_EFR32FG13P ( _DEVINFO_PART_DEVICE_FAMILY_EFR32FG13P << 16)

#define	DEVINFO_PART_DEVICE_FAMILY_EFR32FG13V ( _DEVINFO_PART_DEVICE_FAMILY_EFR32FG13V << 16)

#define	DEVINFO_PART_DEVICE_FAMILY_EFR32FG14B ( _DEVINFO_PART_DEVICE_FAMILY_EFR32FG14B << 16)

#define	DEVINFO_PART_DEVICE_FAMILY_EFR32FG14P ( _DEVINFO_PART_DEVICE_FAMILY_EFR32FG14P << 16)

#define	DEVINFO_PART_DEVICE_FAMILY_EFR32FG14V ( _DEVINFO_PART_DEVICE_FAMILY_EFR32FG14V << 16)

#define	DEVINFO_PART_DEVICE_FAMILY_EFR32FG1B ( _DEVINFO_PART_DEVICE_FAMILY_EFR32FG1B << 16)

#define	DEVINFO_PART_DEVICE_FAMILY_EFR32FG1P ( _DEVINFO_PART_DEVICE_FAMILY_EFR32FG1P << 16)

#define	DEVINFO_PART_DEVICE_FAMILY_EFR32FG1V ( _DEVINFO_PART_DEVICE_FAMILY_EFR32FG1V << 16)

#define	DEVINFO_PART_DEVICE_FAMILY_EFR32MG12B ( _DEVINFO_PART_DEVICE_FAMILY_EFR32MG12B << 16)

#define	DEVINFO_PART_DEVICE_FAMILY_EFR32MG12P ( _DEVINFO_PART_DEVICE_FAMILY_EFR32MG12P << 16)

#define	DEVINFO_PART_DEVICE_FAMILY_EFR32MG12V ( _DEVINFO_PART_DEVICE_FAMILY_EFR32MG12V << 16)

#define	DEVINFO_PART_DEVICE_FAMILY_EFR32MG13B ( _DEVINFO_PART_DEVICE_FAMILY_EFR32MG13B << 16)

#define	DEVINFO_PART_DEVICE_FAMILY_EFR32MG13P ( _DEVINFO_PART_DEVICE_FAMILY_EFR32MG13P << 16)

#define	DEVINFO_PART_DEVICE_FAMILY_EFR32MG13V ( _DEVINFO_PART_DEVICE_FAMILY_EFR32MG13V << 16)

#define	DEVINFO_PART_DEVICE_FAMILY_EFR32MG14B ( _DEVINFO_PART_DEVICE_FAMILY_EFR32MG14B << 16)

#define	DEVINFO_PART_DEVICE_FAMILY_EFR32MG14P ( _DEVINFO_PART_DEVICE_FAMILY_EFR32MG14P << 16)

#define	DEVINFO_PART_DEVICE_FAMILY_EFR32MG14V ( _DEVINFO_PART_DEVICE_FAMILY_EFR32MG14V << 16)

#define	DEVINFO_PART_DEVICE_FAMILY_EFR32MG1B ( _DEVINFO_PART_DEVICE_FAMILY_EFR32MG1B << 16)

#define	DEVINFO_PART_DEVICE_FAMILY_EFR32MG1P ( _DEVINFO_PART_DEVICE_FAMILY_EFR32MG1P << 16)

#define	DEVINFO_PART_DEVICE_FAMILY_EFR32MG1V ( _DEVINFO_PART_DEVICE_FAMILY_EFR32MG1V << 16)

#define	DEVINFO_PART_DEVICE_FAMILY_EFR32ZG13P ( _DEVINFO_PART_DEVICE_FAMILY_EFR32ZG13P << 16)

#define	DEVINFO_PART_DEVICE_FAMILY_EFR32ZG14P ( _DEVINFO_PART_DEVICE_FAMILY_EFR32ZG14P << 16)

#define	DEVINFO_PART_DEVICE_FAMILY_EZR32HG ( _DEVINFO_PART_DEVICE_FAMILY_EZR32HG << 16)

#define	DEVINFO_PART_DEVICE_FAMILY_EZR32LG ( _DEVINFO_PART_DEVICE_FAMILY_EZR32LG << 16)

#define	DEVINFO_PART_DEVICE_FAMILY_EZR32WG ( _DEVINFO_PART_DEVICE_FAMILY_EZR32WG << 16)

#define	DEVINFO_PART_DEVICE_FAMILY_G ( _DEVINFO_PART_DEVICE_FAMILY_G << 16)

#define	DEVINFO_PART_DEVICE_FAMILY_GG ( _DEVINFO_PART_DEVICE_FAMILY_GG << 16)

#define	DEVINFO_PART_DEVICE_FAMILY_HG ( _DEVINFO_PART_DEVICE_FAMILY_HG << 16)

#define	DEVINFO_PART_DEVICE_FAMILY_LG ( _DEVINFO_PART_DEVICE_FAMILY_LG << 16)

#define	DEVINFO_PART_DEVICE_FAMILY_TG ( _DEVINFO_PART_DEVICE_FAMILY_TG << 16)

#define	DEVINFO_PART_DEVICE_FAMILY_WG ( _DEVINFO_PART_DEVICE_FAMILY_WG << 16)

#define	DEVINFO_PART_DEVICE_FAMILY_ZG ( _DEVINFO_PART_DEVICE_FAMILY_ZG << 16)

Macro Definition Documentation

#define _DEVINFO_ADC0CAL0_GAIN1V25_MASK 0x7F00UL

Bit mask for GAIN1V25

Definition at line 384 of file efr32bg14p_devinfo.h .

#define _DEVINFO_ADC0CAL0_GAIN1V25_SHIFT 8

Shift value for GAIN1V25

Definition at line 383 of file efr32bg14p_devinfo.h .

#define _DEVINFO_ADC0CAL0_GAIN2V5_MASK 0x7F000000UL

Bit mask for GAIN2V5

Definition at line 390 of file efr32bg14p_devinfo.h .

#define _DEVINFO_ADC0CAL0_GAIN2V5_SHIFT 24

Shift value for GAIN2V5

Definition at line 389 of file efr32bg14p_devinfo.h .

#define _DEVINFO_ADC0CAL0_MASK 0x7FFF7FFFUL

Mask for DEVINFO_ADC0CAL0

Definition at line 378 of file efr32bg14p_devinfo.h .

#define _DEVINFO_ADC0CAL0_NEGSEOFFSET1V25_MASK 0xF0UL

Bit mask for NEGSEOFFSET1V25

Definition at line 382 of file efr32bg14p_devinfo.h .

#define _DEVINFO_ADC0CAL0_NEGSEOFFSET1V25_SHIFT 4

Shift value for NEGSEOFFSET1V25

Definition at line 381 of file efr32bg14p_devinfo.h .

#define _DEVINFO_ADC0CAL0_NEGSEOFFSET2V5_MASK 0xF00000UL

Bit mask for NEGSEOFFSET2V5

Definition at line 388 of file efr32bg14p_devinfo.h .

#define _DEVINFO_ADC0CAL0_NEGSEOFFSET2V5_SHIFT 20

Shift value for NEGSEOFFSET2V5

Definition at line 387 of file efr32bg14p_devinfo.h .

#define _DEVINFO_ADC0CAL0_OFFSET1V25_MASK 0xFUL

Bit mask for OFFSET1V25

Definition at line 380 of file efr32bg14p_devinfo.h .

#define _DEVINFO_ADC0CAL0_OFFSET1V25_SHIFT 0

Shift value for OFFSET1V25

Definition at line 379 of file efr32bg14p_devinfo.h .

#define _DEVINFO_ADC0CAL0_OFFSET2V5_MASK 0xF0000UL

Bit mask for OFFSET2V5

Definition at line 386 of file efr32bg14p_devinfo.h .

#define _DEVINFO_ADC0CAL0_OFFSET2V5_SHIFT 16

Shift value for OFFSET2V5

Definition at line 385 of file efr32bg14p_devinfo.h .

#define _DEVINFO_ADC0CAL1_GAIN5VDIFF_MASK 0x7F000000UL

Bit mask for GAIN5VDIFF

Definition at line 405 of file efr32bg14p_devinfo.h .

#define _DEVINFO_ADC0CAL1_GAIN5VDIFF_SHIFT 24

Shift value for GAIN5VDIFF

Definition at line 404 of file efr32bg14p_devinfo.h .

#define _DEVINFO_ADC0CAL1_GAINVDD_MASK 0x7F00UL

Bit mask for GAINVDD

Definition at line 399 of file efr32bg14p_devinfo.h .

#define _DEVINFO_ADC0CAL1_GAINVDD_SHIFT 8

Shift value for GAINVDD

Definition at line 398 of file efr32bg14p_devinfo.h .

#define _DEVINFO_ADC0CAL1_MASK 0x7FFF7FFFUL

Mask for DEVINFO_ADC0CAL1

Definition at line 393 of file efr32bg14p_devinfo.h .

#define _DEVINFO_ADC0CAL1_NEGSEOFFSET5VDIFF_MASK 0xF00000UL

Bit mask for NEGSEOFFSET5VDIFF

Definition at line 403 of file efr32bg14p_devinfo.h .

#define _DEVINFO_ADC0CAL1_NEGSEOFFSET5VDIFF_SHIFT 20

Shift value for NEGSEOFFSET5VDIFF

Definition at line 402 of file efr32bg14p_devinfo.h .

#define _DEVINFO_ADC0CAL1_NEGSEOFFSETVDD_MASK 0xF0UL

Bit mask for NEGSEOFFSETVDD

Definition at line 397 of file efr32bg14p_devinfo.h .

#define _DEVINFO_ADC0CAL1_NEGSEOFFSETVDD_SHIFT 4

Shift value for NEGSEOFFSETVDD

Definition at line 396 of file efr32bg14p_devinfo.h .

#define _DEVINFO_ADC0CAL1_OFFSET5VDIFF_MASK 0xF0000UL

Bit mask for OFFSET5VDIFF

Definition at line 401 of file efr32bg14p_devinfo.h .

#define _DEVINFO_ADC0CAL1_OFFSET5VDIFF_SHIFT 16

Shift value for OFFSET5VDIFF

Definition at line 400 of file efr32bg14p_devinfo.h .

#define _DEVINFO_ADC0CAL1_OFFSETVDD_MASK 0xFUL

Bit mask for OFFSETVDD

Definition at line 395 of file efr32bg14p_devinfo.h .

#define _DEVINFO_ADC0CAL1_OFFSETVDD_SHIFT 0

Shift value for OFFSETVDD

Definition at line 394 of file efr32bg14p_devinfo.h .

#define _DEVINFO_ADC0CAL2_MASK 0x000000FFUL

Mask for DEVINFO_ADC0CAL2

Definition at line 408 of file efr32bg14p_devinfo.h .

#define _DEVINFO_ADC0CAL2_NEGSEOFFSET2XVDD_MASK 0xF0UL

Bit mask for NEGSEOFFSET2XVDD

Definition at line 412 of file efr32bg14p_devinfo.h .

#define _DEVINFO_ADC0CAL2_NEGSEOFFSET2XVDD_SHIFT 4

Shift value for NEGSEOFFSET2XVDD

Definition at line 411 of file efr32bg14p_devinfo.h .

#define _DEVINFO_ADC0CAL2_OFFSET2XVDD_MASK 0xFUL

Bit mask for OFFSET2XVDD

Definition at line 410 of file efr32bg14p_devinfo.h .

#define _DEVINFO_ADC0CAL2_OFFSET2XVDD_SHIFT 0

Shift value for OFFSET2XVDD

Definition at line 409 of file efr32bg14p_devinfo.h .

#define _DEVINFO_ADC0CAL3_MASK 0x0000FFF0UL

Mask for DEVINFO_ADC0CAL3

Definition at line 415 of file efr32bg14p_devinfo.h .

#define _DEVINFO_ADC0CAL3_TEMPREAD1V25_MASK 0xFFF0UL

Bit mask for TEMPREAD1V25

Definition at line 417 of file efr32bg14p_devinfo.h .

#define _DEVINFO_ADC0CAL3_TEMPREAD1V25_SHIFT 4

Shift value for TEMPREAD1V25

Definition at line 416 of file efr32bg14p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL0_CLKDIV_MASK 0x6000000UL

Bit mask for CLKDIV

Definition at line 584 of file efr32bg14p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL0_CLKDIV_SHIFT 25

Shift value for CLKDIV

Definition at line 583 of file efr32bg14p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL0_CMPBIAS_MASK 0xE00000UL

Bit mask for CMPBIAS

Definition at line 580 of file efr32bg14p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL0_CMPBIAS_SHIFT 21

Shift value for CMPBIAS

Definition at line 579 of file efr32bg14p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL0_FINETUNING_MASK 0x3F00UL

Bit mask for FINETUNING

Definition at line 576 of file efr32bg14p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL0_FINETUNING_SHIFT 8

Shift value for FINETUNING

Definition at line 575 of file efr32bg14p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL0_FINETUNINGEN_MASK 0x8000000UL

Bit mask for FINETUNINGEN

Definition at line 586 of file efr32bg14p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL0_FINETUNINGEN_SHIFT 27

Shift value for FINETUNINGEN

Definition at line 585 of file efr32bg14p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL0_FREQRANGE_MASK 0x1F0000UL

Bit mask for FREQRANGE

Definition at line 578 of file efr32bg14p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL0_FREQRANGE_SHIFT 16

Shift value for FREQRANGE

Definition at line 577 of file efr32bg14p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL0_LDOHP_MASK 0x1000000UL

Bit mask for LDOHP

Definition at line 582 of file efr32bg14p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL0_LDOHP_SHIFT 24

Shift value for LDOHP

Definition at line 581 of file efr32bg14p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL0_MASK 0xFFFF3F7FUL

Mask for DEVINFO_AUXHFRCOCAL0

Definition at line 572 of file efr32bg14p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL0_TUNING_MASK 0x7FUL

Bit mask for TUNING

Definition at line 574 of file efr32bg14p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL0_TUNING_SHIFT 0

Shift value for TUNING

Definition at line 573 of file efr32bg14p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL0_VREFTC_MASK 0xF0000000UL

Bit mask for VREFTC

Definition at line 588 of file efr32bg14p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL0_VREFTC_SHIFT 28

Shift value for VREFTC

Definition at line 587 of file efr32bg14p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL10_CLKDIV_MASK 0x6000000UL

Bit mask for CLKDIV

Definition at line 679 of file efr32bg14p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL10_CLKDIV_SHIFT 25

Shift value for CLKDIV

Definition at line 678 of file efr32bg14p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL10_CMPBIAS_MASK 0xE00000UL

Bit mask for CMPBIAS

Definition at line 675 of file efr32bg14p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL10_CMPBIAS_SHIFT 21

Shift value for CMPBIAS

Definition at line 674 of file efr32bg14p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL10_FINETUNING_MASK 0x3F00UL

Bit mask for FINETUNING

Definition at line 671 of file efr32bg14p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL10_FINETUNING_SHIFT 8

Shift value for FINETUNING

Definition at line 670 of file efr32bg14p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL10_FINETUNINGEN_MASK 0x8000000UL

Bit mask for FINETUNINGEN

Definition at line 681 of file efr32bg14p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL10_FINETUNINGEN_SHIFT 27

Shift value for FINETUNINGEN

Definition at line 680 of file efr32bg14p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL10_FREQRANGE_MASK 0x1F0000UL

Bit mask for FREQRANGE

Definition at line 673 of file efr32bg14p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL10_FREQRANGE_SHIFT 16

Shift value for FREQRANGE

Definition at line 672 of file efr32bg14p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL10_LDOHP_MASK 0x1000000UL

Bit mask for LDOHP

Definition at line 677 of file efr32bg14p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL10_LDOHP_SHIFT 24

Shift value for LDOHP

Definition at line 676 of file efr32bg14p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL10_MASK 0xFFFF3F7FUL

Mask for DEVINFO_AUXHFRCOCAL10

Definition at line 667 of file efr32bg14p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL10_TUNING_MASK 0x7FUL

Bit mask for TUNING

Definition at line 669 of file efr32bg14p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL10_TUNING_SHIFT 0

Shift value for TUNING

Definition at line 668 of file efr32bg14p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL10_VREFTC_MASK 0xF0000000UL

Bit mask for VREFTC

Definition at line 683 of file efr32bg14p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL10_VREFTC_SHIFT 28

Shift value for VREFTC

Definition at line 682 of file efr32bg14p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL11_CLKDIV_MASK 0x6000000UL

Bit mask for CLKDIV

Definition at line 698 of file efr32bg14p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL11_CLKDIV_SHIFT 25

Shift value for CLKDIV

Definition at line 697 of file efr32bg14p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL11_CMPBIAS_MASK 0xE00000UL

Bit mask for CMPBIAS

Definition at line 694 of file efr32bg14p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL11_CMPBIAS_SHIFT 21

Shift value for CMPBIAS

Definition at line 693 of file efr32bg14p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL11_FINETUNING_MASK 0x3F00UL

Bit mask for FINETUNING

Definition at line 690 of file efr32bg14p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL11_FINETUNING_SHIFT 8

Shift value for FINETUNING

Definition at line 689 of file efr32bg14p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL11_FINETUNINGEN_MASK 0x8000000UL

Bit mask for FINETUNINGEN

Definition at line 700 of file efr32bg14p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL11_FINETUNINGEN_SHIFT 27

Shift value for FINETUNINGEN

Definition at line 699 of file efr32bg14p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL11_FREQRANGE_MASK 0x1F0000UL

Bit mask for FREQRANGE

Definition at line 692 of file efr32bg14p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL11_FREQRANGE_SHIFT 16

Shift value for FREQRANGE

Definition at line 691 of file efr32bg14p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL11_LDOHP_MASK 0x1000000UL

Bit mask for LDOHP

Definition at line 696 of file efr32bg14p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL11_LDOHP_SHIFT 24

Shift value for LDOHP

Definition at line 695 of file efr32bg14p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL11_MASK 0xFFFF3F7FUL

Mask for DEVINFO_AUXHFRCOCAL11

Definition at line 686 of file efr32bg14p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL11_TUNING_MASK 0x7FUL

Bit mask for TUNING

Definition at line 688 of file efr32bg14p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL11_TUNING_SHIFT 0

Shift value for TUNING

Definition at line 687 of file efr32bg14p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL11_VREFTC_MASK 0xF0000000UL

Bit mask for VREFTC

Definition at line 702 of file efr32bg14p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL11_VREFTC_SHIFT 28

Shift value for VREFTC

Definition at line 701 of file efr32bg14p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL12_CLKDIV_MASK 0x6000000UL

Bit mask for CLKDIV

Definition at line 717 of file efr32bg14p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL12_CLKDIV_SHIFT 25

Shift value for CLKDIV

Definition at line 716 of file efr32bg14p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL12_CMPBIAS_MASK 0xE00000UL

Bit mask for CMPBIAS

Definition at line 713 of file efr32bg14p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL12_CMPBIAS_SHIFT 21

Shift value for CMPBIAS

Definition at line 712 of file efr32bg14p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL12_FINETUNING_MASK 0x3F00UL

Bit mask for FINETUNING

Definition at line 709 of file efr32bg14p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL12_FINETUNING_SHIFT 8

Shift value for FINETUNING

Definition at line 708 of file efr32bg14p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL12_FINETUNINGEN_MASK 0x8000000UL

Bit mask for FINETUNINGEN

Definition at line 719 of file efr32bg14p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL12_FINETUNINGEN_SHIFT 27

Shift value for FINETUNINGEN

Definition at line 718 of file efr32bg14p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL12_FREQRANGE_MASK 0x1F0000UL

Bit mask for FREQRANGE

Definition at line 711 of file efr32bg14p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL12_FREQRANGE_SHIFT 16

Shift value for FREQRANGE

Definition at line 710 of file efr32bg14p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL12_LDOHP_MASK 0x1000000UL

Bit mask for LDOHP

Definition at line 715 of file efr32bg14p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL12_LDOHP_SHIFT 24

Shift value for LDOHP

Definition at line 714 of file efr32bg14p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL12_MASK 0xFFFF3F7FUL

Mask for DEVINFO_AUXHFRCOCAL12

Definition at line 705 of file efr32bg14p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL12_TUNING_MASK 0x7FUL

Bit mask for TUNING

Definition at line 707 of file efr32bg14p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL12_TUNING_SHIFT 0

Shift value for TUNING

Definition at line 706 of file efr32bg14p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL12_VREFTC_MASK 0xF0000000UL

Bit mask for VREFTC

Definition at line 721 of file efr32bg14p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL12_VREFTC_SHIFT 28

Shift value for VREFTC

Definition at line 720 of file efr32bg14p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL3_CLKDIV_MASK 0x6000000UL

Bit mask for CLKDIV

Definition at line 603 of file efr32bg14p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL3_CLKDIV_SHIFT 25

Shift value for CLKDIV

Definition at line 602 of file efr32bg14p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL3_CMPBIAS_MASK 0xE00000UL

Bit mask for CMPBIAS

Definition at line 599 of file efr32bg14p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL3_CMPBIAS_SHIFT 21

Shift value for CMPBIAS

Definition at line 598 of file efr32bg14p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL3_FINETUNING_MASK 0x3F00UL

Bit mask for FINETUNING

Definition at line 595 of file efr32bg14p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL3_FINETUNING_SHIFT 8

Shift value for FINETUNING

Definition at line 594 of file efr32bg14p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL3_FINETUNINGEN_MASK 0x8000000UL

Bit mask for FINETUNINGEN

Definition at line 605 of file efr32bg14p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL3_FINETUNINGEN_SHIFT 27

Shift value for FINETUNINGEN

Definition at line 604 of file efr32bg14p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL3_FREQRANGE_MASK 0x1F0000UL

Bit mask for FREQRANGE

Definition at line 597 of file efr32bg14p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL3_FREQRANGE_SHIFT 16

Shift value for FREQRANGE

Definition at line 596 of file efr32bg14p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL3_LDOHP_MASK 0x1000000UL

Bit mask for LDOHP

Definition at line 601 of file efr32bg14p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL3_LDOHP_SHIFT 24

Shift value for LDOHP

Definition at line 600 of file efr32bg14p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL3_MASK 0xFFFF3F7FUL

Mask for DEVINFO_AUXHFRCOCAL3

Definition at line 591 of file efr32bg14p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL3_TUNING_MASK 0x7FUL

Bit mask for TUNING

Definition at line 593 of file efr32bg14p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL3_TUNING_SHIFT 0

Shift value for TUNING

Definition at line 592 of file efr32bg14p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL3_VREFTC_MASK 0xF0000000UL

Bit mask for VREFTC

Definition at line 607 of file efr32bg14p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL3_VREFTC_SHIFT 28

Shift value for VREFTC

Definition at line 606 of file efr32bg14p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL6_CLKDIV_MASK 0x6000000UL

Bit mask for CLKDIV

Definition at line 622 of file efr32bg14p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL6_CLKDIV_SHIFT 25

Shift value for CLKDIV

Definition at line 621 of file efr32bg14p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL6_CMPBIAS_MASK 0xE00000UL

Bit mask for CMPBIAS

Definition at line 618 of file efr32bg14p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL6_CMPBIAS_SHIFT 21

Shift value for CMPBIAS

Definition at line 617 of file efr32bg14p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL6_FINETUNING_MASK 0x3F00UL

Bit mask for FINETUNING

Definition at line 614 of file efr32bg14p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL6_FINETUNING_SHIFT 8

Shift value for FINETUNING

Definition at line 613 of file efr32bg14p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL6_FINETUNINGEN_MASK 0x8000000UL

Bit mask for FINETUNINGEN

Definition at line 624 of file efr32bg14p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL6_FINETUNINGEN_SHIFT 27

Shift value for FINETUNINGEN

Definition at line 623 of file efr32bg14p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL6_FREQRANGE_MASK 0x1F0000UL

Bit mask for FREQRANGE

Definition at line 616 of file efr32bg14p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL6_FREQRANGE_SHIFT 16

Shift value for FREQRANGE

Definition at line 615 of file efr32bg14p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL6_LDOHP_MASK 0x1000000UL

Bit mask for LDOHP

Definition at line 620 of file efr32bg14p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL6_LDOHP_SHIFT 24

Shift value for LDOHP

Definition at line 619 of file efr32bg14p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL6_MASK 0xFFFF3F7FUL

Mask for DEVINFO_AUXHFRCOCAL6

Definition at line 610 of file efr32bg14p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL6_TUNING_MASK 0x7FUL

Bit mask for TUNING

Definition at line 612 of file efr32bg14p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL6_TUNING_SHIFT 0

Shift value for TUNING

Definition at line 611 of file efr32bg14p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL6_VREFTC_MASK 0xF0000000UL

Bit mask for VREFTC

Definition at line 626 of file efr32bg14p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL6_VREFTC_SHIFT 28

Shift value for VREFTC

Definition at line 625 of file efr32bg14p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL7_CLKDIV_MASK 0x6000000UL

Bit mask for CLKDIV

Definition at line 641 of file efr32bg14p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL7_CLKDIV_SHIFT 25

Shift value for CLKDIV

Definition at line 640 of file efr32bg14p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL7_CMPBIAS_MASK 0xE00000UL

Bit mask for CMPBIAS

Definition at line 637 of file efr32bg14p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL7_CMPBIAS_SHIFT 21

Shift value for CMPBIAS

Definition at line 636 of file efr32bg14p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL7_FINETUNING_MASK 0x3F00UL

Bit mask for FINETUNING

Definition at line 633 of file efr32bg14p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL7_FINETUNING_SHIFT 8

Shift value for FINETUNING

Definition at line 632 of file efr32bg14p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL7_FINETUNINGEN_MASK 0x8000000UL

Bit mask for FINETUNINGEN

Definition at line 643 of file efr32bg14p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL7_FINETUNINGEN_SHIFT 27

Shift value for FINETUNINGEN

Definition at line 642 of file efr32bg14p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL7_FREQRANGE_MASK 0x1F0000UL

Bit mask for FREQRANGE

Definition at line 635 of file efr32bg14p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL7_FREQRANGE_SHIFT 16

Shift value for FREQRANGE

Definition at line 634 of file efr32bg14p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL7_LDOHP_MASK 0x1000000UL

Bit mask for LDOHP

Definition at line 639 of file efr32bg14p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL7_LDOHP_SHIFT 24

Shift value for LDOHP

Definition at line 638 of file efr32bg14p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL7_MASK 0xFFFF3F7FUL

Mask for DEVINFO_AUXHFRCOCAL7

Definition at line 629 of file efr32bg14p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL7_TUNING_MASK 0x7FUL

Bit mask for TUNING

Definition at line 631 of file efr32bg14p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL7_TUNING_SHIFT 0

Shift value for TUNING

Definition at line 630 of file efr32bg14p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL7_VREFTC_MASK 0xF0000000UL

Bit mask for VREFTC

Definition at line 645 of file efr32bg14p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL7_VREFTC_SHIFT 28

Shift value for VREFTC

Definition at line 644 of file efr32bg14p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL8_CLKDIV_MASK 0x6000000UL

Bit mask for CLKDIV

Definition at line 660 of file efr32bg14p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL8_CLKDIV_SHIFT 25

Shift value for CLKDIV

Definition at line 659 of file efr32bg14p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL8_CMPBIAS_MASK 0xE00000UL

Bit mask for CMPBIAS

Definition at line 656 of file efr32bg14p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL8_CMPBIAS_SHIFT 21

Shift value for CMPBIAS

Definition at line 655 of file efr32bg14p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL8_FINETUNING_MASK 0x3F00UL

Bit mask for FINETUNING

Definition at line 652 of file efr32bg14p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL8_FINETUNING_SHIFT 8

Shift value for FINETUNING

Definition at line 651 of file efr32bg14p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL8_FINETUNINGEN_MASK 0x8000000UL

Bit mask for FINETUNINGEN

Definition at line 662 of file efr32bg14p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL8_FINETUNINGEN_SHIFT 27

Shift value for FINETUNINGEN

Definition at line 661 of file efr32bg14p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL8_FREQRANGE_MASK 0x1F0000UL

Bit mask for FREQRANGE

Definition at line 654 of file efr32bg14p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL8_FREQRANGE_SHIFT 16

Shift value for FREQRANGE

Definition at line 653 of file efr32bg14p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL8_LDOHP_MASK 0x1000000UL

Bit mask for LDOHP

Definition at line 658 of file efr32bg14p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL8_LDOHP_SHIFT 24

Shift value for LDOHP

Definition at line 657 of file efr32bg14p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL8_MASK 0xFFFF3F7FUL

Mask for DEVINFO_AUXHFRCOCAL8

Definition at line 648 of file efr32bg14p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL8_TUNING_MASK 0x7FUL

Bit mask for TUNING

Definition at line 650 of file efr32bg14p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL8_TUNING_SHIFT 0

Shift value for TUNING

Definition at line 649 of file efr32bg14p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL8_VREFTC_MASK 0xF0000000UL

Bit mask for VREFTC

Definition at line 664 of file efr32bg14p_devinfo.h .

#define _DEVINFO_AUXHFRCOCAL8_VREFTC_SHIFT 28

Shift value for VREFTC

Definition at line 663 of file efr32bg14p_devinfo.h .

#define _DEVINFO_CAL_CRC_MASK 0xFFFFUL

Bit mask for CRC

Definition at line 141 of file efr32bg14p_devinfo.h .

#define _DEVINFO_CAL_CRC_SHIFT 0

Shift value for CRC

Definition at line 140 of file efr32bg14p_devinfo.h .

#define _DEVINFO_CAL_MASK 0x00FFFFFFUL

Mask for DEVINFO_CAL

Definition at line 139 of file efr32bg14p_devinfo.h .

#define _DEVINFO_CAL_TEMP_MASK 0xFF0000UL

Bit mask for TEMP

Definition at line 143 of file efr32bg14p_devinfo.h .

Referenced by calibration() , and SYSTEM_GetCalibrationTemperature() .

#define _DEVINFO_CAL_TEMP_SHIFT 16

Shift value for TEMP

Definition at line 142 of file efr32bg14p_devinfo.h .

Referenced by calibration() , and SYSTEM_GetCalibrationTemperature() .

#define _DEVINFO_CUSTOMINFO_MASK 0xFFFF0000UL

Mask for DEVINFO_CUSTOMINFO

Definition at line 186 of file efr32bg14p_devinfo.h .

#define _DEVINFO_CUSTOMINFO_PARTNO_MASK 0xFFFF0000UL

Bit mask for PARTNO

Definition at line 188 of file efr32bg14p_devinfo.h .

#define _DEVINFO_CUSTOMINFO_PARTNO_SHIFT 16

Shift value for PARTNO

Definition at line 187 of file efr32bg14p_devinfo.h .

#define _DEVINFO_DCDCLNVCTRL0_1V2LNATT0_MASK 0xFFUL

Bit mask for 1V2LNATT0

Definition at line 805 of file efr32bg14p_devinfo.h .

#define _DEVINFO_DCDCLNVCTRL0_1V2LNATT0_SHIFT 0

Shift value for 1V2LNATT0

Definition at line 804 of file efr32bg14p_devinfo.h .

#define _DEVINFO_DCDCLNVCTRL0_1V8LNATT0_MASK 0xFF00UL

Bit mask for 1V8LNATT0

Definition at line 807 of file efr32bg14p_devinfo.h .

#define _DEVINFO_DCDCLNVCTRL0_1V8LNATT0_SHIFT 8

Shift value for 1V8LNATT0

Definition at line 806 of file efr32bg14p_devinfo.h .

#define _DEVINFO_DCDCLNVCTRL0_1V8LNATT1_MASK 0xFF0000UL

Bit mask for 1V8LNATT1

Definition at line 809 of file efr32bg14p_devinfo.h .

#define _DEVINFO_DCDCLNVCTRL0_1V8LNATT1_SHIFT 16

Shift value for 1V8LNATT1

Definition at line 808 of file efr32bg14p_devinfo.h .

#define _DEVINFO_DCDCLNVCTRL0_3V0LNATT1_MASK 0xFF000000UL

Bit mask for 3V0LNATT1

Definition at line 811 of file efr32bg14p_devinfo.h .

#define _DEVINFO_DCDCLNVCTRL0_3V0LNATT1_SHIFT 24

Shift value for 3V0LNATT1

Definition at line 810 of file efr32bg14p_devinfo.h .

#define _DEVINFO_DCDCLNVCTRL0_MASK 0xFFFFFFFFUL

Mask for DEVINFO_DCDCLNVCTRL0

Definition at line 803 of file efr32bg14p_devinfo.h .

#define _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT0_MASK 0xFFUL

Bit mask for LPCMPHYSSELLPATT0

Definition at line 860 of file efr32bg14p_devinfo.h .

#define _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT0_SHIFT 0

Shift value for LPCMPHYSSELLPATT0

Definition at line 859 of file efr32bg14p_devinfo.h .

#define _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT1_MASK 0xFF00UL

Bit mask for LPCMPHYSSELLPATT1

Definition at line 862 of file efr32bg14p_devinfo.h .

#define _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT1_SHIFT 8

Shift value for LPCMPHYSSELLPATT1

Definition at line 861 of file efr32bg14p_devinfo.h .

#define _DEVINFO_DCDCLPCMPHYSSEL0_MASK 0x0000FFFFUL

Mask for DEVINFO_DCDCLPCMPHYSSEL0

Definition at line 858 of file efr32bg14p_devinfo.h .

#define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS0_MASK 0xFFUL

Bit mask for LPCMPHYSSELLPCMPBIAS0

Definition at line 867 of file efr32bg14p_devinfo.h .

#define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS0_SHIFT 0

Shift value for LPCMPHYSSELLPCMPBIAS0

Definition at line 866 of file efr32bg14p_devinfo.h .

#define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS1_MASK 0xFF00UL

Bit mask for LPCMPHYSSELLPCMPBIAS1

Definition at line 869 of file efr32bg14p_devinfo.h .

#define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS1_SHIFT 8

Shift value for LPCMPHYSSELLPCMPBIAS1

Definition at line 868 of file efr32bg14p_devinfo.h .

#define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS2_MASK 0xFF0000UL

Bit mask for LPCMPHYSSELLPCMPBIAS2

Definition at line 871 of file efr32bg14p_devinfo.h .

#define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS2_SHIFT 16

Shift value for LPCMPHYSSELLPCMPBIAS2

Definition at line 870 of file efr32bg14p_devinfo.h .

#define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS3_MASK 0xFF000000UL

Bit mask for LPCMPHYSSELLPCMPBIAS3

Definition at line 873 of file efr32bg14p_devinfo.h .

#define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS3_SHIFT 24

Shift value for LPCMPHYSSELLPCMPBIAS3

Definition at line 872 of file efr32bg14p_devinfo.h .

#define _DEVINFO_DCDCLPCMPHYSSEL1_MASK 0xFFFFFFFFUL

Mask for DEVINFO_DCDCLPCMPHYSSEL1

Definition at line 865 of file efr32bg14p_devinfo.h .

#define _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS0_MASK 0xFFUL

Bit mask for 1V2LPATT0LPCMPBIAS0

Definition at line 816 of file efr32bg14p_devinfo.h .

#define _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS0_SHIFT 0

Shift value for 1V2LPATT0LPCMPBIAS0

Definition at line 815 of file efr32bg14p_devinfo.h .

#define _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS1_MASK 0xFF0000UL

Bit mask for 1V2LPATT0LPCMPBIAS1

Definition at line 820 of file efr32bg14p_devinfo.h .

#define _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS1_SHIFT 16

Shift value for 1V2LPATT0LPCMPBIAS1

Definition at line 819 of file efr32bg14p_devinfo.h .

#define _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS0_MASK 0xFF00UL

Bit mask for 1V8LPATT0LPCMPBIAS0

Definition at line 818 of file efr32bg14p_devinfo.h .

#define _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS0_SHIFT 8

Shift value for 1V8LPATT0LPCMPBIAS0

Definition at line 817 of file efr32bg14p_devinfo.h .

#define _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS1_MASK 0xFF000000UL

Bit mask for 1V8LPATT0LPCMPBIAS1

Definition at line 822 of file efr32bg14p_devinfo.h .

#define _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS1_SHIFT 24

Shift value for 1V8LPATT0LPCMPBIAS1

Definition at line 821 of file efr32bg14p_devinfo.h .

#define _DEVINFO_DCDCLPVCTRL0_MASK 0xFFFFFFFFUL

Mask for DEVINFO_DCDCLPVCTRL0

Definition at line 814 of file efr32bg14p_devinfo.h .

#define _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS2_MASK 0xFFUL

Bit mask for 1V2LPATT0LPCMPBIAS2

Definition at line 827 of file efr32bg14p_devinfo.h .

#define _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS2_SHIFT 0

Shift value for 1V2LPATT0LPCMPBIAS2

Definition at line 826 of file efr32bg14p_devinfo.h .

#define _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS3_MASK 0xFF0000UL

Bit mask for 1V2LPATT0LPCMPBIAS3

Definition at line 831 of file efr32bg14p_devinfo.h .

#define _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS3_SHIFT 16

Shift value for 1V2LPATT0LPCMPBIAS3

Definition at line 830 of file efr32bg14p_devinfo.h .

#define _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS2_MASK 0xFF00UL

Bit mask for 1V8LPATT0LPCMPBIAS2

Definition at line 829 of file efr32bg14p_devinfo.h .

#define _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS2_SHIFT 8

Shift value for 1V8LPATT0LPCMPBIAS2

Definition at line 828 of file efr32bg14p_devinfo.h .

#define _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS3_MASK 0xFF000000UL

Bit mask for 1V8LPATT0LPCMPBIAS3

Definition at line 833 of file efr32bg14p_devinfo.h .

#define _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS3_SHIFT 24

Shift value for 1V8LPATT0LPCMPBIAS3

Definition at line 832 of file efr32bg14p_devinfo.h .

#define _DEVINFO_DCDCLPVCTRL1_MASK 0xFFFFFFFFUL

Mask for DEVINFO_DCDCLPVCTRL1

Definition at line 825 of file efr32bg14p_devinfo.h .

#define _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS0_MASK 0xFFUL

Bit mask for 1V8LPATT1LPCMPBIAS0

Definition at line 838 of file efr32bg14p_devinfo.h .

#define _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS0_SHIFT 0

Shift value for 1V8LPATT1LPCMPBIAS0

Definition at line 837 of file efr32bg14p_devinfo.h .

#define _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS1_MASK 0xFF0000UL

Bit mask for 1V8LPATT1LPCMPBIAS1

Definition at line 842 of file efr32bg14p_devinfo.h .

#define _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS1_SHIFT 16

Shift value for 1V8LPATT1LPCMPBIAS1

Definition at line 841 of file efr32bg14p_devinfo.h .

#define _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS0_MASK 0xFF00UL

Bit mask for 3V0LPATT1LPCMPBIAS0

Definition at line 840 of file efr32bg14p_devinfo.h .

#define _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS0_SHIFT 8

Shift value for 3V0LPATT1LPCMPBIAS0

Definition at line 839 of file efr32bg14p_devinfo.h .

#define _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS1_MASK 0xFF000000UL

Bit mask for 3V0LPATT1LPCMPBIAS1

Definition at line 844 of file efr32bg14p_devinfo.h .

#define _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS1_SHIFT 24

Shift value for 3V0LPATT1LPCMPBIAS1

Definition at line 843 of file efr32bg14p_devinfo.h .

#define _DEVINFO_DCDCLPVCTRL2_MASK 0xFFFFFFFFUL

Mask for DEVINFO_DCDCLPVCTRL2

Definition at line 836 of file efr32bg14p_devinfo.h .

#define _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS2_MASK 0xFFUL

Bit mask for 1V8LPATT1LPCMPBIAS2

Definition at line 849 of file efr32bg14p_devinfo.h .

#define _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS2_SHIFT 0

Shift value for 1V8LPATT1LPCMPBIAS2

Definition at line 848 of file efr32bg14p_devinfo.h .

#define _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS3_MASK 0xFF0000UL

Bit mask for 1V8LPATT1LPCMPBIAS3

Definition at line 853 of file efr32bg14p_devinfo.h .

#define _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS3_SHIFT 16

Shift value for 1V8LPATT1LPCMPBIAS3

Definition at line 852 of file efr32bg14p_devinfo.h .

#define _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS2_MASK 0xFF00UL

Bit mask for 3V0LPATT1LPCMPBIAS2

Definition at line 851 of file efr32bg14p_devinfo.h .

#define _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS2_SHIFT 8

Shift value for 3V0LPATT1LPCMPBIAS2

Definition at line 850 of file efr32bg14p_devinfo.h .

#define _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS3_MASK 0xFF000000UL

Bit mask for 3V0LPATT1LPCMPBIAS3

Definition at line 855 of file efr32bg14p_devinfo.h .

#define _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS3_SHIFT 24

Shift value for 3V0LPATT1LPCMPBIAS3

Definition at line 854 of file efr32bg14p_devinfo.h .

#define _DEVINFO_DCDCLPVCTRL3_MASK 0xFFFFFFFFUL

Mask for DEVINFO_DCDCLPVCTRL3

Definition at line 847 of file efr32bg14p_devinfo.h .

#define _DEVINFO_DEVINFOREV_DEVINFOREV_MASK 0xFFUL

Bit mask for DEVINFOREV

Definition at line 370 of file efr32bg14p_devinfo.h .

Referenced by SYSTEM_GetDevinfoRev() .

#define _DEVINFO_DEVINFOREV_DEVINFOREV_SHIFT 0

Shift value for DEVINFOREV

Definition at line 369 of file efr32bg14p_devinfo.h .

Referenced by SYSTEM_GetDevinfoRev() .

#define _DEVINFO_DEVINFOREV_MASK 0x000000FFUL

Mask for DEVINFO_DEVINFOREV

Definition at line 368 of file efr32bg14p_devinfo.h .

#define _DEVINFO_EMUTEMP_EMUTEMPROOM_MASK 0xFFUL

Bit mask for EMUTEMPROOM

Definition at line 375 of file efr32bg14p_devinfo.h .

Referenced by calibration() .

#define _DEVINFO_EMUTEMP_EMUTEMPROOM_SHIFT 0

Shift value for EMUTEMPROOM

Definition at line 374 of file efr32bg14p_devinfo.h .

Referenced by calibration() .

#define _DEVINFO_EMUTEMP_MASK 0x000000FFUL

Mask for DEVINFO_EMUTEMP

Definition at line 373 of file efr32bg14p_devinfo.h .

#define _DEVINFO_EUI48H_MASK 0x0000FFFFUL

Mask for DEVINFO_EUI48H

Definition at line 181 of file efr32bg14p_devinfo.h .

#define _DEVINFO_EUI48H_OUI48H_MASK 0xFFFFUL

Bit mask for OUI48H

Definition at line 183 of file efr32bg14p_devinfo.h .

#define _DEVINFO_EUI48H_OUI48H_SHIFT 0

Shift value for OUI48H

Definition at line 182 of file efr32bg14p_devinfo.h .

#define _DEVINFO_EUI48L_MASK 0xFFFFFFFFUL

Mask for DEVINFO_EUI48L

Definition at line 174 of file efr32bg14p_devinfo.h .

#define _DEVINFO_EUI48L_OUI48L_MASK 0xFF000000UL

Bit mask for OUI48L

Definition at line 178 of file efr32bg14p_devinfo.h .

#define _DEVINFO_EUI48L_OUI48L_SHIFT 24

Shift value for OUI48L

Definition at line 177 of file efr32bg14p_devinfo.h .

#define _DEVINFO_EUI48L_UNIQUEID_MASK 0xFFFFFFUL

Bit mask for UNIQUEID

Definition at line 176 of file efr32bg14p_devinfo.h .

#define _DEVINFO_EUI48L_UNIQUEID_SHIFT 0

Shift value for UNIQUEID

Definition at line 175 of file efr32bg14p_devinfo.h .

#define _DEVINFO_EXTINFO_CONNECTION_MASK 0xFF00UL

Bit mask for CONNECTION

Definition at line 161 of file efr32bg14p_devinfo.h .

#define _DEVINFO_EXTINFO_CONNECTION_NONE 0x000000FFUL

Mode NONE for DEVINFO_EXTINFO

Definition at line 163 of file efr32bg14p_devinfo.h .

#define _DEVINFO_EXTINFO_CONNECTION_SHIFT 8

Shift value for CONNECTION

Definition at line 160 of file efr32bg14p_devinfo.h .

#define _DEVINFO_EXTINFO_CONNECTION_SPI 0x00000001UL

Mode SPI for DEVINFO_EXTINFO

Definition at line 162 of file efr32bg14p_devinfo.h .

#define _DEVINFO_EXTINFO_MASK 0x00FFFFFFUL

Mask for DEVINFO_EXTINFO

Definition at line 151 of file efr32bg14p_devinfo.h .

#define _DEVINFO_EXTINFO_REV_MASK 0xFF0000UL

Bit mask for REV

Definition at line 167 of file efr32bg14p_devinfo.h .

#define _DEVINFO_EXTINFO_REV_NONE 0x000000FFUL

Mode NONE for DEVINFO_EXTINFO

Definition at line 169 of file efr32bg14p_devinfo.h .

#define _DEVINFO_EXTINFO_REV_REV1 0x00000001UL

Mode REV1 for DEVINFO_EXTINFO

Definition at line 168 of file efr32bg14p_devinfo.h .

#define _DEVINFO_EXTINFO_REV_SHIFT 16

Shift value for REV

Definition at line 166 of file efr32bg14p_devinfo.h .

#define _DEVINFO_EXTINFO_TYPE_AT25S041 0x00000002UL

Mode AT25S041 for DEVINFO_EXTINFO

Definition at line 155 of file efr32bg14p_devinfo.h .

#define _DEVINFO_EXTINFO_TYPE_IS25LQ040B 0x00000001UL

Mode IS25LQ040B for DEVINFO_EXTINFO

Definition at line 154 of file efr32bg14p_devinfo.h .

#define _DEVINFO_EXTINFO_TYPE_MASK 0xFFUL

Bit mask for TYPE

Definition at line 153 of file efr32bg14p_devinfo.h .

#define _DEVINFO_EXTINFO_TYPE_NONE 0x000000FFUL

Mode NONE for DEVINFO_EXTINFO

Definition at line 156 of file efr32bg14p_devinfo.h .

#define _DEVINFO_EXTINFO_TYPE_SHIFT 0

Shift value for TYPE

Definition at line 152 of file efr32bg14p_devinfo.h .

#define _DEVINFO_HFRCOCAL0_CLKDIV_MASK 0x6000000UL

Bit mask for CLKDIV

Definition at line 432 of file efr32bg14p_devinfo.h .

#define _DEVINFO_HFRCOCAL0_CLKDIV_SHIFT 25

Shift value for CLKDIV

Definition at line 431 of file efr32bg14p_devinfo.h .

#define _DEVINFO_HFRCOCAL0_CMPBIAS_MASK 0xE00000UL

Bit mask for CMPBIAS

Definition at line 428 of file efr32bg14p_devinfo.h .

#define _DEVINFO_HFRCOCAL0_CMPBIAS_SHIFT 21

Shift value for CMPBIAS

Definition at line 427 of file efr32bg14p_devinfo.h .

#define _DEVINFO_HFRCOCAL0_FINETUNING_MASK 0x3F00UL

Bit mask for FINETUNING

Definition at line 424 of file efr32bg14p_devinfo.h .

#define _DEVINFO_HFRCOCAL0_FINETUNING_SHIFT 8

Shift value for FINETUNING

Definition at line 423 of file efr32bg14p_devinfo.h .

#define _DEVINFO_HFRCOCAL0_FINETUNINGEN_MASK 0x8000000UL

Bit mask for FINETUNINGEN

Definition at line 434 of file efr32bg14p_devinfo.h .

#define _DEVINFO_HFRCOCAL0_FINETUNINGEN_SHIFT 27

Shift value for FINETUNINGEN

Definition at line 433 of file efr32bg14p_devinfo.h .

#define _DEVINFO_HFRCOCAL0_FREQRANGE_MASK 0x1F0000UL

Bit mask for FREQRANGE

Definition at line 426 of file efr32bg14p_devinfo.h .

#define _DEVINFO_HFRCOCAL0_FREQRANGE_SHIFT 16

Shift value for FREQRANGE

Definition at line 425 of file efr32bg14p_devinfo.h .

#define _DEVINFO_HFRCOCAL0_LDOHP_MASK 0x1000000UL

Bit mask for LDOHP

Definition at line 430 of file efr32bg14p_devinfo.h .

#define _DEVINFO_HFRCOCAL0_LDOHP_SHIFT 24

Shift value for LDOHP

Definition at line 429 of file efr32bg14p_devinfo.h .

#define _DEVINFO_HFRCOCAL0_MASK 0xFFFF3F7FUL

Mask for DEVINFO_HFRCOCAL0

Definition at line 420 of file efr32bg14p_devinfo.h .

#define _DEVINFO_HFRCOCAL0_TUNING_MASK 0x7FUL

Bit mask for TUNING

Definition at line 422 of file efr32bg14p_devinfo.h .

#define _DEVINFO_HFRCOCAL0_TUNING_SHIFT 0

Shift value for TUNING

Definition at line 421 of file efr32bg14p_devinfo.h .

#define _DEVINFO_HFRCOCAL0_VREFTC_MASK 0xF0000000UL

Bit mask for VREFTC

Definition at line 436 of file efr32bg14p_devinfo.h .

#define _DEVINFO_HFRCOCAL0_VREFTC_SHIFT 28

Shift value for VREFTC

Definition at line 435 of file efr32bg14p_devinfo.h .

#define _DEVINFO_HFRCOCAL10_CLKDIV_MASK 0x6000000UL

Bit mask for CLKDIV

Definition at line 527 of file efr32bg14p_devinfo.h .

#define _DEVINFO_HFRCOCAL10_CLKDIV_SHIFT 25

Shift value for CLKDIV

Definition at line 526 of file efr32bg14p_devinfo.h .

#define _DEVINFO_HFRCOCAL10_CMPBIAS_MASK 0xE00000UL

Bit mask for CMPBIAS

Definition at line 523 of file efr32bg14p_devinfo.h .

#define _DEVINFO_HFRCOCAL10_CMPBIAS_SHIFT 21

Shift value for CMPBIAS

Definition at line 522 of file efr32bg14p_devinfo.h .

#define _DEVINFO_HFRCOCAL10_FINETUNING_MASK 0x3F00UL

Bit mask for FINETUNING

Definition at line 519 of file efr32bg14p_devinfo.h .

#define _DEVINFO_HFRCOCAL10_FINETUNING_SHIFT 8

Shift value for FINETUNING

Definition at line 518 of file efr32bg14p_devinfo.h .

#define _DEVINFO_HFRCOCAL10_FINETUNINGEN_MASK 0x8000000UL

Bit mask for FINETUNINGEN

Definition at line 529 of file efr32bg14p_devinfo.h .

#define _DEVINFO_HFRCOCAL10_FINETUNINGEN_SHIFT 27

Shift value for FINETUNINGEN

Definition at line 528 of file efr32bg14p_devinfo.h .

#define _DEVINFO_HFRCOCAL10_FREQRANGE_MASK 0x1F0000UL

Bit mask for FREQRANGE

Definition at line 521 of file efr32bg14p_devinfo.h .

#define _DEVINFO_HFRCOCAL10_FREQRANGE_SHIFT 16

Shift value for FREQRANGE

Definition at line 520 of file efr32bg14p_devinfo.h .

#define _DEVINFO_HFRCOCAL10_LDOHP_MASK 0x1000000UL

Bit mask for LDOHP

Definition at line 525 of file efr32bg14p_devinfo.h .

#define _DEVINFO_HFRCOCAL10_LDOHP_SHIFT 24

Shift value for LDOHP

Definition at line 524 of file efr32bg14p_devinfo.h .

#define _DEVINFO_HFRCOCAL10_MASK 0xFFFF3F7FUL

Mask for DEVINFO_HFRCOCAL10

Definition at line 515 of file efr32bg14p_devinfo.h .

#define _DEVINFO_HFRCOCAL10_TUNING_MASK 0x7FUL

Bit mask for TUNING

Definition at line 517 of file efr32bg14p_devinfo.h .

#define _DEVINFO_HFRCOCAL10_TUNING_SHIFT 0

Shift value for TUNING

Definition at line 516 of file efr32bg14p_devinfo.h .

#define _DEVINFO_HFRCOCAL10_VREFTC_MASK 0xF0000000UL

Bit mask for VREFTC

Definition at line 531 of file efr32bg14p_devinfo.h .

#define _DEVINFO_HFRCOCAL10_VREFTC_SHIFT 28

Shift value for VREFTC

Definition at line 530 of file efr32bg14p_devinfo.h .

#define _DEVINFO_HFRCOCAL11_CLKDIV_MASK 0x6000000UL

Bit mask for CLKDIV

Definition at line 546 of file efr32bg14p_devinfo.h .

#define _DEVINFO_HFRCOCAL11_CLKDIV_SHIFT 25

Shift value for CLKDIV

Definition at line 545 of file efr32bg14p_devinfo.h .

#define _DEVINFO_HFRCOCAL11_CMPBIAS_MASK 0xE00000UL

Bit mask for CMPBIAS

Definition at line 542 of file efr32bg14p_devinfo.h .

#define _DEVINFO_HFRCOCAL11_CMPBIAS_SHIFT 21

Shift value for CMPBIAS

Definition at line 541 of file efr32bg14p_devinfo.h .

#define _DEVINFO_HFRCOCAL11_FINETUNING_MASK 0x3F00UL

Bit mask for FINETUNING

Definition at line 538 of file efr32bg14p_devinfo.h .

#define _DEVINFO_HFRCOCAL11_FINETUNING_SHIFT 8

Shift value for FINETUNING

Definition at line 537 of file efr32bg14p_devinfo.h .

#define _DEVINFO_HFRCOCAL11_FINETUNINGEN_MASK 0x8000000UL

Bit mask for FINETUNINGEN

Definition at line 548 of file efr32bg14p_devinfo.h .

#define _DEVINFO_HFRCOCAL11_FINETUNINGEN_SHIFT 27

Shift value for FINETUNINGEN

Definition at line 547 of file efr32bg14p_devinfo.h .

#define _DEVINFO_HFRCOCAL11_FREQRANGE_MASK 0x1F0000UL

Bit mask for FREQRANGE

Definition at line 540 of file efr32bg14p_devinfo.h .

#define _DEVINFO_HFRCOCAL11_FREQRANGE_SHIFT 16

Shift value for FREQRANGE

Definition at line 539 of file efr32bg14p_devinfo.h .

#define _DEVINFO_HFRCOCAL11_LDOHP_MASK 0x1000000UL

Bit mask for LDOHP

Definition at line 544 of file efr32bg14p_devinfo.h .

#define _DEVINFO_HFRCOCAL11_LDOHP_SHIFT 24

Shift value for LDOHP

Definition at line 543 of file efr32bg14p_devinfo.h .

#define _DEVINFO_HFRCOCAL11_MASK 0xFFFF3F7FUL

Mask for DEVINFO_HFRCOCAL11

Definition at line 534 of file efr32bg14p_devinfo.h .

#define _DEVINFO_HFRCOCAL11_TUNING_MASK 0x7FUL

Bit mask for TUNING

Definition at line 536 of file efr32bg14p_devinfo.h .

#define _DEVINFO_HFRCOCAL11_TUNING_SHIFT 0

Shift value for TUNING

Definition at line 535 of file efr32bg14p_devinfo.h .

#define _DEVINFO_HFRCOCAL11_VREFTC_MASK 0xF0000000UL

Bit mask for VREFTC

Definition at line 550 of file efr32bg14p_devinfo.h .

#define _DEVINFO_HFRCOCAL11_VREFTC_SHIFT 28

Shift value for VREFTC

Definition at line 549 of file efr32bg14p_devinfo.h .

#define _DEVINFO_HFRCOCAL12_CLKDIV_MASK 0x6000000UL

Bit mask for CLKDIV

Definition at line 565 of file efr32bg14p_devinfo.h .

#define _DEVINFO_HFRCOCAL12_CLKDIV_SHIFT 25

Shift value for CLKDIV

Definition at line 564 of file efr32bg14p_devinfo.h .

#define _DEVINFO_HFRCOCAL12_CMPBIAS_MASK 0xE00000UL

Bit mask for CMPBIAS

Definition at line 561 of file efr32bg14p_devinfo.h .

#define _DEVINFO_HFRCOCAL12_CMPBIAS_SHIFT 21

Shift value for CMPBIAS

Definition at line 560 of file efr32bg14p_devinfo.h .

#define _DEVINFO_HFRCOCAL12_FINETUNING_MASK 0x3F00UL

Bit mask for FINETUNING

Definition at line 557 of file efr32bg14p_devinfo.h .

#define _DEVINFO_HFRCOCAL12_FINETUNING_SHIFT 8

Shift value for FINETUNING

Definition at line 556 of file efr32bg14p_devinfo.h .

#define _DEVINFO_HFRCOCAL12_FINETUNINGEN_MASK 0x8000000UL

Bit mask for FINETUNINGEN

Definition at line 567 of file efr32bg14p_devinfo.h .

#define _DEVINFO_HFRCOCAL12_FINETUNINGEN_SHIFT 27

Shift value for FINETUNINGEN

Definition at line 566 of file efr32bg14p_devinfo.h .

#define _DEVINFO_HFRCOCAL12_FREQRANGE_MASK 0x1F0000UL

Bit mask for FREQRANGE

Definition at line 559 of file efr32bg14p_devinfo.h .

#define _DEVINFO_HFRCOCAL12_FREQRANGE_SHIFT 16

Shift value for FREQRANGE

Definition at line 558 of file efr32bg14p_devinfo.h .

#define _DEVINFO_HFRCOCAL12_LDOHP_MASK 0x1000000UL

Bit mask for LDOHP

Definition at line 563 of file efr32bg14p_devinfo.h .

#define _DEVINFO_HFRCOCAL12_LDOHP_SHIFT 24

Shift value for LDOHP

Definition at line 562 of file efr32bg14p_devinfo.h .

#define _DEVINFO_HFRCOCAL12_MASK 0xFFFF3F7FUL

Mask for DEVINFO_HFRCOCAL12

Definition at line 553 of file efr32bg14p_devinfo.h .

#define _DEVINFO_HFRCOCAL12_TUNING_MASK 0x7FUL

Bit mask for TUNING

Definition at line 555 of file efr32bg14p_devinfo.h .

#define _DEVINFO_HFRCOCAL12_TUNING_SHIFT 0

Shift value for TUNING

Definition at line 554 of file efr32bg14p_devinfo.h .

#define _DEVINFO_HFRCOCAL12_VREFTC_MASK 0xF0000000UL

Bit mask for VREFTC

Definition at line 569 of file efr32bg14p_devinfo.h .

#define _DEVINFO_HFRCOCAL12_VREFTC_SHIFT 28

Shift value for VREFTC

Definition at line 568 of file efr32bg14p_devinfo.h .

#define _DEVINFO_HFRCOCAL3_CLKDIV_MASK 0x6000000UL

Bit mask for CLKDIV

Definition at line 451 of file efr32bg14p_devinfo.h .

#define _DEVINFO_HFRCOCAL3_CLKDIV_SHIFT 25

Shift value for CLKDIV

Definition at line 450 of file efr32bg14p_devinfo.h .

#define _DEVINFO_HFRCOCAL3_CMPBIAS_MASK 0xE00000UL

Bit mask for CMPBIAS

Definition at line 447 of file efr32bg14p_devinfo.h .

#define _DEVINFO_HFRCOCAL3_CMPBIAS_SHIFT 21

Shift value for CMPBIAS

Definition at line 446 of file efr32bg14p_devinfo.h .

#define _DEVINFO_HFRCOCAL3_FINETUNING_MASK 0x3F00UL

Bit mask for FINETUNING

Definition at line 443 of file efr32bg14p_devinfo.h .

#define _DEVINFO_HFRCOCAL3_FINETUNING_SHIFT 8

Shift value for FINETUNING

Definition at line 442 of file efr32bg14p_devinfo.h .

#define _DEVINFO_HFRCOCAL3_FINETUNINGEN_MASK 0x8000000UL

Bit mask for FINETUNINGEN

Definition at line 453 of file efr32bg14p_devinfo.h .

#define _DEVINFO_HFRCOCAL3_FINETUNINGEN_SHIFT 27

Shift value for FINETUNINGEN

Definition at line 452 of file efr32bg14p_devinfo.h .

#define _DEVINFO_HFRCOCAL3_FREQRANGE_MASK 0x1F0000UL

Bit mask for FREQRANGE

Definition at line 445 of file efr32bg14p_devinfo.h .

#define _DEVINFO_HFRCOCAL3_FREQRANGE_SHIFT 16

Shift value for FREQRANGE

Definition at line 444 of file efr32bg14p_devinfo.h .

#define _DEVINFO_HFRCOCAL3_LDOHP_MASK 0x1000000UL

Bit mask for LDOHP

Definition at line 449 of file efr32bg14p_devinfo.h .

#define _DEVINFO_HFRCOCAL3_LDOHP_SHIFT 24

Shift value for LDOHP

Definition at line 448 of file efr32bg14p_devinfo.h .

#define _DEVINFO_HFRCOCAL3_MASK 0xFFFF3F7FUL

Mask for DEVINFO_HFRCOCAL3

Definition at line 439 of file efr32bg14p_devinfo.h .

#define _DEVINFO_HFRCOCAL3_TUNING_MASK 0x7FUL

Bit mask for TUNING

Definition at line 441 of file efr32bg14p_devinfo.h .

#define _DEVINFO_HFRCOCAL3_TUNING_SHIFT 0

Shift value for TUNING

Definition at line 440 of file efr32bg14p_devinfo.h .

#define _DEVINFO_HFRCOCAL3_VREFTC_MASK 0xF0000000UL

Bit mask for VREFTC

Definition at line 455 of file efr32bg14p_devinfo.h .

#define _DEVINFO_HFRCOCAL3_VREFTC_SHIFT 28

Shift value for VREFTC

Definition at line 454 of file efr32bg14p_devinfo.h .

#define _DEVINFO_HFRCOCAL6_CLKDIV_MASK 0x6000000UL

Bit mask for CLKDIV

Definition at line 470 of file efr32bg14p_devinfo.h .

#define _DEVINFO_HFRCOCAL6_CLKDIV_SHIFT 25

Shift value for CLKDIV

Definition at line 469 of file efr32bg14p_devinfo.h .

#define _DEVINFO_HFRCOCAL6_CMPBIAS_MASK 0xE00000UL

Bit mask for CMPBIAS

Definition at line 466 of file efr32bg14p_devinfo.h .

#define _DEVINFO_HFRCOCAL6_CMPBIAS_SHIFT 21

Shift value for CMPBIAS

Definition at line 465 of file efr32bg14p_devinfo.h .

#define _DEVINFO_HFRCOCAL6_FINETUNING_MASK 0x3F00UL

Bit mask for FINETUNING

Definition at line 462 of file efr32bg14p_devinfo.h .

#define _DEVINFO_HFRCOCAL6_FINETUNING_SHIFT 8

Shift value for FINETUNING

Definition at line 461 of file efr32bg14p_devinfo.h .

#define _DEVINFO_HFRCOCAL6_FINETUNINGEN_MASK 0x8000000UL

Bit mask for FINETUNINGEN

Definition at line 472 of file efr32bg14p_devinfo.h .

#define _DEVINFO_HFRCOCAL6_FINETUNINGEN_SHIFT 27

Shift value for FINETUNINGEN

Definition at line 471 of file efr32bg14p_devinfo.h .

#define _DEVINFO_HFRCOCAL6_FREQRANGE_MASK 0x1F0000UL

Bit mask for FREQRANGE

Definition at line 464 of file efr32bg14p_devinfo.h .

#define _DEVINFO_HFRCOCAL6_FREQRANGE_SHIFT 16

Shift value for FREQRANGE

Definition at line 463 of file efr32bg14p_devinfo.h .

#define _DEVINFO_HFRCOCAL6_LDOHP_MASK 0x1000000UL

Bit mask for LDOHP

Definition at line 468 of file efr32bg14p_devinfo.h .

#define _DEVINFO_HFRCOCAL6_LDOHP_SHIFT 24

Shift value for LDOHP

Definition at line 467 of file efr32bg14p_devinfo.h .

#define _DEVINFO_HFRCOCAL6_MASK 0xFFFF3F7FUL

Mask for DEVINFO_HFRCOCAL6

Definition at line 458 of file efr32bg14p_devinfo.h .

#define _DEVINFO_HFRCOCAL6_TUNING_MASK 0x7FUL

Bit mask for TUNING

Definition at line 460 of file efr32bg14p_devinfo.h .

#define _DEVINFO_HFRCOCAL6_TUNING_SHIFT 0

Shift value for TUNING

Definition at line 459 of file efr32bg14p_devinfo.h .

#define _DEVINFO_HFRCOCAL6_VREFTC_MASK 0xF0000000UL

Bit mask for VREFTC

Definition at line 474 of file efr32bg14p_devinfo.h .

#define _DEVINFO_HFRCOCAL6_VREFTC_SHIFT 28

Shift value for VREFTC

Definition at line 473 of file efr32bg14p_devinfo.h .

#define _DEVINFO_HFRCOCAL7_CLKDIV_MASK 0x6000000UL

Bit mask for CLKDIV

Definition at line 489 of file efr32bg14p_devinfo.h .

#define _DEVINFO_HFRCOCAL7_CLKDIV_SHIFT 25

Shift value for CLKDIV

Definition at line 488 of file efr32bg14p_devinfo.h .

#define _DEVINFO_HFRCOCAL7_CMPBIAS_MASK 0xE00000UL

Bit mask for CMPBIAS

Definition at line 485 of file efr32bg14p_devinfo.h .

#define _DEVINFO_HFRCOCAL7_CMPBIAS_SHIFT 21

Shift value for CMPBIAS

Definition at line 484 of file efr32bg14p_devinfo.h .

#define _DEVINFO_HFRCOCAL7_FINETUNING_MASK 0x3F00UL

Bit mask for FINETUNING

Definition at line 481 of file efr32bg14p_devinfo.h .

#define _DEVINFO_HFRCOCAL7_FINETUNING_SHIFT 8

Shift value for FINETUNING

Definition at line 480 of file efr32bg14p_devinfo.h .

#define _DEVINFO_HFRCOCAL7_FINETUNINGEN_MASK 0x8000000UL

Bit mask for FINETUNINGEN

Definition at line 491 of file efr32bg14p_devinfo.h .

#define _DEVINFO_HFRCOCAL7_FINETUNINGEN_SHIFT 27

Shift value for FINETUNINGEN

Definition at line 490 of file efr32bg14p_devinfo.h .

#define _DEVINFO_HFRCOCAL7_FREQRANGE_MASK 0x1F0000UL

Bit mask for FREQRANGE

Definition at line 483 of file efr32bg14p_devinfo.h .

#define _DEVINFO_HFRCOCAL7_FREQRANGE_SHIFT 16

Shift value for FREQRANGE

Definition at line 482 of file efr32bg14p_devinfo.h .

#define _DEVINFO_HFRCOCAL7_LDOHP_MASK 0x1000000UL

Bit mask for LDOHP

Definition at line 487 of file efr32bg14p_devinfo.h .

#define _DEVINFO_HFRCOCAL7_LDOHP_SHIFT 24

Shift value for LDOHP

Definition at line 486 of file efr32bg14p_devinfo.h .

#define _DEVINFO_HFRCOCAL7_MASK 0xFFFF3F7FUL

Mask for DEVINFO_HFRCOCAL7

Definition at line 477 of file efr32bg14p_devinfo.h .

#define _DEVINFO_HFRCOCAL7_TUNING_MASK 0x7FUL

Bit mask for TUNING

Definition at line 479 of file efr32bg14p_devinfo.h .

#define _DEVINFO_HFRCOCAL7_TUNING_SHIFT 0

Shift value for TUNING

Definition at line 478 of file efr32bg14p_devinfo.h .

#define _DEVINFO_HFRCOCAL7_VREFTC_MASK 0xF0000000UL

Bit mask for VREFTC

Definition at line 493 of file efr32bg14p_devinfo.h .

#define _DEVINFO_HFRCOCAL7_VREFTC_SHIFT 28

Shift value for VREFTC

Definition at line 492 of file efr32bg14p_devinfo.h .

#define _DEVINFO_HFRCOCAL8_CLKDIV_MASK 0x6000000UL

Bit mask for CLKDIV

Definition at line 508 of file efr32bg14p_devinfo.h .

#define _DEVINFO_HFRCOCAL8_CLKDIV_SHIFT 25

Shift value for CLKDIV

Definition at line 507 of file efr32bg14p_devinfo.h .

#define _DEVINFO_HFRCOCAL8_CMPBIAS_MASK 0xE00000UL

Bit mask for CMPBIAS

Definition at line 504 of file efr32bg14p_devinfo.h .

#define _DEVINFO_HFRCOCAL8_CMPBIAS_SHIFT 21

Shift value for CMPBIAS

Definition at line 503 of file efr32bg14p_devinfo.h .

#define _DEVINFO_HFRCOCAL8_FINETUNING_MASK 0x3F00UL

Bit mask for FINETUNING

Definition at line 500 of file efr32bg14p_devinfo.h .

#define _DEVINFO_HFRCOCAL8_FINETUNING_SHIFT 8

Shift value for FINETUNING

Definition at line 499 of file efr32bg14p_devinfo.h .

#define _DEVINFO_HFRCOCAL8_FINETUNINGEN_MASK 0x8000000UL

Bit mask for FINETUNINGEN

Definition at line 510 of file efr32bg14p_devinfo.h .

#define _DEVINFO_HFRCOCAL8_FINETUNINGEN_SHIFT 27

Shift value for FINETUNINGEN

Definition at line 509 of file efr32bg14p_devinfo.h .

#define _DEVINFO_HFRCOCAL8_FREQRANGE_MASK 0x1F0000UL

Bit mask for FREQRANGE

Definition at line 502 of file efr32bg14p_devinfo.h .

#define _DEVINFO_HFRCOCAL8_FREQRANGE_SHIFT 16

Shift value for FREQRANGE

Definition at line 501 of file efr32bg14p_devinfo.h .

#define _DEVINFO_HFRCOCAL8_LDOHP_MASK 0x1000000UL

Bit mask for LDOHP

Definition at line 506 of file efr32bg14p_devinfo.h .

#define _DEVINFO_HFRCOCAL8_LDOHP_SHIFT 24

Shift value for LDOHP

Definition at line 505 of file efr32bg14p_devinfo.h .

#define _DEVINFO_HFRCOCAL8_MASK 0xFFFF3F7FUL

Mask for DEVINFO_HFRCOCAL8

Definition at line 496 of file efr32bg14p_devinfo.h .

#define _DEVINFO_HFRCOCAL8_TUNING_MASK 0x7FUL

Bit mask for TUNING

Definition at line 498 of file efr32bg14p_devinfo.h .

#define _DEVINFO_HFRCOCAL8_TUNING_SHIFT 0

Shift value for TUNING

Definition at line 497 of file efr32bg14p_devinfo.h .

#define _DEVINFO_HFRCOCAL8_VREFTC_MASK 0xF0000000UL

Bit mask for VREFTC

Definition at line 512 of file efr32bg14p_devinfo.h .

#define _DEVINFO_HFRCOCAL8_VREFTC_SHIFT 28

Shift value for VREFTC

Definition at line 511 of file efr32bg14p_devinfo.h .

#define _DEVINFO_IDAC0CAL0_MASK 0xFFFFFFFFUL

Mask for DEVINFO_IDAC0CAL0

Definition at line 781 of file efr32bg14p_devinfo.h .

#define _DEVINFO_IDAC0CAL0_SOURCERANGE0TUNING_MASK 0xFFUL

Bit mask for SOURCERANGE0TUNING

Definition at line 783 of file efr32bg14p_devinfo.h .

Referenced by IDAC_RangeSet() .

#define _DEVINFO_IDAC0CAL0_SOURCERANGE0TUNING_SHIFT 0

Shift value for SOURCERANGE0TUNING

Definition at line 782 of file efr32bg14p_devinfo.h .

Referenced by IDAC_RangeSet() .

#define _DEVINFO_IDAC0CAL0_SOURCERANGE1TUNING_MASK 0xFF00UL

Bit mask for SOURCERANGE1TUNING

Definition at line 785 of file efr32bg14p_devinfo.h .

Referenced by IDAC_RangeSet() .

#define _DEVINFO_IDAC0CAL0_SOURCERANGE1TUNING_SHIFT 8

Shift value for SOURCERANGE1TUNING

Definition at line 784 of file efr32bg14p_devinfo.h .

Referenced by IDAC_RangeSet() .

#define _DEVINFO_IDAC0CAL0_SOURCERANGE2TUNING_MASK 0xFF0000UL

Bit mask for SOURCERANGE2TUNING

Definition at line 787 of file efr32bg14p_devinfo.h .

Referenced by IDAC_RangeSet() .

#define _DEVINFO_IDAC0CAL0_SOURCERANGE2TUNING_SHIFT 16

Shift value for SOURCERANGE2TUNING

Definition at line 786 of file efr32bg14p_devinfo.h .

Referenced by IDAC_RangeSet() .

#define _DEVINFO_IDAC0CAL0_SOURCERANGE3TUNING_MASK 0xFF000000UL

Bit mask for SOURCERANGE3TUNING

Definition at line 789 of file efr32bg14p_devinfo.h .

Referenced by IDAC_RangeSet() .

#define _DEVINFO_IDAC0CAL0_SOURCERANGE3TUNING_SHIFT 24

Shift value for SOURCERANGE3TUNING

Definition at line 788 of file efr32bg14p_devinfo.h .

Referenced by IDAC_RangeSet() .

#define _DEVINFO_IDAC0CAL1_MASK 0xFFFFFFFFUL

Mask for DEVINFO_IDAC0CAL1

Definition at line 792 of file efr32bg14p_devinfo.h .

#define _DEVINFO_IDAC0CAL1_SINKRANGE0TUNING_MASK 0xFFUL

Bit mask for SINKRANGE0TUNING

Definition at line 794 of file efr32bg14p_devinfo.h .

Referenced by IDAC_RangeSet() .

#define _DEVINFO_IDAC0CAL1_SINKRANGE0TUNING_SHIFT 0

Shift value for SINKRANGE0TUNING

Definition at line 793 of file efr32bg14p_devinfo.h .

Referenced by IDAC_RangeSet() .

#define _DEVINFO_IDAC0CAL1_SINKRANGE1TUNING_MASK 0xFF00UL

Bit mask for SINKRANGE1TUNING

Definition at line 796 of file efr32bg14p_devinfo.h .

Referenced by IDAC_RangeSet() .

#define _DEVINFO_IDAC0CAL1_SINKRANGE1TUNING_SHIFT 8

Shift value for SINKRANGE1TUNING

Definition at line 795 of file efr32bg14p_devinfo.h .

Referenced by IDAC_RangeSet() .

#define _DEVINFO_IDAC0CAL1_SINKRANGE2TUNING_MASK 0xFF0000UL

Bit mask for SINKRANGE2TUNING

Definition at line 798 of file efr32bg14p_devinfo.h .

Referenced by IDAC_RangeSet() .

#define _DEVINFO_IDAC0CAL1_SINKRANGE2TUNING_SHIFT 16

Shift value for SINKRANGE2TUNING

Definition at line 797 of file efr32bg14p_devinfo.h .

Referenced by IDAC_RangeSet() .

#define _DEVINFO_IDAC0CAL1_SINKRANGE3TUNING_MASK 0xFF000000UL

Bit mask for SINKRANGE3TUNING

Definition at line 800 of file efr32bg14p_devinfo.h .

Referenced by IDAC_RangeSet() .

#define _DEVINFO_IDAC0CAL1_SINKRANGE3TUNING_SHIFT 24

Shift value for SINKRANGE3TUNING

Definition at line 799 of file efr32bg14p_devinfo.h .

Referenced by IDAC_RangeSet() .

#define _DEVINFO_MEMINFO_FLASH_PAGE_SIZE_MASK 0xFF000000UL

Bit mask for FLASH_PAGE_SIZE

Definition at line 215 of file efr32bg14p_devinfo.h .

Referenced by SYSTEM_GetFlashPageSize() .

#define _DEVINFO_MEMINFO_FLASH_PAGE_SIZE_SHIFT 24

Shift value for FLASH_PAGE_SIZE

Definition at line 214 of file efr32bg14p_devinfo.h .

Referenced by SYSTEM_GetFlashPageSize() .

#define _DEVINFO_MEMINFO_MASK 0xFFFFFFFFUL

Mask for DEVINFO_MEMINFO

Definition at line 191 of file efr32bg14p_devinfo.h .

#define _DEVINFO_MEMINFO_PINCOUNT_MASK 0xFF0000UL

Bit mask for PINCOUNT

Definition at line 213 of file efr32bg14p_devinfo.h .

#define _DEVINFO_MEMINFO_PINCOUNT_SHIFT 16

Shift value for PINCOUNT

Definition at line 212 of file efr32bg14p_devinfo.h .

#define _DEVINFO_MEMINFO_PKGTYPE_BGA 0x0000004CUL

Mode BGA for DEVINFO_MEMINFO

Definition at line 205 of file efr32bg14p_devinfo.h .

#define _DEVINFO_MEMINFO_PKGTYPE_MASK 0xFF00UL

Bit mask for PKGTYPE

Definition at line 203 of file efr32bg14p_devinfo.h .

#define _DEVINFO_MEMINFO_PKGTYPE_QFN 0x0000004DUL

Mode QFN for DEVINFO_MEMINFO

Definition at line 206 of file efr32bg14p_devinfo.h .

#define _DEVINFO_MEMINFO_PKGTYPE_QFP 0x00000051UL

Mode QFP for DEVINFO_MEMINFO

Definition at line 207 of file efr32bg14p_devinfo.h .

#define _DEVINFO_MEMINFO_PKGTYPE_SHIFT 8

Shift value for PKGTYPE

Definition at line 202 of file efr32bg14p_devinfo.h .

#define _DEVINFO_MEMINFO_PKGTYPE_WLCSP 0x0000004AUL

Mode WLCSP for DEVINFO_MEMINFO

Definition at line 204 of file efr32bg14p_devinfo.h .

#define _DEVINFO_MEMINFO_TEMPGRADE_MASK 0xFFUL

Bit mask for TEMPGRADE

Definition at line 193 of file efr32bg14p_devinfo.h .

#define _DEVINFO_MEMINFO_TEMPGRADE_N0TO70 0x00000003UL

Mode N0TO70 for DEVINFO_MEMINFO

Definition at line 197 of file efr32bg14p_devinfo.h .

#define _DEVINFO_MEMINFO_TEMPGRADE_N40TO105 0x00000002UL

Mode N40TO105 for DEVINFO_MEMINFO

Definition at line 196 of file efr32bg14p_devinfo.h .

#define _DEVINFO_MEMINFO_TEMPGRADE_N40TO125 0x00000001UL

Mode N40TO125 for DEVINFO_MEMINFO

Definition at line 195 of file efr32bg14p_devinfo.h .

#define _DEVINFO_MEMINFO_TEMPGRADE_N40TO85 0x00000000UL

Mode N40TO85 for DEVINFO_MEMINFO

Definition at line 194 of file efr32bg14p_devinfo.h .

#define _DEVINFO_MEMINFO_TEMPGRADE_SHIFT 0

Shift value for TEMPGRADE

Definition at line 192 of file efr32bg14p_devinfo.h .

#define _DEVINFO_MODULEINFO_MASK 0xFFFFFFFFUL

Mask for DEVINFO_MODULEINFO

Definition at line 146 of file efr32bg14p_devinfo.h .

#define _DEVINFO_MODULEINFO_RESERVED1_MASK 0xFFFFFFFFUL

Bit mask for RESERVED1

Definition at line 148 of file efr32bg14p_devinfo.h .

#define _DEVINFO_MODULEINFO_RESERVED1_SHIFT 0

Shift value for RESERVED1

Definition at line 147 of file efr32bg14p_devinfo.h .

#define _DEVINFO_MSIZE_FLASH_MASK 0xFFFFUL

Bit mask for FLASH

Definition at line 230 of file efr32bg14p_devinfo.h .

Referenced by SYSTEM_GetFlashSize() , and SYSTEM_GetSRAMSize() .

#define _DEVINFO_MSIZE_FLASH_SHIFT 0

Shift value for FLASH

Definition at line 229 of file efr32bg14p_devinfo.h .

Referenced by SYSTEM_GetFlashSize() , and SYSTEM_GetSRAMSize() .

#define _DEVINFO_MSIZE_MASK 0xFFFFFFFFUL

Mask for DEVINFO_MSIZE

Definition at line 228 of file efr32bg14p_devinfo.h .

#define _DEVINFO_MSIZE_SRAM_MASK 0xFFFF0000UL

Bit mask for SRAM

Definition at line 232 of file efr32bg14p_devinfo.h .

Referenced by SYSTEM_GetFlashSize() , and SYSTEM_GetSRAMSize() .

#define _DEVINFO_MSIZE_SRAM_SHIFT 16

Shift value for SRAM

Definition at line 231 of file efr32bg14p_devinfo.h .

Referenced by SYSTEM_GetFlashSize() , and SYSTEM_GetSRAMSize() .

#define _DEVINFO_OPA0CAL0_CM1_MASK 0xFUL

Bit mask for CM1

Definition at line 913 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA0CAL0_CM1_SHIFT 0

Shift value for CM1

Definition at line 912 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA0CAL0_CM2_MASK 0x1E0UL

Bit mask for CM2

Definition at line 915 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA0CAL0_CM2_SHIFT 5

Shift value for CM2

Definition at line 914 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA0CAL0_CM3_MASK 0xC00UL

Bit mask for CM3

Definition at line 917 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA0CAL0_CM3_SHIFT 10

Shift value for CM3

Definition at line 916 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA0CAL0_GM3_MASK 0x60000UL

Bit mask for GM3

Definition at line 921 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA0CAL0_GM3_SHIFT 17

Shift value for GM3

Definition at line 920 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA0CAL0_GM_MASK 0xE000UL

Bit mask for GM

Definition at line 919 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA0CAL0_GM_SHIFT 13

Shift value for GM

Definition at line 918 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA0CAL0_MASK 0x7DF6EDEFUL

Mask for DEVINFO_OPA0CAL0

Definition at line 911 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA0CAL0_OFFSETN_MASK 0x7C000000UL

Bit mask for OFFSETN

Definition at line 925 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA0CAL0_OFFSETN_SHIFT 26

Shift value for OFFSETN

Definition at line 924 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA0CAL0_OFFSETP_MASK 0x1F00000UL

Bit mask for OFFSETP

Definition at line 923 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA0CAL0_OFFSETP_SHIFT 20

Shift value for OFFSETP

Definition at line 922 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA0CAL1_CM1_MASK 0xFUL

Bit mask for CM1

Definition at line 930 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA0CAL1_CM1_SHIFT 0

Shift value for CM1

Definition at line 929 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA0CAL1_CM2_MASK 0x1E0UL

Bit mask for CM2

Definition at line 932 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA0CAL1_CM2_SHIFT 5

Shift value for CM2

Definition at line 931 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA0CAL1_CM3_MASK 0xC00UL

Bit mask for CM3

Definition at line 934 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA0CAL1_CM3_SHIFT 10

Shift value for CM3

Definition at line 933 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA0CAL1_GM3_MASK 0x60000UL

Bit mask for GM3

Definition at line 938 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA0CAL1_GM3_SHIFT 17

Shift value for GM3

Definition at line 937 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA0CAL1_GM_MASK 0xE000UL

Bit mask for GM

Definition at line 936 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA0CAL1_GM_SHIFT 13

Shift value for GM

Definition at line 935 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA0CAL1_MASK 0x7DF6EDEFUL

Mask for DEVINFO_OPA0CAL1

Definition at line 928 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA0CAL1_OFFSETN_MASK 0x7C000000UL

Bit mask for OFFSETN

Definition at line 942 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA0CAL1_OFFSETN_SHIFT 26

Shift value for OFFSETN

Definition at line 941 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA0CAL1_OFFSETP_MASK 0x1F00000UL

Bit mask for OFFSETP

Definition at line 940 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA0CAL1_OFFSETP_SHIFT 20

Shift value for OFFSETP

Definition at line 939 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA0CAL2_CM1_MASK 0xFUL

Bit mask for CM1

Definition at line 947 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA0CAL2_CM1_SHIFT 0

Shift value for CM1

Definition at line 946 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA0CAL2_CM2_MASK 0x1E0UL

Bit mask for CM2

Definition at line 949 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA0CAL2_CM2_SHIFT 5

Shift value for CM2

Definition at line 948 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA0CAL2_CM3_MASK 0xC00UL

Bit mask for CM3

Definition at line 951 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA0CAL2_CM3_SHIFT 10

Shift value for CM3

Definition at line 950 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA0CAL2_GM3_MASK 0x60000UL

Bit mask for GM3

Definition at line 955 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA0CAL2_GM3_SHIFT 17

Shift value for GM3

Definition at line 954 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA0CAL2_GM_MASK 0xE000UL

Bit mask for GM

Definition at line 953 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA0CAL2_GM_SHIFT 13

Shift value for GM

Definition at line 952 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA0CAL2_MASK 0x7DF6EDEFUL

Mask for DEVINFO_OPA0CAL2

Definition at line 945 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA0CAL2_OFFSETN_MASK 0x7C000000UL

Bit mask for OFFSETN

Definition at line 959 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA0CAL2_OFFSETN_SHIFT 26

Shift value for OFFSETN

Definition at line 958 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA0CAL2_OFFSETP_MASK 0x1F00000UL

Bit mask for OFFSETP

Definition at line 957 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA0CAL2_OFFSETP_SHIFT 20

Shift value for OFFSETP

Definition at line 956 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA0CAL3_CM1_MASK 0xFUL

Bit mask for CM1

Definition at line 964 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA0CAL3_CM1_SHIFT 0

Shift value for CM1

Definition at line 963 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA0CAL3_CM2_MASK 0x1E0UL

Bit mask for CM2

Definition at line 966 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA0CAL3_CM2_SHIFT 5

Shift value for CM2

Definition at line 965 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA0CAL3_CM3_MASK 0xC00UL

Bit mask for CM3

Definition at line 968 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA0CAL3_CM3_SHIFT 10

Shift value for CM3

Definition at line 967 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA0CAL3_GM3_MASK 0x60000UL

Bit mask for GM3

Definition at line 972 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA0CAL3_GM3_SHIFT 17

Shift value for GM3

Definition at line 971 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA0CAL3_GM_MASK 0xE000UL

Bit mask for GM

Definition at line 970 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA0CAL3_GM_SHIFT 13

Shift value for GM

Definition at line 969 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA0CAL3_MASK 0x7DF6EDEFUL

Mask for DEVINFO_OPA0CAL3

Definition at line 962 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA0CAL3_OFFSETN_MASK 0x7C000000UL

Bit mask for OFFSETN

Definition at line 976 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA0CAL3_OFFSETN_SHIFT 26

Shift value for OFFSETN

Definition at line 975 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA0CAL3_OFFSETP_MASK 0x1F00000UL

Bit mask for OFFSETP

Definition at line 974 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA0CAL3_OFFSETP_SHIFT 20

Shift value for OFFSETP

Definition at line 973 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA0CAL4_CM1_MASK 0xFUL

Bit mask for CM1

Definition at line 1049 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA0CAL4_CM1_SHIFT 0

Shift value for CM1

Definition at line 1048 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA0CAL4_CM2_MASK 0x1E0UL

Bit mask for CM2

Definition at line 1051 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA0CAL4_CM2_SHIFT 5

Shift value for CM2

Definition at line 1050 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA0CAL4_CM3_MASK 0xC00UL

Bit mask for CM3

Definition at line 1053 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA0CAL4_CM3_SHIFT 10

Shift value for CM3

Definition at line 1052 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA0CAL4_GM3_MASK 0x60000UL

Bit mask for GM3

Definition at line 1057 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA0CAL4_GM3_SHIFT 17

Shift value for GM3

Definition at line 1056 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA0CAL4_GM_MASK 0xE000UL

Bit mask for GM

Definition at line 1055 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA0CAL4_GM_SHIFT 13

Shift value for GM

Definition at line 1054 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA0CAL4_MASK 0x7DF6EDEFUL

Mask for DEVINFO_OPA0CAL4

Definition at line 1047 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA0CAL4_OFFSETN_MASK 0x7C000000UL

Bit mask for OFFSETN

Definition at line 1061 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA0CAL4_OFFSETN_SHIFT 26

Shift value for OFFSETN

Definition at line 1060 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA0CAL4_OFFSETP_MASK 0x1F00000UL

Bit mask for OFFSETP

Definition at line 1059 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA0CAL4_OFFSETP_SHIFT 20

Shift value for OFFSETP

Definition at line 1058 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA0CAL5_CM1_MASK 0xFUL

Bit mask for CM1

Definition at line 1066 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA0CAL5_CM1_SHIFT 0

Shift value for CM1

Definition at line 1065 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA0CAL5_CM2_MASK 0x1E0UL

Bit mask for CM2

Definition at line 1068 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA0CAL5_CM2_SHIFT 5

Shift value for CM2

Definition at line 1067 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA0CAL5_CM3_MASK 0xC00UL

Bit mask for CM3

Definition at line 1070 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA0CAL5_CM3_SHIFT 10

Shift value for CM3

Definition at line 1069 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA0CAL5_GM3_MASK 0x60000UL

Bit mask for GM3

Definition at line 1074 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA0CAL5_GM3_SHIFT 17

Shift value for GM3

Definition at line 1073 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA0CAL5_GM_MASK 0xE000UL

Bit mask for GM

Definition at line 1072 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA0CAL5_GM_SHIFT 13

Shift value for GM

Definition at line 1071 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA0CAL5_MASK 0x7DF6EDEFUL

Mask for DEVINFO_OPA0CAL5

Definition at line 1064 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA0CAL5_OFFSETN_MASK 0x7C000000UL

Bit mask for OFFSETN

Definition at line 1078 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA0CAL5_OFFSETN_SHIFT 26

Shift value for OFFSETN

Definition at line 1077 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA0CAL5_OFFSETP_MASK 0x1F00000UL

Bit mask for OFFSETP

Definition at line 1076 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA0CAL5_OFFSETP_SHIFT 20

Shift value for OFFSETP

Definition at line 1075 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA0CAL6_CM1_MASK 0xFUL

Bit mask for CM1

Definition at line 1083 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA0CAL6_CM1_SHIFT 0

Shift value for CM1

Definition at line 1082 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA0CAL6_CM2_MASK 0x1E0UL

Bit mask for CM2

Definition at line 1085 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA0CAL6_CM2_SHIFT 5

Shift value for CM2

Definition at line 1084 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA0CAL6_CM3_MASK 0xC00UL

Bit mask for CM3

Definition at line 1087 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA0CAL6_CM3_SHIFT 10

Shift value for CM3

Definition at line 1086 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA0CAL6_GM3_MASK 0x60000UL

Bit mask for GM3

Definition at line 1091 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA0CAL6_GM3_SHIFT 17

Shift value for GM3

Definition at line 1090 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA0CAL6_GM_MASK 0xE000UL

Bit mask for GM

Definition at line 1089 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA0CAL6_GM_SHIFT 13

Shift value for GM

Definition at line 1088 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA0CAL6_MASK 0x7DF6EDEFUL

Mask for DEVINFO_OPA0CAL6

Definition at line 1081 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA0CAL6_OFFSETN_MASK 0x7C000000UL

Bit mask for OFFSETN

Definition at line 1095 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA0CAL6_OFFSETN_SHIFT 26

Shift value for OFFSETN

Definition at line 1094 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA0CAL6_OFFSETP_MASK 0x1F00000UL

Bit mask for OFFSETP

Definition at line 1093 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA0CAL6_OFFSETP_SHIFT 20

Shift value for OFFSETP

Definition at line 1092 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA0CAL7_CM1_MASK 0xFUL

Bit mask for CM1

Definition at line 1100 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA0CAL7_CM1_SHIFT 0

Shift value for CM1

Definition at line 1099 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA0CAL7_CM2_MASK 0x1E0UL

Bit mask for CM2

Definition at line 1102 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA0CAL7_CM2_SHIFT 5

Shift value for CM2

Definition at line 1101 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA0CAL7_CM3_MASK 0xC00UL

Bit mask for CM3

Definition at line 1104 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA0CAL7_CM3_SHIFT 10

Shift value for CM3

Definition at line 1103 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA0CAL7_GM3_MASK 0x60000UL

Bit mask for GM3

Definition at line 1108 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA0CAL7_GM3_SHIFT 17

Shift value for GM3

Definition at line 1107 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA0CAL7_GM_MASK 0xE000UL

Bit mask for GM

Definition at line 1106 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA0CAL7_GM_SHIFT 13

Shift value for GM

Definition at line 1105 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA0CAL7_MASK 0x7DF6EDEFUL

Mask for DEVINFO_OPA0CAL7

Definition at line 1098 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA0CAL7_OFFSETN_MASK 0x7C000000UL

Bit mask for OFFSETN

Definition at line 1112 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA0CAL7_OFFSETN_SHIFT 26

Shift value for OFFSETN

Definition at line 1111 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA0CAL7_OFFSETP_MASK 0x1F00000UL

Bit mask for OFFSETP

Definition at line 1110 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA0CAL7_OFFSETP_SHIFT 20

Shift value for OFFSETP

Definition at line 1109 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA1CAL0_CM1_MASK 0xFUL

Bit mask for CM1

Definition at line 981 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA1CAL0_CM1_SHIFT 0

Shift value for CM1

Definition at line 980 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA1CAL0_CM2_MASK 0x1E0UL

Bit mask for CM2

Definition at line 983 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA1CAL0_CM2_SHIFT 5

Shift value for CM2

Definition at line 982 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA1CAL0_CM3_MASK 0xC00UL

Bit mask for CM3

Definition at line 985 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA1CAL0_CM3_SHIFT 10

Shift value for CM3

Definition at line 984 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA1CAL0_GM3_MASK 0x60000UL

Bit mask for GM3

Definition at line 989 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA1CAL0_GM3_SHIFT 17

Shift value for GM3

Definition at line 988 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA1CAL0_GM_MASK 0xE000UL

Bit mask for GM

Definition at line 987 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA1CAL0_GM_SHIFT 13

Shift value for GM

Definition at line 986 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA1CAL0_MASK 0x7DF6EDEFUL

Mask for DEVINFO_OPA1CAL0

Definition at line 979 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA1CAL0_OFFSETN_MASK 0x7C000000UL

Bit mask for OFFSETN

Definition at line 993 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA1CAL0_OFFSETN_SHIFT 26

Shift value for OFFSETN

Definition at line 992 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA1CAL0_OFFSETP_MASK 0x1F00000UL

Bit mask for OFFSETP

Definition at line 991 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA1CAL0_OFFSETP_SHIFT 20

Shift value for OFFSETP

Definition at line 990 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA1CAL1_CM1_MASK 0xFUL

Bit mask for CM1

Definition at line 998 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA1CAL1_CM1_SHIFT 0

Shift value for CM1

Definition at line 997 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA1CAL1_CM2_MASK 0x1E0UL

Bit mask for CM2

Definition at line 1000 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA1CAL1_CM2_SHIFT 5

Shift value for CM2

Definition at line 999 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA1CAL1_CM3_MASK 0xC00UL

Bit mask for CM3

Definition at line 1002 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA1CAL1_CM3_SHIFT 10

Shift value for CM3

Definition at line 1001 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA1CAL1_GM3_MASK 0x60000UL

Bit mask for GM3

Definition at line 1006 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA1CAL1_GM3_SHIFT 17

Shift value for GM3

Definition at line 1005 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA1CAL1_GM_MASK 0xE000UL

Bit mask for GM

Definition at line 1004 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA1CAL1_GM_SHIFT 13

Shift value for GM

Definition at line 1003 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA1CAL1_MASK 0x7DF6EDEFUL

Mask for DEVINFO_OPA1CAL1

Definition at line 996 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA1CAL1_OFFSETN_MASK 0x7C000000UL

Bit mask for OFFSETN

Definition at line 1010 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA1CAL1_OFFSETN_SHIFT 26

Shift value for OFFSETN

Definition at line 1009 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA1CAL1_OFFSETP_MASK 0x1F00000UL

Bit mask for OFFSETP

Definition at line 1008 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA1CAL1_OFFSETP_SHIFT 20

Shift value for OFFSETP

Definition at line 1007 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA1CAL2_CM1_MASK 0xFUL

Bit mask for CM1

Definition at line 1015 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA1CAL2_CM1_SHIFT 0

Shift value for CM1

Definition at line 1014 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA1CAL2_CM2_MASK 0x1E0UL

Bit mask for CM2

Definition at line 1017 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA1CAL2_CM2_SHIFT 5

Shift value for CM2

Definition at line 1016 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA1CAL2_CM3_MASK 0xC00UL

Bit mask for CM3

Definition at line 1019 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA1CAL2_CM3_SHIFT 10

Shift value for CM3

Definition at line 1018 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA1CAL2_GM3_MASK 0x60000UL

Bit mask for GM3

Definition at line 1023 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA1CAL2_GM3_SHIFT 17

Shift value for GM3

Definition at line 1022 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA1CAL2_GM_MASK 0xE000UL

Bit mask for GM

Definition at line 1021 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA1CAL2_GM_SHIFT 13

Shift value for GM

Definition at line 1020 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA1CAL2_MASK 0x7DF6EDEFUL

Mask for DEVINFO_OPA1CAL2

Definition at line 1013 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA1CAL2_OFFSETN_MASK 0x7C000000UL

Bit mask for OFFSETN

Definition at line 1027 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA1CAL2_OFFSETN_SHIFT 26

Shift value for OFFSETN

Definition at line 1026 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA1CAL2_OFFSETP_MASK 0x1F00000UL

Bit mask for OFFSETP

Definition at line 1025 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA1CAL2_OFFSETP_SHIFT 20

Shift value for OFFSETP

Definition at line 1024 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA1CAL3_CM1_MASK 0xFUL

Bit mask for CM1

Definition at line 1032 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA1CAL3_CM1_SHIFT 0

Shift value for CM1

Definition at line 1031 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA1CAL3_CM2_MASK 0x1E0UL

Bit mask for CM2

Definition at line 1034 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA1CAL3_CM2_SHIFT 5

Shift value for CM2

Definition at line 1033 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA1CAL3_CM3_MASK 0xC00UL

Bit mask for CM3

Definition at line 1036 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA1CAL3_CM3_SHIFT 10

Shift value for CM3

Definition at line 1035 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA1CAL3_GM3_MASK 0x60000UL

Bit mask for GM3

Definition at line 1040 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA1CAL3_GM3_SHIFT 17

Shift value for GM3

Definition at line 1039 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA1CAL3_GM_MASK 0xE000UL

Bit mask for GM

Definition at line 1038 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA1CAL3_GM_SHIFT 13

Shift value for GM

Definition at line 1037 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA1CAL3_MASK 0x7DF6EDEFUL

Mask for DEVINFO_OPA1CAL3

Definition at line 1030 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA1CAL3_OFFSETN_MASK 0x7C000000UL

Bit mask for OFFSETN

Definition at line 1044 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA1CAL3_OFFSETN_SHIFT 26

Shift value for OFFSETN

Definition at line 1043 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA1CAL3_OFFSETP_MASK 0x1F00000UL

Bit mask for OFFSETP

Definition at line 1042 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA1CAL3_OFFSETP_SHIFT 20

Shift value for OFFSETP

Definition at line 1041 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA1CAL4_CM1_MASK 0xFUL

Bit mask for CM1

Definition at line 1117 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA1CAL4_CM1_SHIFT 0

Shift value for CM1

Definition at line 1116 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA1CAL4_CM2_MASK 0x1E0UL

Bit mask for CM2

Definition at line 1119 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA1CAL4_CM2_SHIFT 5

Shift value for CM2

Definition at line 1118 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA1CAL4_CM3_MASK 0xC00UL

Bit mask for CM3

Definition at line 1121 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA1CAL4_CM3_SHIFT 10

Shift value for CM3

Definition at line 1120 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA1CAL4_GM3_MASK 0x60000UL

Bit mask for GM3

Definition at line 1125 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA1CAL4_GM3_SHIFT 17

Shift value for GM3

Definition at line 1124 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA1CAL4_GM_MASK 0xE000UL

Bit mask for GM

Definition at line 1123 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA1CAL4_GM_SHIFT 13

Shift value for GM

Definition at line 1122 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA1CAL4_MASK 0x7DF6EDEFUL

Mask for DEVINFO_OPA1CAL4

Definition at line 1115 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA1CAL4_OFFSETN_MASK 0x7C000000UL

Bit mask for OFFSETN

Definition at line 1129 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA1CAL4_OFFSETN_SHIFT 26

Shift value for OFFSETN

Definition at line 1128 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA1CAL4_OFFSETP_MASK 0x1F00000UL

Bit mask for OFFSETP

Definition at line 1127 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA1CAL4_OFFSETP_SHIFT 20

Shift value for OFFSETP

Definition at line 1126 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA1CAL5_CM1_MASK 0xFUL

Bit mask for CM1

Definition at line 1134 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA1CAL5_CM1_SHIFT 0

Shift value for CM1

Definition at line 1133 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA1CAL5_CM2_MASK 0x1E0UL

Bit mask for CM2

Definition at line 1136 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA1CAL5_CM2_SHIFT 5

Shift value for CM2

Definition at line 1135 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA1CAL5_CM3_MASK 0xC00UL

Bit mask for CM3

Definition at line 1138 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA1CAL5_CM3_SHIFT 10

Shift value for CM3

Definition at line 1137 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA1CAL5_GM3_MASK 0x60000UL

Bit mask for GM3

Definition at line 1142 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA1CAL5_GM3_SHIFT 17

Shift value for GM3

Definition at line 1141 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA1CAL5_GM_MASK 0xE000UL

Bit mask for GM

Definition at line 1140 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA1CAL5_GM_SHIFT 13

Shift value for GM

Definition at line 1139 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA1CAL5_MASK 0x7DF6EDEFUL

Mask for DEVINFO_OPA1CAL5

Definition at line 1132 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA1CAL5_OFFSETN_MASK 0x7C000000UL

Bit mask for OFFSETN

Definition at line 1146 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA1CAL5_OFFSETN_SHIFT 26

Shift value for OFFSETN

Definition at line 1145 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA1CAL5_OFFSETP_MASK 0x1F00000UL

Bit mask for OFFSETP

Definition at line 1144 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA1CAL5_OFFSETP_SHIFT 20

Shift value for OFFSETP

Definition at line 1143 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA1CAL6_CM1_MASK 0xFUL

Bit mask for CM1

Definition at line 1151 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA1CAL6_CM1_SHIFT 0

Shift value for CM1

Definition at line 1150 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA1CAL6_CM2_MASK 0x1E0UL

Bit mask for CM2

Definition at line 1153 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA1CAL6_CM2_SHIFT 5

Shift value for CM2

Definition at line 1152 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA1CAL6_CM3_MASK 0xC00UL

Bit mask for CM3

Definition at line 1155 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA1CAL6_CM3_SHIFT 10

Shift value for CM3

Definition at line 1154 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA1CAL6_GM3_MASK 0x60000UL

Bit mask for GM3

Definition at line 1159 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA1CAL6_GM3_SHIFT 17

Shift value for GM3

Definition at line 1158 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA1CAL6_GM_MASK 0xE000UL

Bit mask for GM

Definition at line 1157 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA1CAL6_GM_SHIFT 13

Shift value for GM

Definition at line 1156 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA1CAL6_MASK 0x7DF6EDEFUL

Mask for DEVINFO_OPA1CAL6

Definition at line 1149 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA1CAL6_OFFSETN_MASK 0x7C000000UL

Bit mask for OFFSETN

Definition at line 1163 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA1CAL6_OFFSETN_SHIFT 26

Shift value for OFFSETN

Definition at line 1162 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA1CAL6_OFFSETP_MASK 0x1F00000UL

Bit mask for OFFSETP

Definition at line 1161 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA1CAL6_OFFSETP_SHIFT 20

Shift value for OFFSETP

Definition at line 1160 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA1CAL7_CM1_MASK 0xFUL

Bit mask for CM1

Definition at line 1168 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA1CAL7_CM1_SHIFT 0

Shift value for CM1

Definition at line 1167 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA1CAL7_CM2_MASK 0x1E0UL

Bit mask for CM2

Definition at line 1170 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA1CAL7_CM2_SHIFT 5

Shift value for CM2

Definition at line 1169 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA1CAL7_CM3_MASK 0xC00UL

Bit mask for CM3

Definition at line 1172 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA1CAL7_CM3_SHIFT 10

Shift value for CM3

Definition at line 1171 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA1CAL7_GM3_MASK 0x60000UL

Bit mask for GM3

Definition at line 1176 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA1CAL7_GM3_SHIFT 17

Shift value for GM3

Definition at line 1175 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA1CAL7_GM_MASK 0xE000UL

Bit mask for GM

Definition at line 1174 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA1CAL7_GM_SHIFT 13

Shift value for GM

Definition at line 1173 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA1CAL7_MASK 0x7DF6EDEFUL

Mask for DEVINFO_OPA1CAL7

Definition at line 1166 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA1CAL7_OFFSETN_MASK 0x7C000000UL

Bit mask for OFFSETN

Definition at line 1180 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA1CAL7_OFFSETN_SHIFT 26

Shift value for OFFSETN

Definition at line 1179 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA1CAL7_OFFSETP_MASK 0x1F00000UL

Bit mask for OFFSETP

Definition at line 1178 of file efr32bg14p_devinfo.h .

#define _DEVINFO_OPA1CAL7_OFFSETP_SHIFT 20

Shift value for OFFSETP

Definition at line 1177 of file efr32bg14p_devinfo.h .

#define _DEVINFO_PART_DEVICE_FAMILY_EFM32G 0x00000047UL

Mode EFM32G for DEVINFO_PART

Definition at line 278 of file efr32bg14p_devinfo.h .

#define _DEVINFO_PART_DEVICE_FAMILY_EFM32GG 0x00000048UL

Mode EFM32GG for DEVINFO_PART

Definition at line 280 of file efr32bg14p_devinfo.h .

#define _DEVINFO_PART_DEVICE_FAMILY_EFM32GG11B 0x00000064UL

Mode EFM32GG11B for DEVINFO_PART

Definition at line 296 of file efr32bg14p_devinfo.h .

#define _DEVINFO_PART_DEVICE_FAMILY_EFM32GG12B 0x0000006AUL

Mode EFM32GG12B for DEVINFO_PART

Definition at line 298 of file efr32bg14p_devinfo.h .

#define _DEVINFO_PART_DEVICE_FAMILY_EFM32HG 0x0000004DUL

Mode EFM32HG for DEVINFO_PART

Definition at line 291 of file efr32bg14p_devinfo.h .

#define _DEVINFO_PART_DEVICE_FAMILY_EFM32JG12B 0x00000057UL

Mode EFM32JG12B for DEVINFO_PART

Definition at line 295 of file efr32bg14p_devinfo.h .

#define _DEVINFO_PART_DEVICE_FAMILY_EFM32JG1B 0x00000053UL

Mode EFM32JG1B for DEVINFO_PART

Definition at line 293 of file efr32bg14p_devinfo.h .

#define _DEVINFO_PART_DEVICE_FAMILY_EFM32LG 0x0000004AUL

Mode EFM32LG for DEVINFO_PART

Definition at line 284 of file efr32bg14p_devinfo.h .

#define _DEVINFO_PART_DEVICE_FAMILY_EFM32PG12B 0x00000055UL

Mode EFM32PG12B for DEVINFO_PART

Definition at line 294 of file efr32bg14p_devinfo.h .

#define _DEVINFO_PART_DEVICE_FAMILY_EFM32PG1B 0x00000051UL

Mode EFM32PG1B for DEVINFO_PART

Definition at line 292 of file efr32bg14p_devinfo.h .

#define _DEVINFO_PART_DEVICE_FAMILY_EFM32TG 0x00000049UL

Mode EFM32TG for DEVINFO_PART

Definition at line 283 of file efr32bg14p_devinfo.h .

#define _DEVINFO_PART_DEVICE_FAMILY_EFM32TG11B 0x00000067UL

Mode EFM32TG11B for DEVINFO_PART

Definition at line 297 of file efr32bg14p_devinfo.h .

#define _DEVINFO_PART_DEVICE_FAMILY_EFM32WG 0x0000004BUL

Mode EFM32WG for DEVINFO_PART

Definition at line 286 of file efr32bg14p_devinfo.h .

#define _DEVINFO_PART_DEVICE_FAMILY_EFM32ZG 0x0000004CUL

Mode EFM32ZG for DEVINFO_PART

Definition at line 289 of file efr32bg14p_devinfo.h .

#define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG12B 0x00000020UL

Mode EFR32BG12B for DEVINFO_PART

Definition at line 253 of file efr32bg14p_devinfo.h .

#define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG12P 0x0000001FUL

Mode EFR32BG12P for DEVINFO_PART

Definition at line 252 of file efr32bg14p_devinfo.h .

#define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG12V 0x00000021UL

Mode EFR32BG12V for DEVINFO_PART

Definition at line 254 of file efr32bg14p_devinfo.h .

#define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG13B 0x0000002CUL

Mode EFR32BG13B for DEVINFO_PART

Definition at line 262 of file efr32bg14p_devinfo.h .

#define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG13P 0x0000002BUL

Mode EFR32BG13P for DEVINFO_PART

Definition at line 261 of file efr32bg14p_devinfo.h .

#define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG13V 0x0000002DUL

Mode EFR32BG13V for DEVINFO_PART

Definition at line 263 of file efr32bg14p_devinfo.h .

#define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG14B 0x00000038UL

Mode EFR32BG14B for DEVINFO_PART

Definition at line 272 of file efr32bg14p_devinfo.h .

#define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG14P 0x00000037UL

Mode EFR32BG14P for DEVINFO_PART

Definition at line 271 of file efr32bg14p_devinfo.h .

#define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG14V 0x00000039UL

Mode EFR32BG14V for DEVINFO_PART

Definition at line 273 of file efr32bg14p_devinfo.h .

#define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG1B 0x00000014UL

Mode EFR32BG1B for DEVINFO_PART

Definition at line 244 of file efr32bg14p_devinfo.h .

#define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG1P 0x00000013UL

Mode EFR32BG1P for DEVINFO_PART

Definition at line 243 of file efr32bg14p_devinfo.h .

#define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG1V 0x00000015UL

Mode EFR32BG1V for DEVINFO_PART

Definition at line 245 of file efr32bg14p_devinfo.h .

#define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG12B 0x00000026UL

Mode EFR32FG12B for DEVINFO_PART

Definition at line 256 of file efr32bg14p_devinfo.h .

#define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG12P 0x00000025UL

Mode EFR32FG12P for DEVINFO_PART

Definition at line 255 of file efr32bg14p_devinfo.h .

#define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG12V 0x00000027UL

Mode EFR32FG12V for DEVINFO_PART

Definition at line 257 of file efr32bg14p_devinfo.h .

#define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG13B 0x00000032UL

Mode EFR32FG13B for DEVINFO_PART

Definition at line 266 of file efr32bg14p_devinfo.h .

#define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG13P 0x00000031UL

Mode EFR32FG13P for DEVINFO_PART

Definition at line 265 of file efr32bg14p_devinfo.h .

#define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG13V 0x00000033UL

Mode EFR32FG13V for DEVINFO_PART

Definition at line 267 of file efr32bg14p_devinfo.h .

#define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG14B 0x0000003EUL

Mode EFR32FG14B for DEVINFO_PART

Definition at line 276 of file efr32bg14p_devinfo.h .

#define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG14P 0x0000003DUL

Mode EFR32FG14P for DEVINFO_PART

Definition at line 275 of file efr32bg14p_devinfo.h .

#define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG14V 0x0000003FUL

Mode EFR32FG14V for DEVINFO_PART

Definition at line 277 of file efr32bg14p_devinfo.h .

#define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG1B 0x0000001AUL

Mode EFR32FG1B for DEVINFO_PART

Definition at line 247 of file efr32bg14p_devinfo.h .

#define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG1P 0x00000019UL

Mode EFR32FG1P for DEVINFO_PART

Definition at line 246 of file efr32bg14p_devinfo.h .

#define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG1V 0x0000001BUL

Mode EFR32FG1V for DEVINFO_PART

Definition at line 248 of file efr32bg14p_devinfo.h .

#define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG12B 0x0000001DUL

Mode EFR32MG12B for DEVINFO_PART

Definition at line 250 of file efr32bg14p_devinfo.h .

#define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG12P 0x0000001CUL

Mode EFR32MG12P for DEVINFO_PART

Definition at line 249 of file efr32bg14p_devinfo.h .

#define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG12V 0x0000001EUL

Mode EFR32MG12V for DEVINFO_PART

Definition at line 251 of file efr32bg14p_devinfo.h .

#define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG13B 0x00000029UL

Mode EFR32MG13B for DEVINFO_PART

Definition at line 259 of file efr32bg14p_devinfo.h .

#define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG13P 0x00000028UL

Mode EFR32MG13P for DEVINFO_PART

Definition at line 258 of file efr32bg14p_devinfo.h .

#define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG13V 0x0000002AUL

Mode EFR32MG13V for DEVINFO_PART

Definition at line 260 of file efr32bg14p_devinfo.h .

#define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG14B 0x00000035UL

Mode EFR32MG14B for DEVINFO_PART

Definition at line 269 of file efr32bg14p_devinfo.h .

#define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG14P 0x00000034UL

Mode EFR32MG14P for DEVINFO_PART

Definition at line 268 of file efr32bg14p_devinfo.h .

#define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG14V 0x00000036UL

Mode EFR32MG14V for DEVINFO_PART

Definition at line 270 of file efr32bg14p_devinfo.h .

#define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG1B 0x00000011UL

Mode EFR32MG1B for DEVINFO_PART

Definition at line 241 of file efr32bg14p_devinfo.h .

#define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG1P 0x00000010UL

Mode EFR32MG1P for DEVINFO_PART

Definition at line 240 of file efr32bg14p_devinfo.h .

#define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG1V 0x00000012UL

Mode EFR32MG1V for DEVINFO_PART

Definition at line 242 of file efr32bg14p_devinfo.h .

#define _DEVINFO_PART_DEVICE_FAMILY_EFR32ZG13P 0x0000002EUL

Mode EFR32ZG13P for DEVINFO_PART

Definition at line 264 of file efr32bg14p_devinfo.h .

#define _DEVINFO_PART_DEVICE_FAMILY_EFR32ZG14P 0x0000003AUL

Mode EFR32ZG14P for DEVINFO_PART

Definition at line 274 of file efr32bg14p_devinfo.h .

#define _DEVINFO_PART_DEVICE_FAMILY_EZR32HG 0x0000007AUL

Mode EZR32HG for DEVINFO_PART

Definition at line 301 of file efr32bg14p_devinfo.h .

#define _DEVINFO_PART_DEVICE_FAMILY_EZR32LG 0x00000078UL

Mode EZR32LG for DEVINFO_PART

Definition at line 299 of file efr32bg14p_devinfo.h .

#define _DEVINFO_PART_DEVICE_FAMILY_EZR32WG 0x00000079UL

Mode EZR32WG for DEVINFO_PART

Definition at line 300 of file efr32bg14p_devinfo.h .

#define _DEVINFO_PART_DEVICE_FAMILY_G 0x00000047UL

Mode G for DEVINFO_PART

Definition at line 279 of file efr32bg14p_devinfo.h .

#define _DEVINFO_PART_DEVICE_FAMILY_GG 0x00000048UL

Mode GG for DEVINFO_PART

Definition at line 281 of file efr32bg14p_devinfo.h .

#define _DEVINFO_PART_DEVICE_FAMILY_HG 0x0000004DUL

Mode HG for DEVINFO_PART

Definition at line 290 of file efr32bg14p_devinfo.h .

#define _DEVINFO_PART_DEVICE_FAMILY_LG 0x0000004AUL

Mode LG for DEVINFO_PART

Definition at line 285 of file efr32bg14p_devinfo.h .

#define _DEVINFO_PART_DEVICE_FAMILY_MASK 0xFF0000UL

Bit mask for DEVICE_FAMILY

Definition at line 239 of file efr32bg14p_devinfo.h .

Referenced by SYSTEM_GetFamily() .

#define _DEVINFO_PART_DEVICE_FAMILY_SHIFT 16

Shift value for DEVICE_FAMILY

Definition at line 238 of file efr32bg14p_devinfo.h .

Referenced by SYSTEM_GetFamily() .

#define _DEVINFO_PART_DEVICE_FAMILY_TG 0x00000049UL

Mode TG for DEVINFO_PART

Definition at line 282 of file efr32bg14p_devinfo.h .

#define _DEVINFO_PART_DEVICE_FAMILY_WG 0x0000004BUL

Mode WG for DEVINFO_PART

Definition at line 287 of file efr32bg14p_devinfo.h .

#define _DEVINFO_PART_DEVICE_FAMILY_ZG 0x0000004CUL

Mode ZG for DEVINFO_PART

Definition at line 288 of file efr32bg14p_devinfo.h .

#define _DEVINFO_PART_DEVICE_NUMBER_MASK 0xFFFFUL

Bit mask for DEVICE_NUMBER

Definition at line 237 of file efr32bg14p_devinfo.h .

Referenced by SYSTEM_GetPartNumber() .

#define _DEVINFO_PART_DEVICE_NUMBER_SHIFT 0

Shift value for DEVICE_NUMBER

Definition at line 236 of file efr32bg14p_devinfo.h .

Referenced by SYSTEM_GetPartNumber() .

#define _DEVINFO_PART_MASK 0xFFFFFFFFUL

Mask for DEVINFO_PART

Definition at line 235 of file efr32bg14p_devinfo.h .

#define _DEVINFO_PART_PROD_REV_MASK 0xFF000000UL

Bit mask for PROD_REV

Definition at line 365 of file efr32bg14p_devinfo.h .

Referenced by SYSTEM_GetProdRev() .

#define _DEVINFO_PART_PROD_REV_SHIFT 24

Shift value for PROD_REV

Definition at line 364 of file efr32bg14p_devinfo.h .

Referenced by SYSTEM_GetProdRev() .

#define _DEVINFO_UNIQUEH_MASK 0xFFFFFFFFUL

Mask for DEVINFO_UNIQUEH

Definition at line 223 of file efr32bg14p_devinfo.h .

#define _DEVINFO_UNIQUEH_UNIQUEH_MASK 0xFFFFFFFFUL

Bit mask for UNIQUEH

Definition at line 225 of file efr32bg14p_devinfo.h .

#define _DEVINFO_UNIQUEH_UNIQUEH_SHIFT 0

Shift value for UNIQUEH

Definition at line 224 of file efr32bg14p_devinfo.h .

#define _DEVINFO_UNIQUEL_MASK 0xFFFFFFFFUL

Mask for DEVINFO_UNIQUEL

Definition at line 218 of file efr32bg14p_devinfo.h .

#define _DEVINFO_UNIQUEL_UNIQUEL_MASK 0xFFFFFFFFUL

Bit mask for UNIQUEL

Definition at line 220 of file efr32bg14p_devinfo.h .

#define _DEVINFO_UNIQUEL_UNIQUEL_SHIFT 0

Shift value for UNIQUEL

Definition at line 219 of file efr32bg14p_devinfo.h .

#define _DEVINFO_VDAC0ALTCAL_GAINERRTRIM1V25ALT_MASK 0x3F000UL

Bit mask for GAINERRTRIM1V25ALT

Definition at line 895 of file efr32bg14p_devinfo.h .

#define _DEVINFO_VDAC0ALTCAL_GAINERRTRIM1V25ALT_SHIFT 12

Shift value for GAINERRTRIM1V25ALT

Definition at line 894 of file efr32bg14p_devinfo.h .

#define _DEVINFO_VDAC0ALTCAL_GAINERRTRIM1V25LNALT_MASK 0x3FUL

Bit mask for GAINERRTRIM1V25LNALT

Definition at line 891 of file efr32bg14p_devinfo.h .

#define _DEVINFO_VDAC0ALTCAL_GAINERRTRIM1V25LNALT_SHIFT 0

Shift value for GAINERRTRIM1V25LNALT

Definition at line 890 of file efr32bg14p_devinfo.h .

#define _DEVINFO_VDAC0ALTCAL_GAINERRTRIM2V5ALT_MASK 0xFC0000UL

Bit mask for GAINERRTRIM2V5ALT

Definition at line 897 of file efr32bg14p_devinfo.h .

#define _DEVINFO_VDAC0ALTCAL_GAINERRTRIM2V5ALT_SHIFT 18

Shift value for GAINERRTRIM2V5ALT

Definition at line 896 of file efr32bg14p_devinfo.h .

#define _DEVINFO_VDAC0ALTCAL_GAINERRTRIM2V5LNALT_MASK 0xFC0UL

Bit mask for GAINERRTRIM2V5LNALT

Definition at line 893 of file efr32bg14p_devinfo.h .

#define _DEVINFO_VDAC0ALTCAL_GAINERRTRIM2V5LNALT_SHIFT 6

Shift value for GAINERRTRIM2V5LNALT

Definition at line 892 of file efr32bg14p_devinfo.h .

#define _DEVINFO_VDAC0ALTCAL_GAINERRTRIMVDDANAEXTPINALT_MASK 0x3F000000UL

Bit mask for GAINERRTRIMVDDANAEXTPINALT

Definition at line 899 of file efr32bg14p_devinfo.h .

#define _DEVINFO_VDAC0ALTCAL_GAINERRTRIMVDDANAEXTPINALT_SHIFT 24

Shift value for GAINERRTRIMVDDANAEXTPINALT

Definition at line 898 of file efr32bg14p_devinfo.h .

#define _DEVINFO_VDAC0ALTCAL_MASK 0x3FFFFFFFUL

Mask for DEVINFO_VDAC0ALTCAL

Definition at line 889 of file efr32bg14p_devinfo.h .

#define _DEVINFO_VDAC0CH1CAL_GAINERRTRIMCH1A_MASK 0xF0UL

Bit mask for GAINERRTRIMCH1A

Definition at line 906 of file efr32bg14p_devinfo.h .

Referenced by VDAC_Init() .

#define _DEVINFO_VDAC0CH1CAL_GAINERRTRIMCH1A_SHIFT 4

Shift value for GAINERRTRIMCH1A

Definition at line 905 of file efr32bg14p_devinfo.h .

Referenced by VDAC_Init() .

#define _DEVINFO_VDAC0CH1CAL_GAINERRTRIMCH1B_MASK 0xF00UL

Bit mask for GAINERRTRIMCH1B

Definition at line 908 of file efr32bg14p_devinfo.h .

Referenced by VDAC_Init() .

#define _DEVINFO_VDAC0CH1CAL_GAINERRTRIMCH1B_SHIFT 8

Shift value for GAINERRTRIMCH1B

Definition at line 907 of file efr32bg14p_devinfo.h .

Referenced by VDAC_Init() .

#define _DEVINFO_VDAC0CH1CAL_MASK 0x00000FF7UL

Mask for DEVINFO_VDAC0CH1CAL

Definition at line 902 of file efr32bg14p_devinfo.h .

#define _DEVINFO_VDAC0CH1CAL_OFFSETTRIM_MASK 0x7UL

Bit mask for OFFSETTRIM

Definition at line 904 of file efr32bg14p_devinfo.h .

Referenced by VDAC_Init() .

#define _DEVINFO_VDAC0CH1CAL_OFFSETTRIM_SHIFT 0

Shift value for OFFSETTRIM

Definition at line 903 of file efr32bg14p_devinfo.h .

Referenced by VDAC_Init() .

#define _DEVINFO_VDAC0MAINCAL_GAINERRTRIM1V25_MASK 0x3F000UL

Bit mask for GAINERRTRIM1V25

Definition at line 882 of file efr32bg14p_devinfo.h .

Referenced by VDAC_Init() .

#define _DEVINFO_VDAC0MAINCAL_GAINERRTRIM1V25_SHIFT 12

Shift value for GAINERRTRIM1V25

Definition at line 881 of file efr32bg14p_devinfo.h .

Referenced by VDAC_Init() .

#define _DEVINFO_VDAC0MAINCAL_GAINERRTRIM1V25LN_MASK 0x3FUL

Bit mask for GAINERRTRIM1V25LN

Definition at line 878 of file efr32bg14p_devinfo.h .

Referenced by VDAC_Init() .

#define _DEVINFO_VDAC0MAINCAL_GAINERRTRIM1V25LN_SHIFT 0

Shift value for GAINERRTRIM1V25LN

Definition at line 877 of file efr32bg14p_devinfo.h .

Referenced by VDAC_Init() .

#define _DEVINFO_VDAC0MAINCAL_GAINERRTRIM2V5_MASK 0xFC0000UL

Bit mask for GAINERRTRIM2V5

Definition at line 884 of file efr32bg14p_devinfo.h .

Referenced by VDAC_Init() .

#define _DEVINFO_VDAC0MAINCAL_GAINERRTRIM2V5_SHIFT 18

Shift value for GAINERRTRIM2V5

Definition at line 883 of file efr32bg14p_devinfo.h .

Referenced by VDAC_Init() .

#define _DEVINFO_VDAC0MAINCAL_GAINERRTRIM2V5LN_MASK 0xFC0UL

Bit mask for GAINERRTRIM2V5LN

Definition at line 880 of file efr32bg14p_devinfo.h .

Referenced by VDAC_Init() .

#define _DEVINFO_VDAC0MAINCAL_GAINERRTRIM2V5LN_SHIFT 6

Shift value for GAINERRTRIM2V5LN

Definition at line 879 of file efr32bg14p_devinfo.h .

Referenced by VDAC_Init() .

#define _DEVINFO_VDAC0MAINCAL_GAINERRTRIMVDDANAEXTPIN_MASK 0x3F000000UL

Bit mask for GAINERRTRIMVDDANAEXTPIN

Definition at line 886 of file efr32bg14p_devinfo.h .

Referenced by VDAC_Init() .

#define _DEVINFO_VDAC0MAINCAL_GAINERRTRIMVDDANAEXTPIN_SHIFT 24

Shift value for GAINERRTRIMVDDANAEXTPIN

Definition at line 885 of file efr32bg14p_devinfo.h .

Referenced by VDAC_Init() .

#define _DEVINFO_VDAC0MAINCAL_MASK 0x3FFFFFFFUL

Mask for DEVINFO_VDAC0MAINCAL

Definition at line 876 of file efr32bg14p_devinfo.h .

#define _DEVINFO_VMONCAL0_ALTAVDD1V86THRESCOARSE_MASK 0xF00000UL

Bit mask for ALTAVDD1V86THRESCOARSE

Definition at line 736 of file efr32bg14p_devinfo.h .

#define _DEVINFO_VMONCAL0_ALTAVDD1V86THRESCOARSE_SHIFT 20

Shift value for ALTAVDD1V86THRESCOARSE

Definition at line 735 of file efr32bg14p_devinfo.h .

#define _DEVINFO_VMONCAL0_ALTAVDD1V86THRESFINE_MASK 0xF0000UL

Bit mask for ALTAVDD1V86THRESFINE

Definition at line 734 of file efr32bg14p_devinfo.h .

#define _DEVINFO_VMONCAL0_ALTAVDD1V86THRESFINE_SHIFT 16

Shift value for ALTAVDD1V86THRESFINE

Definition at line 733 of file efr32bg14p_devinfo.h .

#define _DEVINFO_VMONCAL0_ALTAVDD2V98THRESCOARSE_MASK 0xF0000000UL

Bit mask for ALTAVDD2V98THRESCOARSE

Definition at line 740 of file efr32bg14p_devinfo.h .

#define _DEVINFO_VMONCAL0_ALTAVDD2V98THRESCOARSE_SHIFT 28

Shift value for ALTAVDD2V98THRESCOARSE

Definition at line 739 of file efr32bg14p_devinfo.h .

#define _DEVINFO_VMONCAL0_ALTAVDD2V98THRESFINE_MASK 0xF000000UL

Bit mask for ALTAVDD2V98THRESFINE

Definition at line 738 of file efr32bg14p_devinfo.h .

#define _DEVINFO_VMONCAL0_ALTAVDD2V98THRESFINE_SHIFT 24

Shift value for ALTAVDD2V98THRESFINE

Definition at line 737 of file efr32bg14p_devinfo.h .

#define _DEVINFO_VMONCAL0_AVDD1V86THRESCOARSE_MASK 0xF0UL

Bit mask for AVDD1V86THRESCOARSE

Definition at line 728 of file efr32bg14p_devinfo.h .

#define _DEVINFO_VMONCAL0_AVDD1V86THRESCOARSE_SHIFT 4

Shift value for AVDD1V86THRESCOARSE

Definition at line 727 of file efr32bg14p_devinfo.h .

#define _DEVINFO_VMONCAL0_AVDD1V86THRESFINE_MASK 0xFUL

Bit mask for AVDD1V86THRESFINE

Definition at line 726 of file efr32bg14p_devinfo.h .

#define _DEVINFO_VMONCAL0_AVDD1V86THRESFINE_SHIFT 0

Shift value for AVDD1V86THRESFINE

Definition at line 725 of file efr32bg14p_devinfo.h .

#define _DEVINFO_VMONCAL0_AVDD2V98THRESCOARSE_MASK 0xF000UL

Bit mask for AVDD2V98THRESCOARSE

Definition at line 732 of file efr32bg14p_devinfo.h .

#define _DEVINFO_VMONCAL0_AVDD2V98THRESCOARSE_SHIFT 12

Shift value for AVDD2V98THRESCOARSE

Definition at line 731 of file efr32bg14p_devinfo.h .

#define _DEVINFO_VMONCAL0_AVDD2V98THRESFINE_MASK 0xF00UL

Bit mask for AVDD2V98THRESFINE

Definition at line 730 of file efr32bg14p_devinfo.h .

#define _DEVINFO_VMONCAL0_AVDD2V98THRESFINE_SHIFT 8

Shift value for AVDD2V98THRESFINE

Definition at line 729 of file efr32bg14p_devinfo.h .

#define _DEVINFO_VMONCAL0_MASK 0xFFFFFFFFUL

Mask for DEVINFO_VMONCAL0

Definition at line 724 of file efr32bg14p_devinfo.h .

#define _DEVINFO_VMONCAL1_DVDD1V86THRESCOARSE_MASK 0xF0UL

Bit mask for DVDD1V86THRESCOARSE

Definition at line 747 of file efr32bg14p_devinfo.h .

#define _DEVINFO_VMONCAL1_DVDD1V86THRESCOARSE_SHIFT 4

Shift value for DVDD1V86THRESCOARSE

Definition at line 746 of file efr32bg14p_devinfo.h .

#define _DEVINFO_VMONCAL1_DVDD1V86THRESFINE_MASK 0xFUL

Bit mask for DVDD1V86THRESFINE

Definition at line 745 of file efr32bg14p_devinfo.h .

#define _DEVINFO_VMONCAL1_DVDD1V86THRESFINE_SHIFT 0

Shift value for DVDD1V86THRESFINE

Definition at line 744 of file efr32bg14p_devinfo.h .

#define _DEVINFO_VMONCAL1_DVDD2V98THRESCOARSE_MASK 0xF000UL

Bit mask for DVDD2V98THRESCOARSE

Definition at line 751 of file efr32bg14p_devinfo.h .

#define _DEVINFO_VMONCAL1_DVDD2V98THRESCOARSE_SHIFT 12

Shift value for DVDD2V98THRESCOARSE

Definition at line 750 of file efr32bg14p_devinfo.h .

#define _DEVINFO_VMONCAL1_DVDD2V98THRESFINE_MASK 0xF00UL

Bit mask for DVDD2V98THRESFINE

Definition at line 749 of file efr32bg14p_devinfo.h .

#define _DEVINFO_VMONCAL1_DVDD2V98THRESFINE_SHIFT 8

Shift value for DVDD2V98THRESFINE

Definition at line 748 of file efr32bg14p_devinfo.h .

#define _DEVINFO_VMONCAL1_IO01V86THRESCOARSE_MASK 0xF00000UL

Bit mask for IO01V86THRESCOARSE

Definition at line 755 of file efr32bg14p_devinfo.h .

#define _DEVINFO_VMONCAL1_IO01V86THRESCOARSE_SHIFT 20

Shift value for IO01V86THRESCOARSE

Definition at line 754 of file efr32bg14p_devinfo.h .

#define _DEVINFO_VMONCAL1_IO01V86THRESFINE_MASK 0xF0000UL

Bit mask for IO01V86THRESFINE

Definition at line 753 of file efr32bg14p_devinfo.h .

#define _DEVINFO_VMONCAL1_IO01V86THRESFINE_SHIFT 16

Shift value for IO01V86THRESFINE

Definition at line 752 of file efr32bg14p_devinfo.h .

#define _DEVINFO_VMONCAL1_IO02V98THRESCOARSE_MASK 0xF0000000UL

Bit mask for IO02V98THRESCOARSE

Definition at line 759 of file efr32bg14p_devinfo.h .

#define _DEVINFO_VMONCAL1_IO02V98THRESCOARSE_SHIFT 28

Shift value for IO02V98THRESCOARSE

Definition at line 758 of file efr32bg14p_devinfo.h .

#define _DEVINFO_VMONCAL1_IO02V98THRESFINE_MASK 0xF000000UL

Bit mask for IO02V98THRESFINE

Definition at line 757 of file efr32bg14p_devinfo.h .

#define _DEVINFO_VMONCAL1_IO02V98THRESFINE_SHIFT 24

Shift value for IO02V98THRESFINE

Definition at line 756 of file

DEVINFO Bit FieldsDevices > Device Information and Calibration

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