CMUEMLIB

Detailed Description

Clock management unit (CMU) Peripheral API.

This module contains functions for the CMU peripheral of Silicon Labs 32-bit MCUs and SoCs. The CMU module controls oscillators, clocks gates, clock multiplexers, pre-scalers, calibration modules and wait-states.

Data Structures

struct  CMU_DPLLInit_TypeDef
 
struct  CMU_HFXOInit_TypeDef
 
struct  CMU_LFXOInit_TypeDef
 

Macros

#define CMU_DPLL_HFXO_TO_80MHZ
 
#define CMU_DPLL_LFXO_TO_40MHZ
 
#define CMU_DPLLINIT_DEFAULT
 
#define CMU_HFRCODPLL_MAX   cmuHFRCODPLLFreq_80M0Hz
 
#define CMU_HFRCODPLL_MIN   cmuHFRCODPLLFreq_1M0Hz
 
#define CMU_HFRCOEM23_MAX   cmuHFRCOEM23Freq_40M0Hz
 
#define CMU_HFRCOEM23_MIN   cmuHFRCOEM23Freq_1M0Hz
 
#define CMU_HFXOINIT_DEFAULT
 
#define CMU_HFXOINIT_EXTERNAL_SINE
 
#define CMU_LFXOINIT_DEFAULT
 
#define CMU_LFXOINIT_EXTERNAL_CLOCK
 
#define CMU_LFXOINIT_EXTERNAL_SINE
 

Typedefs

typedef uint32_t CMU_ClkDiv_TypeDef
 

Enumerations

enum  CMU_Clock_TypeDef {
  cmuClock_SYSCLK,
  cmuClock_HCLK,
  cmuClock_EXPCLK,
  cmuClock_PCLK,
  cmuClock_LSPCLK,
  cmuClock_IADCCLK,
  cmuClock_EM01GRPACLK,
  cmuClock_EM23GRPACLK,
  cmuClock_EM4GRPACLK,
  cmuClock_WDOG0CLK,
  cmuClock_WDOG1CLK,
  cmuClock_DPLLREFCLK,
  cmuClock_TRACECLK,
  cmuClock_RTCCCLK,
  cmuClock_CORE,
  cmuClock_SYSTICK,
  cmuClock_ACMP0,
  cmuClock_ACMP1,
  cmuClock_BURTC,
  cmuClock_GPCRC,
  cmuClock_GPIO,
  cmuClock_I2C0,
  cmuClock_I2C1,
  cmuClock_IADC0,
  cmuClock_LDMA,
  cmuClock_LETIMER0,
  cmuClock_PRS,
  cmuClock_RTCC,
  cmuClock_TIMER0,
  cmuClock_TIMER1,
  cmuClock_TIMER2,
  cmuClock_TIMER3,
  cmuClock_USART0,
  cmuClock_USART1,
  cmuClock_USART2,
  cmuClock_WDOG0,
  cmuClock_WDOG1,
  cmuClock_PDM
}
 
enum  CMU_DPLLEdgeSel_TypeDef {
  cmuDPLLEdgeSel_Fall = 0,
  cmuDPLLEdgeSel_Rise = 1
}
 
enum  CMU_DPLLLockMode_TypeDef {
  cmuDPLLLockMode_Freq = _DPLL_CFG_MODE_FLL,
  cmuDPLLLockMode_Phase = _DPLL_CFG_MODE_PLL
}
 
enum  CMU_HFRCODPLLFreq_TypeDef {
  cmuHFRCODPLLFreq_1M0Hz = 1000000U,
  cmuHFRCODPLLFreq_2M0Hz = 2000000U,
  cmuHFRCODPLLFreq_4M0Hz = 4000000U,
  cmuHFRCODPLLFreq_7M0Hz = 7000000U,
  cmuHFRCODPLLFreq_13M0Hz = 13000000U,
  cmuHFRCODPLLFreq_16M0Hz = 16000000U,
  cmuHFRCODPLLFreq_19M0Hz = 19000000U,
  cmuHFRCODPLLFreq_26M0Hz = 26000000U,
  cmuHFRCODPLLFreq_32M0Hz = 32000000U,
  cmuHFRCODPLLFreq_38M0Hz = 38000000U,
  cmuHFRCODPLLFreq_48M0Hz = 48000000U,
  cmuHFRCODPLLFreq_56M0Hz = 56000000U,
  cmuHFRCODPLLFreq_64M0Hz = 64000000U,
  cmuHFRCODPLLFreq_80M0Hz = 80000000U,
  cmuHFRCODPLLFreq_UserDefined = 0
}
 
enum  CMU_HFRCOEM23Freq_TypeDef {
  cmuHFRCOEM23Freq_1M0Hz = 1000000U,
  cmuHFRCOEM23Freq_2M0Hz = 2000000U,
  cmuHFRCOEM23Freq_4M0Hz = 4000000U,
  cmuHFRCOEM23Freq_13M0Hz = 13000000U,
  cmuHFRCOEM23Freq_16M0Hz = 16000000U,
  cmuHFRCOEM23Freq_19M0Hz = 19000000U,
  cmuHFRCOEM23Freq_26M0Hz = 26000000U,
  cmuHFRCOEM23Freq_32M0Hz = 32000000U,
  cmuHFRCOEM23Freq_40M0Hz = 40000000U,
  cmuHFRCOEM23Freq_UserDefined = 0
}
 
enum  CMU_HfxoCbLsbTimeout_TypeDef {
  cmuHfxoCbLsbTimeout_8us = _HFXO_XTALCFG_TIMEOUTCBLSB_T8US,
  cmuHfxoCbLsbTimeout_20us = _HFXO_XTALCFG_TIMEOUTCBLSB_T20US,
  cmuHfxoCbLsbTimeout_41us = _HFXO_XTALCFG_TIMEOUTCBLSB_T41US,
  cmuHfxoCbLsbTimeout_62us = _HFXO_XTALCFG_TIMEOUTCBLSB_T62US,
  cmuHfxoCbLsbTimeout_83us = _HFXO_XTALCFG_TIMEOUTCBLSB_T83US,
  cmuHfxoCbLsbTimeout_104us = _HFXO_XTALCFG_TIMEOUTCBLSB_T104US,
  cmuHfxoCbLsbTimeout_125us = _HFXO_XTALCFG_TIMEOUTCBLSB_T125US,
  cmuHfxoCbLsbTimeout_166us = _HFXO_XTALCFG_TIMEOUTCBLSB_T166US,
  cmuHfxoCbLsbTimeout_208us = _HFXO_XTALCFG_TIMEOUTCBLSB_T208US,
  cmuHfxoCbLsbTimeout_250us = _HFXO_XTALCFG_TIMEOUTCBLSB_T250US,
  cmuHfxoCbLsbTimeout_333us = _HFXO_XTALCFG_TIMEOUTCBLSB_T333US,
  cmuHfxoCbLsbTimeout_416us = _HFXO_XTALCFG_TIMEOUTCBLSB_T416US,
  cmuHfxoCbLsbTimeout_833us = _HFXO_XTALCFG_TIMEOUTCBLSB_T833US,
  cmuHfxoCbLsbTimeout_1250us = _HFXO_XTALCFG_TIMEOUTCBLSB_T1250US,
  cmuHfxoCbLsbTimeout_2083us = _HFXO_XTALCFG_TIMEOUTCBLSB_T2083US,
  cmuHfxoCbLsbTimeout_3750us = _HFXO_XTALCFG_TIMEOUTCBLSB_T3750US
}
 
enum  CMU_HfxoCoreDegen_TypeDef {
  cmuHfxoCoreDegen_None = _HFXO_XTALCTRL_COREDGENANA_NONE,
  cmuHfxoCoreDegen_33 = _HFXO_XTALCTRL_COREDGENANA_DGEN33,
  cmuHfxoCoreDegen_50 = _HFXO_XTALCTRL_COREDGENANA_DGEN50,
  cmuHfxoCoreDegen_100 = _HFXO_XTALCTRL_COREDGENANA_DGEN100
}
 
enum  CMU_HfxoCtuneFixCap_TypeDef {
  cmuHfxoCtuneFixCap_None = _HFXO_XTALCTRL_CTUNEFIXANA_NONE,
  cmuHfxoCtuneFixCap_Xi = _HFXO_XTALCTRL_CTUNEFIXANA_XI,
  cmuHfxoCtuneFixCap_Xo = _HFXO_XTALCTRL_CTUNEFIXANA_XO,
  cmuHfxoCtuneFixCap_Both = _HFXO_XTALCTRL_CTUNEFIXANA_BOTH
}
 
enum  CMU_HfxoOscMode_TypeDef {
  cmuHfxoOscMode_Crystal = _HFXO_CFG_MODE_XTAL,
  cmuHfxoOscMode_ExternalSine = _HFXO_CFG_MODE_EXTCLK
}
 
enum  CMU_HfxoSteadyStateTimeout_TypeDef {
  cmuHfxoSteadyStateTimeout_16us = _HFXO_XTALCFG_TIMEOUTSTEADY_T16US,
  cmuHfxoSteadyStateTimeout_41us = _HFXO_XTALCFG_TIMEOUTSTEADY_T41US,
  cmuHfxoSteadyStateTimeout_83us = _HFXO_XTALCFG_TIMEOUTSTEADY_T83US,
  cmuHfxoSteadyStateTimeout_125us = _HFXO_XTALCFG_TIMEOUTSTEADY_T125US,
  cmuHfxoSteadyStateTimeout_166us = _HFXO_XTALCFG_TIMEOUTSTEADY_T166US,
  cmuHfxoSteadyStateTimeout_208us = _HFXO_XTALCFG_TIMEOUTSTEADY_T208US,
  cmuHfxoSteadyStateTimeout_250us = _HFXO_XTALCFG_TIMEOUTSTEADY_T250US,
  cmuHfxoSteadyStateTimeout_333us = _HFXO_XTALCFG_TIMEOUTSTEADY_T333US,
  cmuHfxoSteadyStateTimeout_416us = _HFXO_XTALCFG_TIMEOUTSTEADY_T416US,
  cmuHfxoSteadyStateTimeout_500us = _HFXO_XTALCFG_TIMEOUTSTEADY_T500US,
  cmuHfxoSteadyStateTimeout_666us = _HFXO_XTALCFG_TIMEOUTSTEADY_T666US,
  cmuHfxoSteadyStateTimeout_833us = _HFXO_XTALCFG_TIMEOUTSTEADY_T833US,
  cmuHfxoSteadyStateTimeout_1666us = _HFXO_XTALCFG_TIMEOUTSTEADY_T1666US,
  cmuHfxoSteadyStateTimeout_2500us = _HFXO_XTALCFG_TIMEOUTSTEADY_T2500US,
  cmuHfxoSteadyStateTimeout_4166us = _HFXO_XTALCFG_TIMEOUTSTEADY_T4166US,
  cmuHfxoSteadyStateTimeout_7500us = _HFXO_XTALCFG_TIMEOUTSTEADY_T7500US
}
 
enum  CMU_LfxoOscMode_TypeDef {
  cmuLfxoOscMode_Crystal = _LFXO_CFG_MODE_XTAL,
  cmuLfxoOscMode_AcCoupledSine = _LFXO_CFG_MODE_BUFEXTCLK,
  cmuLfxoOscMode_External = _LFXO_CFG_MODE_DIGEXTCLK
}
 
enum  CMU_LfxoStartupDelay_TypeDef {
  cmuLfxoStartupDelay_2Cycles = _LFXO_CFG_TIMEOUT_CYCLES2,
  cmuLfxoStartupDelay_256Cycles = _LFXO_CFG_TIMEOUT_CYCLES256,
  cmuLfxoStartupDelay_1KCycles = _LFXO_CFG_TIMEOUT_CYCLES1K,
  cmuLfxoStartupDelay_2KCycles = _LFXO_CFG_TIMEOUT_CYCLES2K,
  cmuLfxoStartupDelay_4KCycles = _LFXO_CFG_TIMEOUT_CYCLES4K,
  cmuLfxoStartupDelay_8KCycles = _LFXO_CFG_TIMEOUT_CYCLES8K,
  cmuLfxoStartupDelay_16KCycles = _LFXO_CFG_TIMEOUT_CYCLES16K,
  cmuLfxoStartupDelay_32KCycles = _LFXO_CFG_TIMEOUT_CYCLES32K
}
 
enum  CMU_Osc_TypeDef {
  cmuOsc_LFXO,
  cmuOsc_LFRCO,
  cmuOsc_FSRCO,
  cmuOsc_HFXO,
  cmuOsc_HFRCODPLL,
  cmuOsc_HFRCOEM23,
  cmuOsc_ULFRCO
}
 
enum  CMU_Precision_TypeDef {
  cmuPrecisionDefault,
  cmuPrecisionHigh
}
 
enum  CMU_Select_TypeDef {
  cmuSelect_Error,
  cmuSelect_Disabled,
  cmuSelect_FSRCO,
  cmuSelect_HFXO,
  cmuSelect_HFRCODPLL,
  cmuSelect_HFRCOEM23,
  cmuSelect_CLKIN0,
  cmuSelect_LFXO,
  cmuSelect_LFRCO,
  cmuSelect_ULFRCO,
  cmuSelect_PCLK,
  cmuSelect_HCLK,
  cmuSelect_HCLKDIV1024,
  cmuSelect_EM01GRPACLK,
  cmuSelect_EXPCLK,
  cmuSelect_PRS
}
 

Functions

uint32_t CMU_Calibrate (uint32_t cycles, CMU_Select_TypeDef ref)
 Calibrate an oscillator.
 
void CMU_CalibrateConfig (uint32_t downCycles, CMU_Select_TypeDef downSel, CMU_Select_TypeDef upSel)
 Configure clock calibration.
 
__STATIC_INLINE void CMU_CalibrateCont (bool enable)
 Configures continuous calibration mode.
 
uint32_t CMU_CalibrateCountGet (void)
 Get calibration count value.
 
__STATIC_INLINE void CMU_CalibrateStart (void)
 Starts calibration.
 
__STATIC_INLINE void CMU_CalibrateStop (void)
 Stop calibration counters.
 
void CMU_ClkOutPinConfig (uint32_t clkNo, CMU_Select_TypeDef sel, CMU_ClkDiv_TypeDef clkDiv, GPIO_Port_TypeDef port, unsigned int pin)
 Direct a clock to a GPIO pin.
 
CMU_ClkDiv_TypeDef CMU_ClockDivGet (CMU_Clock_TypeDef clock)
 Get clock divisor.
 
void CMU_ClockDivSet (CMU_Clock_TypeDef clock, CMU_ClkDiv_TypeDef div)
 Set clock divisor.
 
__STATIC_INLINE void CMU_ClockEnable (CMU_Clock_TypeDef clock, bool enable)
 Enable/disable a clock.
 
uint32_t CMU_ClockFreqGet (CMU_Clock_TypeDef clock)
 Get clock frequency for a clock point.
 
CMU_Select_TypeDef CMU_ClockSelectGet (CMU_Clock_TypeDef clock)
 Get currently selected reference clock used for a clock branch.
 
void CMU_ClockSelectSet (CMU_Clock_TypeDef clock, CMU_Select_TypeDef ref)
 Select reference clock/oscillator used for a clock branch.
 
bool CMU_DPLLLock (const CMU_DPLLInit_TypeDef *init)
 Lock the DPLL to a given frequency. The frequency is given by: Fout = Fref * (N+1) / (M+1).
 
__STATIC_INLINE void CMU_DPLLUnlock (void)
 Unlock the DPLL.
 
CMU_HFRCODPLLFreq_TypeDef CMU_HFRCODPLLBandGet (void)
 Get HFRCODPLL band in use.
 
void CMU_HFRCODPLLBandSet (CMU_HFRCODPLLFreq_TypeDef freq)
 Set HFRCODPLL band and the tuning value based on the value in the calibration table made during production.
 
CMU_HFRCOEM23Freq_TypeDef CMU_HFRCOEM23BandGet (void)
 Get HFRCOEM23 band in use.
 
void CMU_HFRCOEM23BandSet (CMU_HFRCOEM23Freq_TypeDef freq)
 Set HFRCOEM23 band and the tuning value based on the value in the calibration table made during production.
 
void CMU_HFXOInit (const CMU_HFXOInit_TypeDef *hfxoInit)
 Initialize all HFXO control registers.
 
__STATIC_INLINE void CMU_IntClear (uint32_t flags)
 Clear one or more pending CMU interrupt flags.
 
__STATIC_INLINE void CMU_IntDisable (uint32_t flags)
 Disable one or more CMU interrupt sources.
 
__STATIC_INLINE void CMU_IntEnable (uint32_t flags)
 Enable one or more CMU interrupt sources.
 
__STATIC_INLINE uint32_t CMU_IntGet (void)
 Get pending CMU interrupt sources.
 
__STATIC_INLINE uint32_t CMU_IntGetEnabled (void)
 Get enabled and pending CMU interrupt flags.
 
__STATIC_INLINE void CMU_IntSet (uint32_t flags)
 Set one or more pending CMU interrupt sources.
 
void CMU_LFRCOSetPrecision (CMU_Precision_TypeDef precision)
 Configure the LFRCO precision.
 
void CMU_LFXOInit (const CMU_LFXOInit_TypeDef *lfxoInit)
 Initialize LFXO control registers.
 
__STATIC_INLINE void CMU_Lock (void)
 Lock CMU register access in order to protect registers contents against unintended modification.
 
__STATIC_INLINE void CMU_OscillatorEnable (CMU_Osc_TypeDef osc, bool enable, bool wait)
 Enable/disable oscillator.
 
uint32_t CMU_OscillatorTuningGet (CMU_Osc_TypeDef osc)
 Get oscillator frequency tuning setting.
 
void CMU_OscillatorTuningSet (CMU_Osc_TypeDef osc, uint32_t val)
 Set the oscillator frequency tuning control.
 
__STATIC_INLINE uint32_t CMU_PrescToLog2 (uint32_t presc)
 Convert prescaler dividend to a logarithmic value. It only works for even numbers equal to 2^n.
 
__STATIC_INLINE void CMU_Unlock (void)
 Unlock CMU register access so that writing to registers is possible.
 
void CMU_UpdateWaitStates (uint32_t freq, int vscale)
 Configure wait state settings necessary to switch to a given core clock frequency at a certain voltage scale level.
 
__STATIC_INLINE void CMU_WdogLock (void)
 Lock WDOG register access in order to protect registers contents against unintended modification.
 
__STATIC_INLINE void CMU_WdogUnlock (void)
 Unlock WDOG register access so that writing to registers is possible.
 
static void dpllRefClkGet (uint32_t *freq, CMU_Select_TypeDef *sel)
 Get selected oscillator and frequency for cmuClock_DPLLREFCLK clock tree.
 
static void em01GrpaClkGet (uint32_t *freq, CMU_Select_TypeDef *sel)
 Get selected oscillator and frequency for cmuClock_EM01GRPACLK clock tree.
 
static void em23GrpaClkGet (uint32_t *freq, CMU_Select_TypeDef *sel)
 Get selected oscillator and frequency for cmuClock_EM23GRPACLK clock tree.
 
static void em4GrpaClkGet (uint32_t *freq, CMU_Select_TypeDef *sel)
 Get selected oscillator and frequency for cmuClock_EM4GRPACLK clock tree.
 
static void flashWaitStateControl (uint32_t coreFreq, int vscale)
 Configure flash access wait states to support the given core clock frequency and vscale level.
 
static uint32_t HFRCODPLLDevinfoGet (CMU_HFRCODPLLFreq_TypeDef freq)
 Get calibrated HFRCODPLL tuning value from Device information (DI) page for a given frequency. Calibration value is not available for all frequency bands.
 
static void iadcClkGet (uint32_t *freq, CMU_Select_TypeDef *sel)
 Get selected oscillator and frequency for cmuClock_IADCCLK clock tree.
 
static void pclkDivMax (void)
 Set maximum allowed divisor for cmuClock_PCLK clock tree.
 
static void pclkDivOptimize (void)
 Set cmuClock_PCLK clock tree divisor to achieve highest possible frequency and still be within spec.
 
static void rtccClkGet (uint32_t *freq, CMU_Select_TypeDef *sel)
 Get selected oscillator and frequency for cmuClock_RTCCCLK clock tree.
 
static void waitStateMax (void)
 Set wait-states to values valid for maximum allowable core clock frequency.
 
static void wdog0ClkGet (uint32_t *freq, CMU_Select_TypeDef *sel)
 Get selected oscillator and frequency for cmuClock_WDOG0CLK clock tree.
 

Macro Definition Documentation

#define CMU_DPLL_HFXO_TO_80MHZ
Value:
{ \
80000000, /* Target frequency. */ \
(4000 - 1), /* Factor N. */ \
(1920 - 1), /* Factor M. */ \
cmuSelect_HFXO, /* Select HFXO as reference clock. */ \
cmuDPLLEdgeSel_Fall, /* Select falling edge of ref clock. */ \
cmuDPLLLockMode_Freq, /* Use frequency lock mode. */ \
true, /* Enable automatic lock recovery. */ \
false /* Don't enable dither function. */ \
}

DPLL initialization values for 80,000,000 Hz using HFXO as reference clock, M = 1919, N = 3999.

Definition at line 651 of file em_cmu.h.

Referenced by BSP_initClocks().

#define CMU_DPLL_LFXO_TO_40MHZ
Value:
{ \
39998805, /* Target frequency. */ \
3661, /* Factor N. */ \
2, /* Factor M. */ \
cmuSelect_LFXO, /* Select LFXO as reference clock. */ \
cmuDPLLEdgeSel_Fall, /* Select falling edge of ref clock. */ \
cmuDPLLLockMode_Freq, /* Use frequency lock mode. */ \
true, /* Enable automatic lock recovery. */ \
false /* Don't enable dither function. */ \
}

DPLL initialization values for 39,998,805 Hz using LFXO as reference clock, M=2 and N=3661.

Definition at line 635 of file em_cmu.h.

Referenced by BSP_initClocks().

#define CMU_DPLLINIT_DEFAULT
Value:
{ \
80000000, /* Target frequency. */ \
(4000 - 1), /* Factor N. */ \
(1920 - 1), /* Factor M. */ \
cmuSelect_HFXO, /* Select HFXO as reference clock. */ \
cmuDPLLEdgeSel_Fall, /* Select falling edge of ref clock. */ \
cmuDPLLLockMode_Freq, /* Use frequency lock mode. */ \
true, /* Enable automatic lock recovery. */ \
false /* Don't enable dither function. */ \
}

Default configurations for DPLL initialization. When using this macro you need to modify the N and M factor and the desired frequency to match the components placed on the board.

Definition at line 668 of file em_cmu.h.

#define CMU_HFRCODPLL_MAX   cmuHFRCODPLLFreq_80M0Hz

HFRCODPLL minimum frequency

Definition at line 128 of file em_cmu.h.

#define CMU_HFRCODPLL_MIN   cmuHFRCODPLLFreq_1M0Hz

HFRCODPLL maximum frequency

Definition at line 126 of file em_cmu.h.

#define CMU_HFRCOEM23_MAX   cmuHFRCOEM23Freq_40M0Hz

HFRCOEM23 minimum frequency

Definition at line 148 of file em_cmu.h.

#define CMU_HFRCOEM23_MIN   cmuHFRCOEM23Freq_1M0Hz

HFRCOEM23 maximum frequency

Definition at line 146 of file em_cmu.h.

#define CMU_HFXOINIT_DEFAULT
Value:
{ \
cmuHfxoCbLsbTimeout_416us, \
cmuHfxoSteadyStateTimeout_833us, /* First lock */ \
cmuHfxoSteadyStateTimeout_83us, /* Subsequent locks */ \
0U, /* ctuneXoStartup */ \
0U, /* ctuneXiStartup */ \
32U, /* coreBiasStartup */ \
32U, /* imCoreBiasStartup */ \
cmuHfxoCoreDegen_None, \
cmuHfxoCtuneFixCap_Both, \
_HFXO_XTALCTRL_CTUNEXOANA_DEFAULT, /* ctuneXoAna */ \
_HFXO_XTALCTRL_CTUNEXIANA_DEFAULT, /* ctuneXiAna */ \
60U, /* coreBiasAna */ \
false, /* enXiDcBiasAna */ \
cmuHfxoOscMode_Crystal, \
false, /* forceXo2GndAna */ \
false, /* forceXi2GndAna */ \
false, /* DisOndemand */ \
false, /* ForceEn */ \
false /* Lock registers */ \
}

Default HFXO initialization values for XTAL mode.

Definition at line 572 of file em_cmu.h.

#define CMU_HFXOINIT_EXTERNAL_SINE
Value:
{ \
(CMU_HfxoCbLsbTimeout_TypeDef)0, /* timeoutCbLsb */ \
(CMU_HfxoSteadyStateTimeout_TypeDef)0, /* timeoutSteady, first lock */ \
(CMU_HfxoSteadyStateTimeout_TypeDef)0, /* timeoutSteady, subseq. locks */ \
0U, /* ctuneXoStartup */ \
0U, /* ctuneXiStartup */ \
0U, /* coreBiasStartup */ \
0U, /* imCoreBiasStartup */ \
0U, /* ctuneXoAna */ \
0U, /* ctuneXiAna */ \
0U, /* coreBiasAna */ \
false, /* enXiDcBiasAna, false=DC true=AC coupling of signal */ \
false, /* forceXo2GndAna */ \
false, /* forceXi2GndAna */ \
false, /* DisOndemand */ \
false, /* ForceEn */ \
false /* Lock registers */ \
}
Definition: em_cmu.h:459
Definition: em_cmu.h:414
Definition: em_cmu.h:467
CMU_HfxoSteadyStateTimeout_TypeDef
Definition: em_cmu.h:438
CMU_HfxoCbLsbTimeout_TypeDef
Definition: em_cmu.h:418

Default HFXO initialization values for external sine mode.

Definition at line 596 of file em_cmu.h.

#define CMU_LFXOINIT_DEFAULT
Value:
{ \
1, \
38, \
cmuLfxoStartupDelay_4KCycles, \
cmuLfxoOscMode_Crystal, \
false, /* highAmplitudeEn */ \
true, /* agcEn */ \
false, /* failDetEM4WUEn */ \
false, /* failDetEn */ \
false, /* DisOndemand */ \
false, /* ForceEn */ \
false /* Lock registers */ \
}

Default LFXO initialization values for XTAL mode.

Definition at line 500 of file em_cmu.h.

#define CMU_LFXOINIT_EXTERNAL_CLOCK
Value:
{ \
0U, \
0U, \
cmuLfxoStartupDelay_2Cycles, \
cmuLfxoOscMode_External, \
false, /* highAmplitudeEn */ \
false, /* agcEn */ \
false, /* failDetEM4WUEn */ \
false, /* failDetEn */ \
false, /* DisOndemand */ \
false, /* ForceEn */ \
false /* Lock registers */ \
}

Default LFXO initialization values for external clock mode.

Definition at line 516 of file em_cmu.h.

#define CMU_LFXOINIT_EXTERNAL_SINE
Value:
{ \
0U, \
0U, \
cmuLfxoStartupDelay_2Cycles, \
cmuLfxoOscMode_AcCoupledSine, \
false, /* highAmplitudeEn */ \
false, /* agcEn */ \
false, /* failDetEM4WUEn */ \
false, /* failDetEn */ \
false, /* DisOndemand */ \
false, /* ForceEn */ \
false /* Lock registers */ \
}

Default LFXO initialization values for external sine mode.

Definition at line 532 of file em_cmu.h.

Typedef Documentation

typedef uint32_t CMU_ClkDiv_TypeDef

Clock divider configuration

Definition at line 104 of file em_cmu.h.

Enumeration Type Documentation

Clock points in CMU clock-tree.

Enumerator
cmuClock_SYSCLK 

System clock.

cmuClock_HCLK 

Core and AHB bus interface clock.

cmuClock_EXPCLK 

Export clock.

cmuClock_PCLK 

Peripheral APB bus interface clock.

cmuClock_LSPCLK 

Low speed peripheral APB bus interface clock.

cmuClock_IADCCLK 

IADC clock.

cmuClock_EM01GRPACLK 

EM01GRPA clock.

cmuClock_EM23GRPACLK 

EM23GRPA clock.

cmuClock_EM4GRPACLK 

EM4GRPA clock.

cmuClock_WDOG0CLK 

WDOG0 clock.

cmuClock_WDOG1CLK 

WDOG1 clock.

cmuClock_DPLLREFCLK 

DPLL reference clock.

cmuClock_TRACECLK 

Debug trace clock.

cmuClock_RTCCCLK 

RTCC clock.

cmuClock_CORE 

Cortex-M33 core clock.

cmuClock_SYSTICK 

Optional Cortex-M33 SYSTICK clock.

cmuClock_ACMP0 

ACMP0 clock.

cmuClock_ACMP1 

ACMP1 clock.

cmuClock_BURTC 

BURTC clock.

cmuClock_GPCRC 

GPCRC clock.

cmuClock_GPIO 

GPIO clock.

cmuClock_I2C0 

I2C0 clock.

cmuClock_I2C1 

I2C1 clock.

cmuClock_IADC0 

IADC clock.

cmuClock_LDMA 

RTCC clock.

cmuClock_LETIMER0 

LETIMER clock.

cmuClock_PRS 

PRS clock.

cmuClock_RTCC 

RTCC clock.

cmuClock_TIMER0 

TIMER0 clock.

cmuClock_TIMER1 

TIMER1 clock.

cmuClock_TIMER2 

TIMER2 clock.

cmuClock_TIMER3 

TIMER3 clock.

cmuClock_USART0 

USART0 clock.

cmuClock_USART1 

USART1 clock.

cmuClock_USART2 

USART2 clock.

cmuClock_WDOG0 

WDOG0 clock.

cmuClock_WDOG1 

WDOG1 clock.

cmuClock_PDM 

PDM clock.

Definition at line 153 of file em_cmu.h.

DPLL reference clock edge detect selector.

Enumerator
cmuDPLLEdgeSel_Fall 

Detect falling edge of reference clock.

cmuDPLLEdgeSel_Rise 

Detect rising edge of reference clock.

Definition at line 381 of file em_cmu.h.

DPLL lock mode selector.

Enumerator
cmuDPLLLockMode_Freq 

Frequency lock mode.

cmuDPLLLockMode_Phase 

Phase lock mode.

Definition at line 387 of file em_cmu.h.

HFRCODPLL frequency bands

Enumerator
cmuHFRCODPLLFreq_1M0Hz 

1MHz RC band.

cmuHFRCODPLLFreq_2M0Hz 

2MHz RC band.

cmuHFRCODPLLFreq_4M0Hz 

4MHz RC band.

cmuHFRCODPLLFreq_7M0Hz 

7MHz RC band.

cmuHFRCODPLLFreq_13M0Hz 

13MHz RC band.

cmuHFRCODPLLFreq_16M0Hz 

16MHz RC band.

cmuHFRCODPLLFreq_19M0Hz 

19MHz RC band.

cmuHFRCODPLLFreq_26M0Hz 

26MHz RC band.

cmuHFRCODPLLFreq_32M0Hz 

32MHz RC band.

cmuHFRCODPLLFreq_38M0Hz 

38MHz RC band.

cmuHFRCODPLLFreq_48M0Hz 

48MHz RC band.

cmuHFRCODPLLFreq_56M0Hz 

56MHz RC band.

cmuHFRCODPLLFreq_64M0Hz 

64MHz RC band.

cmuHFRCODPLLFreq_80M0Hz 

80MHz RC band.

Definition at line 107 of file em_cmu.h.

HFRCOEM23 frequency bands

Enumerator
cmuHFRCOEM23Freq_1M0Hz 

1MHz RC band.

cmuHFRCOEM23Freq_2M0Hz 

2MHz RC band.

cmuHFRCOEM23Freq_4M0Hz 

4MHz RC band.

cmuHFRCOEM23Freq_13M0Hz 

13MHz RC band.

cmuHFRCOEM23Freq_16M0Hz 

16MHz RC band.

cmuHFRCOEM23Freq_19M0Hz 

19MHz RC band.

cmuHFRCOEM23Freq_26M0Hz 

26MHz RC band.

cmuHFRCOEM23Freq_32M0Hz 

32MHz RC band.

cmuHFRCOEM23Freq_40M0Hz 

40MHz RC band.

Definition at line 132 of file em_cmu.h.

HFXO core bias LSB change timeout.

Enumerator
cmuHfxoCbLsbTimeout_8us 

8 us timeout.

cmuHfxoCbLsbTimeout_20us 

20 us timeout.

cmuHfxoCbLsbTimeout_41us 

41 us timeout.

cmuHfxoCbLsbTimeout_62us 

62 us timeout.

cmuHfxoCbLsbTimeout_83us 

83 us timeout.

cmuHfxoCbLsbTimeout_104us 

104 us timeout.

cmuHfxoCbLsbTimeout_125us 

125 us timeout.

cmuHfxoCbLsbTimeout_166us 

166 us timeout.

cmuHfxoCbLsbTimeout_208us 

208 us timeout.

cmuHfxoCbLsbTimeout_250us 

250 us timeout.

cmuHfxoCbLsbTimeout_333us 

333 us timeout.

cmuHfxoCbLsbTimeout_416us 

416 us timeout.

cmuHfxoCbLsbTimeout_833us 

833 us timeout.

cmuHfxoCbLsbTimeout_1250us 

1250 us timeout.

cmuHfxoCbLsbTimeout_2083us 

2083 us timeout.

cmuHfxoCbLsbTimeout_3750us 

3750 us timeout.

Definition at line 418 of file em_cmu.h.

HFXO core degeneration control.

Enumerator
cmuHfxoCoreDegen_None 

No core degeneration.

cmuHfxoCoreDegen_33 

Core degeneration control 33.

cmuHfxoCoreDegen_50 

Core degeneration control 50.

cmuHfxoCoreDegen_100 

Core degeneration control 100.

Definition at line 458 of file em_cmu.h.

HFXO XI and XO pin fixed capacitor control.

Enumerator
cmuHfxoCtuneFixCap_None 

No fixed capacitors.

cmuHfxoCtuneFixCap_Xi 

Fixed capacitor on XI pin.

cmuHfxoCtuneFixCap_Xo 

Fixed capacitor on XO pin.

cmuHfxoCtuneFixCap_Both 

Fixed capacitor on both pins.

Definition at line 466 of file em_cmu.h.

HFXO oscillator modes.

Enumerator
cmuHfxoOscMode_Crystal 

Crystal oscillator.

cmuHfxoOscMode_ExternalSine 

External digital clock.

Definition at line 412 of file em_cmu.h.

HFXO steady state timeout.

Enumerator
cmuHfxoSteadyStateTimeout_16us 

16 us timeout.

cmuHfxoSteadyStateTimeout_41us 

41 us timeout.

cmuHfxoSteadyStateTimeout_83us 

83 us timeout.

cmuHfxoSteadyStateTimeout_125us 

125 us timeout.

cmuHfxoSteadyStateTimeout_166us 

166 us timeout.

cmuHfxoSteadyStateTimeout_208us 

208 us timeout.

cmuHfxoSteadyStateTimeout_250us 

250 us timeout.

cmuHfxoSteadyStateTimeout_333us 

333 us timeout.

cmuHfxoSteadyStateTimeout_416us 

416 us timeout.

cmuHfxoSteadyStateTimeout_500us 

500 us timeout.

cmuHfxoSteadyStateTimeout_666us 

666 us timeout.

cmuHfxoSteadyStateTimeout_833us 

833 us timeout.

cmuHfxoSteadyStateTimeout_1666us 

1666 us timeout.

cmuHfxoSteadyStateTimeout_2500us 

2500 us timeout.

cmuHfxoSteadyStateTimeout_4166us 

4166 us timeout.

cmuHfxoSteadyStateTimeout_7500us 

7500 us timeout.

Definition at line 438 of file em_cmu.h.

LFXO oscillator modes.

Enumerator
cmuLfxoOscMode_Crystal 

Crystal oscillator.

cmuLfxoOscMode_AcCoupledSine 

External AC coupled sine.

cmuLfxoOscMode_External 

External digital clock.

Definition at line 393 of file em_cmu.h.

LFXO start-up timeout delay.

Enumerator
cmuLfxoStartupDelay_2Cycles 

2 cycles start-up delay.

cmuLfxoStartupDelay_256Cycles 

256 cycles start-up delay.

cmuLfxoStartupDelay_1KCycles 

1K cycles start-up delay.

cmuLfxoStartupDelay_2KCycles 

2K cycles start-up delay.

cmuLfxoStartupDelay_4KCycles 

4K cycles start-up delay.

cmuLfxoStartupDelay_8KCycles 

8K cycles start-up delay.

cmuLfxoStartupDelay_16KCycles 

16K cycles start-up delay.

cmuLfxoStartupDelay_32KCycles 

32K cycles start-up delay.

Definition at line 400 of file em_cmu.h.

Oscillator types.

Enumerator
cmuOsc_LFXO 

Low frequency crystal oscillator.

cmuOsc_LFRCO 

Low frequency RC oscillator.

cmuOsc_FSRCO 

Fast startup fixed frequency RC oscillator.

cmuOsc_HFXO 

High frequency crystal oscillator.

cmuOsc_HFRCODPLL 

High frequency RC and DPLL oscillator.

cmuOsc_HFRCOEM23 

High frequency deep sleep RC oscillator.

cmuOsc_ULFRCO 

Ultra low frequency RC oscillator.

Definition at line 320 of file em_cmu.h.

Enumerator
cmuPrecisionDefault 

Default precision mode.

cmuPrecisionHigh 

High precision mode.

Definition at line 474 of file em_cmu.h.

Selectable clock sources.

Enumerator
cmuSelect_Error 

Usage error.

cmuSelect_Disabled 

Clock selector disabled.

cmuSelect_FSRCO 

Fast startup fixed frequency RC oscillator.

cmuSelect_HFXO 

High frequency crystal oscillator.

cmuSelect_HFRCODPLL 

High frequency RC and DPLL oscillator.

cmuSelect_HFRCOEM23 

High frequency deep sleep RC oscillator.

cmuSelect_CLKIN0 

External clock input.

cmuSelect_LFXO 

Low frequency crystal oscillator.

cmuSelect_LFRCO 

Low frequency RC oscillator.

cmuSelect_ULFRCO 

Ultra low frequency RC oscillator.

cmuSelect_PCLK 

Peripheral APB bus interface clock.

cmuSelect_HCLK 

Core and AHB bus interface clock.

cmuSelect_HCLKDIV1024 

Prescaled HCLK frequency clock.

cmuSelect_EM01GRPACLK 

EM01GRPA clock.

cmuSelect_EXPCLK 

Pin export clock.

cmuSelect_PRS 

PRS input as clock.

Definition at line 334 of file em_cmu.h.

Function Documentation

uint32_t CMU_Calibrate ( uint32_t  cycles,
CMU_Select_TypeDef  ref 
)

Calibrate an oscillator.

Run a calibration of a selectable reference clock againt HCLK. Please refer to the reference manual, CMU chapter, for further details.

Note
This function will not return until calibration measurement is completed.
Parameters
[in]cyclesThe number of HCLK cycles to run calibration. Increasing this number increases precision, but the calibration will take more time.
[in]refThe reference clock used to compare against HCLK.
Returns
The number of ticks the selected reference clock ticked while running cycles ticks of the HCLK clock.

Definition at line 782 of file em_cmu.c.

References _CMU_CALCTRL_CALTOP_MASK, _CMU_CALCTRL_CALTOP_SHIFT, CMU_CalibrateConfig(), CMU_CalibrateCountGet(), CMU_CalibrateStart(), and cmuSelect_HCLK.

void CMU_CalibrateConfig ( uint32_t  downCycles,
CMU_Select_TypeDef  downSel,
CMU_Select_TypeDef  upSel 
)

Configure clock calibration.

Configure a calibration for a selectable clock source against another selectable reference clock. Refer to the reference manual, CMU chapter, for further details.

Note
After configuration, a call to CMU_CalibrateStart() is required, and the resulting calibration value can be read with the CMU_CalibrateCountGet() function call.
Parameters
[in]downCyclesThe number of downSel clock cycles to run calibration. Increasing this number increases precision, but the calibration will take more time.
[in]downSelThe clock which will be counted down downCycles cycles.
[in]upSelThe reference clock, the number of cycles generated by this clock will be counted and added up, the result can be given with the CMU_CalibrateCountGet() function call.

Definition at line 819 of file em_cmu.c.

References _CMU_CALCTRL_CALTOP_MASK, _CMU_CALCTRL_CALTOP_SHIFT, _CMU_CALCTRL_DOWNSEL_MASK, _CMU_CALCTRL_UPSEL_MASK, CMU, CMU_CALCTRL_DOWNSEL_FSRCO, CMU_CALCTRL_DOWNSEL_HCLK, CMU_CALCTRL_DOWNSEL_HFRCODPLL, CMU_CALCTRL_DOWNSEL_HFRCOEM23, CMU_CALCTRL_DOWNSEL_HFXO, CMU_CALCTRL_DOWNSEL_LFRCO, CMU_CALCTRL_DOWNSEL_LFXO, CMU_CALCTRL_DOWNSEL_PRS, CMU_CALCTRL_DOWNSEL_ULFRCO, CMU_CALCTRL_UPSEL_FSRCO, CMU_CALCTRL_UPSEL_HFRCODPLL, CMU_CALCTRL_UPSEL_HFRCOEM23, CMU_CALCTRL_UPSEL_HFXO, CMU_CALCTRL_UPSEL_LFRCO, CMU_CALCTRL_UPSEL_LFXO, CMU_CALCTRL_UPSEL_PRS, CMU_CALCTRL_UPSEL_ULFRCO, cmuSelect_Disabled, cmuSelect_FSRCO, cmuSelect_HCLK, cmuSelect_HFRCODPLL, cmuSelect_HFRCOEM23, cmuSelect_HFXO, cmuSelect_LFRCO, cmuSelect_LFXO, cmuSelect_PRS, and cmuSelect_ULFRCO.

Referenced by CMU_Calibrate().

__STATIC_INLINE void CMU_CalibrateCont ( bool  enable)

Configures continuous calibration mode.

Parameters
[in]enableIf true, enables continuous calibration, if false disables continuous calibration.

Definition at line 750 of file em_cmu.h.

References _CMU_CALCTRL_CONT_SHIFT, BUS_RegBitWrite(), and CMU.

uint32_t CMU_CalibrateCountGet ( void  )

Get calibration count value.

Note
If continuous calibrartion mode is active, calibration busy will almost always be off, and we just need to read the value, where the normal case would be that this function call has been triggered by the CALRDY interrupt flag.
Returns
Calibration count, the number of UPSEL clocks (see CMU_CalibrateConfig()) in the period of DOWNSEL oscillator clock cycles configured by a previous write operation to CMU->CALCNT.

Definition at line 943 of file em_cmu.c.

References CMU, CMU_CALCTRL_CONT, and CMU_STATUS_CALRDY.

Referenced by CMU_Calibrate().

__STATIC_INLINE void CMU_CalibrateStart ( void  )

Starts calibration.

Note
This call is usually invoked after CMU_CalibrateConfig() and possibly CMU_CalibrateCont().

Definition at line 762 of file em_cmu.h.

References CMU, and CMU_CALCMD_CALSTART.

Referenced by CMU_Calibrate().

void CMU_ClkOutPinConfig ( uint32_t  clkNo,
CMU_Select_TypeDef  sel,
CMU_ClkDiv_TypeDef  clkDiv,
GPIO_Port_TypeDef  port,
unsigned int  pin 
)
CMU_ClkDiv_TypeDef CMU_ClockDivGet ( CMU_Clock_TypeDef  clock)

Get clock divisor.

Parameters
[in]clockClock point to get divisor for. Notice that not all clock points have a divisors. Please refer to CMU overview in reference manual.
Returns
The current clock point divisor. 1 is returned if clock specifies a clock point without divisor.

Definition at line 1081 of file em_cmu.c.

References _CMU_EXPORTCLKCTRL_PRESC_MASK, _CMU_EXPORTCLKCTRL_PRESC_SHIFT, _CMU_SYSCLKCTRL_HCLKPRESC_DIV1, _CMU_SYSCLKCTRL_HCLKPRESC_DIV2, _CMU_SYSCLKCTRL_HCLKPRESC_DIV4, _CMU_SYSCLKCTRL_HCLKPRESC_MASK, _CMU_SYSCLKCTRL_HCLKPRESC_SHIFT, _CMU_SYSCLKCTRL_PCLKPRESC_MASK, _CMU_SYSCLKCTRL_PCLKPRESC_SHIFT, CMU, cmuClock_CORE, cmuClock_EXPCLK, cmuClock_HCLK, cmuClock_PCLK, and cmuClock_TRACECLK.

Referenced by CMU_ClockFreqGet(), CMU_DPLLLock(), and UDELAY_Calibrate().

void CMU_ClockDivSet ( CMU_Clock_TypeDef  clock,
CMU_ClkDiv_TypeDef  div 
)

Set clock divisor.

Parameters
[in]clockClock point to set divisor for. Notice that not all clock points have a divisor, please refer to CMU overview in the reference manual.
[in]divThe clock divisor to use.

Definition at line 1147 of file em_cmu.c.

References _CMU_EXPORTCLKCTRL_PRESC_MASK, _CMU_EXPORTCLKCTRL_PRESC_SHIFT, _CMU_SYSCLKCTRL_HCLKPRESC_MASK, _CMU_SYSCLKCTRL_HCLKPRESC_SHIFT, _CMU_SYSCLKCTRL_PCLKPRESC_MASK, _CMU_SYSCLKCTRL_PCLKPRESC_SHIFT, CMU, CMU_UpdateWaitStates(), cmuClock_CORE, cmuClock_EXPCLK, cmuClock_HCLK, cmuClock_PCLK, cmuClock_TRACECLK, pclkDivMax(), pclkDivOptimize(), SystemCoreClockGet(), and waitStateMax().

Referenced by CAPLESENSE_setupCMU(), CMU_DPLLLock(), pclkDivMax(), pclkDivOptimize(), RETARGET_SerialInit(), RTCDRV_Init(), SegmentLCD_Init(), and UDELAY_Calibrate().

void CMU_ClockSelectSet ( CMU_Clock_TypeDef  clock,
CMU_Select_TypeDef  ref 
)

Select reference clock/oscillator used for a clock branch.

Parameters
[in]clockClock branch to select reference clock for.
[in]refReference selected for clocking, please refer to reference manual for for details on which reference is available for a specific clock branch.

Definition at line 1345 of file em_cmu.c.

References _CMU_DPLLREFCLKCTRL_CLKSEL_MASK, _CMU_EM01GRPACLKCTRL_CLKSEL_MASK, _CMU_EM23GRPACLKCTRL_CLKSEL_MASK, _CMU_EM4GRPACLKCTRL_CLKSEL_MASK, _CMU_IADCCLKCTRL_CLKSEL_MASK, _CMU_RTCCCLKCTRL_CLKSEL_MASK, _CMU_SYSCLKCTRL_CLKSEL_MASK, _CMU_TRACECLKCTRL_CLKSEL_MASK, _CMU_WDOG0CLKCTRL_CLKSEL_MASK, _CMU_WDOG1CLKCTRL_CLKSEL_MASK, CMU, CMU_DPLLREFCLKCTRL_CLKSEL_CLKIN0, CMU_DPLLREFCLKCTRL_CLKSEL_DISABLED, CMU_DPLLREFCLKCTRL_CLKSEL_HFXO, CMU_DPLLREFCLKCTRL_CLKSEL_LFXO, CMU_EM01GRPACLKCTRL_CLKSEL_FSRCO, CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLL, CMU_EM01GRPACLKCTRL_CLKSEL_HFRCOEM23, CMU_EM01GRPACLKCTRL_CLKSEL_HFXO, CMU_EM23GRPACLKCTRL_CLKSEL_LFRCO, CMU_EM23GRPACLKCTRL_CLKSEL_LFXO, CMU_EM23GRPACLKCTRL_CLKSEL_ULFRCO, CMU_EM4GRPACLKCTRL_CLKSEL_LFRCO, CMU_EM4GRPACLKCTRL_CLKSEL_LFXO, CMU_EM4GRPACLKCTRL_CLKSEL_ULFRCO, CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK, CMU_IADCCLKCTRL_CLKSEL_FSRCO, CMU_IADCCLKCTRL_CLKSEL_HFRCOEM23, CMU_RTCCCLKCTRL_CLKSEL_LFRCO, CMU_RTCCCLKCTRL_CLKSEL_LFXO, CMU_RTCCCLKCTRL_CLKSEL_ULFRCO, CMU_SYSCLKCTRL_CLKSEL_CLKIN0, CMU_SYSCLKCTRL_CLKSEL_FSRCO, CMU_SYSCLKCTRL_CLKSEL_HFRCODPLL, CMU_SYSCLKCTRL_CLKSEL_HFXO, CMU_TRACECLKCTRL_CLKSEL_HCLK, CMU_TRACECLKCTRL_CLKSEL_HFRCOEM23, CMU_UpdateWaitStates(), CMU_WDOG0CLKCTRL_CLKSEL_HCLKDIV1024, CMU_WDOG0CLKCTRL_CLKSEL_LFRCO, CMU_WDOG0CLKCTRL_CLKSEL_LFXO, CMU_WDOG0CLKCTRL_CLKSEL_ULFRCO, CMU_WDOG1CLKCTRL_CLKSEL_HCLKDIV1024, CMU_WDOG1CLKCTRL_CLKSEL_LFRCO, CMU_WDOG1CLKCTRL_CLKSEL_LFXO, CMU_WDOG1CLKCTRL_CLKSEL_ULFRCO, cmuClock_BURTC, cmuClock_DPLLREFCLK, cmuClock_EM01GRPACLK, cmuClock_EM23GRPACLK, cmuClock_EM4GRPACLK, cmuClock_IADC0, cmuClock_IADCCLK, cmuClock_LETIMER0, cmuClock_RTCC, cmuClock_RTCCCLK, cmuClock_SYSCLK, cmuClock_SYSTICK, cmuClock_TIMER0, cmuClock_TIMER1, cmuClock_TIMER2, cmuClock_TIMER3, cmuClock_TRACECLK, cmuClock_WDOG0, cmuClock_WDOG0CLK, cmuClock_WDOG1, cmuClock_WDOG1CLK, cmuSelect_CLKIN0, cmuSelect_Disabled, cmuSelect_EM01GRPACLK, cmuSelect_FSRCO, cmuSelect_HCLK, cmuSelect_HCLKDIV1024, cmuSelect_HFRCODPLL, cmuSelect_HFRCOEM23, cmuSelect_HFXO, cmuSelect_LFRCO, cmuSelect_LFXO, cmuSelect_ULFRCO, HFXO0, HFXO_CTRL_DISONDEMAND, HFXO_CTRL_FORCEEN, pclkDivMax(), pclkDivOptimize(), SystemCoreClockGet(), and waitStateMax().

Referenced by BSP_BccInit(), BSP_initClocks(), CAPLESENSE_setupCMU(), CMU_DPLLLock(), MIC_init(), RETARGET_SerialInit(), RTCDRV_Init(), SegmentLCD_Init(), and UDELAY_Calibrate().

bool CMU_DPLLLock ( const CMU_DPLLInit_TypeDef init)

Lock the DPLL to a given frequency. The frequency is given by: Fout = Fref * (N+1) / (M+1).

Note
This function does not check if the given N & M values will actually produce the desired target frequency.
N & M limitations:
300 < N <= 4095
0 <= M <= 4095
Any peripheral running off HFRCODPLL should be switched to a lower frequency clock (if possible) prior to calling this function to avoid over-clocking.
Parameters
[in]initDPLL setup parameter struct.
Returns
Returns false on invalid target frequency or DPLL locking error.

Definition at line 1740 of file em_cmu.c.

References _DPLL_CFG1_M_MASK, _DPLL_CFG1_M_SHIFT, _DPLL_CFG1_N_MASK, _DPLL_CFG1_N_SHIFT, _DPLL_CFG_AUTORECOVER_SHIFT, _DPLL_CFG_DITHEN_SHIFT, _DPLL_CFG_EDGESEL_SHIFT, _DPLL_CFG_MODE_SHIFT, _HFRCO_CAL_TUNING_MASK, _HFRCO_CAL_TUNING_SHIFT, CMU_DPLLInit_TypeDef::autoRecover, CMU, CMU_ClockDivGet(), CMU_ClockDivSet(), CMU_ClockSelectGet(), CMU_ClockSelectSet(), CMU_UpdateWaitStates(), cmuClock_DPLLREFCLK, cmuClock_HCLK, cmuClock_SYSCLK, cmuSelect_HFRCODPLL, CMU_DPLLInit_TypeDef::ditherEn, DPLL0, DPLL_EN_EN, DPLL_IF_LOCK, DPLL_IF_LOCKFAILHIGH, DPLL_IF_LOCKFAILLOW, DPLL_STATUS_ENS, DPLL_STATUS_RDY, CMU_DPLLInit_TypeDef::edgeSel, CMU_DPLLInit_TypeDef::frequency, HFRCO0, HFRCODPLLDevinfoGet(), CMU_DPLLInit_TypeDef::lockMode, CMU_DPLLInit_TypeDef::m, CMU_DPLLInit_TypeDef::n, pclkDivMax(), pclkDivOptimize(), CMU_DPLLInit_TypeDef::refClk, SystemCoreClockGet(), SystemHFRCODPLLClockGet(), SystemHFRCODPLLClockSet(), and waitStateMax().

Referenced by BSP_initClocks().

__STATIC_INLINE void CMU_DPLLUnlock ( void  )

Unlock the DPLL.

Note
The HFRCODPLL oscillator is not turned off.

Definition at line 782 of file em_cmu.h.

References DPLL0, and DPLL_EN_EN.

CMU_HFRCODPLLFreq_TypeDef CMU_HFRCODPLLBandGet ( void  )

Get HFRCODPLL band in use.

Returns
HFRCODPLL band in use.

Definition at line 1862 of file em_cmu.c.

References SystemHFRCODPLLClockGet().

void CMU_HFRCODPLLBandSet ( CMU_HFRCODPLLFreq_TypeDef  freq)

Set HFRCODPLL band and the tuning value based on the value in the calibration table made during production.

Parameters
[in]freqHFRCODPLL frequency band to activate.

Definition at line 1875 of file em_cmu.c.

References _HFRCO_CAL_CLKDIV_MASK, CMU, CMU_ClockSelectGet(), CMU_UpdateWaitStates(), cmuClock_SYSCLK, cmuHFRCODPLLFreq_1M0Hz, cmuHFRCODPLLFreq_2M0Hz, cmuSelect_HFRCODPLL, DPLL0, DPLL_EN_EN, DPLL_STATUS_ENS, DPLL_STATUS_RDY, HFRCO0, HFRCO_CAL_CLKDIV_DIV2, HFRCO_CAL_CLKDIV_DIV4, HFRCODPLLDevinfoGet(), pclkDivMax(), pclkDivOptimize(), SystemCoreClockGet(), SystemHFRCODPLLClockSet(), and waitStateMax().

Referenced by CHIP_Init().

CMU_HFRCOEM23Freq_TypeDef CMU_HFRCOEM23BandGet ( void  )

Get HFRCOEM23 band in use.

Returns
HFRCOEM23 band in use.

Definition at line 557 of file em_cmu.c.

References SystemHFRCOEM23ClockGet().

void CMU_HFRCOEM23BandSet ( CMU_HFRCOEM23Freq_TypeDef  freq)

Set HFRCOEM23 band and the tuning value based on the value in the calibration table made during production.

Parameters
[in]freqHFRCOEM23 frequency band to activate.

Definition at line 570 of file em_cmu.c.

References _HFRCO_CAL_CLKDIV_MASK, cmuHFRCOEM23Freq_1M0Hz, cmuHFRCOEM23Freq_2M0Hz, HFRCO_CAL_CLKDIV_DIV2, HFRCO_CAL_CLKDIV_DIV4, and HFRCOEM23.

void CMU_HFXOInit ( const CMU_HFXOInit_TypeDef hfxoInit)

Initialize all HFXO control registers.

Note
HFXO configuration should be obtained from a configuration tool, app note or xtal datasheet. This function returns early if HFXO is already selected as SYSCLK.
Parameters
[in]hfxoInitHFXO setup parameters.

Definition at line 1952 of file em_cmu.c.

References _HFXO_CFG_ENXIDCBIASANA_MASK, _HFXO_CFG_ENXIDCBIASANA_SHIFT, _HFXO_CFG_MODE_MASK, _HFXO_CFG_MODE_SHIFT, _HFXO_CFG_SQBUFSCHTRGANA_MASK, _HFXO_CTRL_DISONDEMAND_MASK, _HFXO_CTRL_DISONDEMAND_SHIFT, _HFXO_CTRL_FORCEEN_MASK, _HFXO_CTRL_FORCEEN_SHIFT, _HFXO_CTRL_FORCEXI2GNDANA_MASK, _HFXO_CTRL_FORCEXI2GNDANA_SHIFT, _HFXO_CTRL_FORCEXO2GNDANA_MASK, _HFXO_CTRL_FORCEXO2GNDANA_SHIFT, _HFXO_STATUS_ENS_MASK, _HFXO_XTALCFG_COREBIASSTARTUP_MASK, _HFXO_XTALCFG_COREBIASSTARTUP_SHIFT, _HFXO_XTALCFG_COREBIASSTARTUPI_MASK, _HFXO_XTALCFG_COREBIASSTARTUPI_SHIFT, _HFXO_XTALCFG_CTUNEXISTARTUP_MASK, _HFXO_XTALCFG_CTUNEXISTARTUP_SHIFT, _HFXO_XTALCFG_CTUNEXOSTARTUP_MASK, _HFXO_XTALCFG_CTUNEXOSTARTUP_SHIFT, _HFXO_XTALCFG_TIMEOUTCBLSB_MASK, _HFXO_XTALCFG_TIMEOUTCBLSB_SHIFT, _HFXO_XTALCFG_TIMEOUTSTEADY_MASK, _HFXO_XTALCFG_TIMEOUTSTEADY_SHIFT, _HFXO_XTALCTRL_COREBIASANA_SHIFT, _HFXO_XTALCTRL_COREDGENANA_MASK, _HFXO_XTALCTRL_COREDGENANA_SHIFT, _HFXO_XTALCTRL_CTUNEFIXANA_MASK, _HFXO_XTALCTRL_CTUNEFIXANA_SHIFT, _HFXO_XTALCTRL_CTUNEXIANA_SHIFT, _HFXO_XTALCTRL_CTUNEXOANA_SHIFT, CMU, CMU_ClockSelectGet(), cmuClock_SYSCLK, cmuHfxoOscMode_Crystal, cmuSelect_HFXO, CMU_HFXOInit_TypeDef::coreBiasAna, CMU_HFXOInit_TypeDef::coreBiasStartup, CMU_HFXOInit_TypeDef::coreDegenAna, CMU_HFXOInit_TypeDef::ctuneFixAna, CMU_HFXOInit_TypeDef::ctuneXiAna, CMU_HFXOInit_TypeDef::ctuneXiStartup, CMU_HFXOInit_TypeDef::ctuneXoAna, CMU_HFXOInit_TypeDef::ctuneXoStartup, CMU_HFXOInit_TypeDef::disOnDemand, CMU_HFXOInit_TypeDef::enXiDcBiasAna, CMU_HFXOInit_TypeDef::forceEn, CMU_HFXOInit_TypeDef::forceXi2GndAna, CMU_HFXOInit_TypeDef::forceXo2GndAna, HFXO0, HFXO_CFG_SQBUFSCHTRGANA, HFXO_CTRL_DISONDEMAND, HFXO_CTRL_FORCEEN, HFXO_LOCK_LOCKKEY_UNLOCK, HFXO_STATUS_COREBIASOPTRDY, HFXO_STATUS_ENS, HFXO_STATUS_FSMLOCK, HFXO_STATUS_RDY, HFXO_XTALCTRL_SKIPCOREBIASOPT, CMU_HFXOInit_TypeDef::imCoreBiasStartup, CMU_HFXOInit_TypeDef::mode, CMU_HFXOInit_TypeDef::regLock, CMU_HFXOInit_TypeDef::timeoutCbLsb, CMU_HFXOInit_TypeDef::timeoutSteady, and CMU_HFXOInit_TypeDef::timeoutSteadyFirstLock.

Referenced by BSP_initClocks().

__STATIC_INLINE void CMU_IntClear ( uint32_t  flags)

Clear one or more pending CMU interrupt flags.

Parameters
[in]flagsCMU interrupt sources to clear.

Definition at line 794 of file em_cmu.h.

References CMU.

__STATIC_INLINE void CMU_IntDisable ( uint32_t  flags)

Disable one or more CMU interrupt sources.

Parameters
[in]flagsCMU interrupt sources to disable.

Definition at line 806 of file em_cmu.h.

References CMU.

__STATIC_INLINE void CMU_IntEnable ( uint32_t  flags)

Enable one or more CMU interrupt sources.

Note
Depending on the use, a pending interrupt may already be set prior to enabling the interrupt. Consider using CMU_IntClear() prior to enabling if such a pending interrupt should be ignored.
Parameters
[in]flagsCMU interrupt sources to enable.

Definition at line 823 of file em_cmu.h.

References CMU.

__STATIC_INLINE uint32_t CMU_IntGet ( void  )

Get pending CMU interrupt sources.

Returns
CMU interrupt sources pending.

Definition at line 835 of file em_cmu.h.

References CMU.

__STATIC_INLINE uint32_t CMU_IntGetEnabled ( void  )

Get enabled and pending CMU interrupt flags.

Useful for handling more interrupt sources in the same interrupt handler.

Note
The event bits are not cleared by the use of this function.
Returns
Pending and enabled CMU interrupt sources. The return value is the bitwise AND of
  • the enabled interrupt sources in CMU_IEN and
  • the pending interrupt flags CMU_IF

Definition at line 856 of file em_cmu.h.

References CMU.

__STATIC_INLINE void CMU_IntSet ( uint32_t  flags)

Set one or more pending CMU interrupt sources.

Parameters
[in]flagsCMU interrupt sources to set to pending.

Definition at line 871 of file em_cmu.h.

References CMU.

void CMU_LFRCOSetPrecision ( CMU_Precision_TypeDef  precision)

Configure the LFRCO precision.

When enabling high precision mode on the LFRCO the hardware will tune the oscillator automatically using the HFXO as a reference.

Parameters
[in]precisionLFRCO precision, this can be either high or default.

Definition at line 2159 of file em_cmu.c.

References CMU, cmuPrecisionHigh, LFRCO, LFRCO_STATUS_ENS, and SystemHFXOClockGet().

Referenced by BSP_initClocks().

__STATIC_INLINE void CMU_Lock ( void  )

Lock CMU register access in order to protect registers contents against unintended modification.

Please refer to the reference manual for CMU registers that will be locked.

Note
If locking the CMU registers, they must be unlocked prior to using any CMU API functions modifying CMU registers protected by the lock.

Definition at line 889 of file em_cmu.h.

References CMU, and CMU_LOCK_LOCKKEY_UNLOCK.

Referenced by EMU_EnterEM3().

__STATIC_INLINE void CMU_OscillatorEnable ( CMU_Osc_TypeDef  osc,
bool  enable,
bool  wait 
)

Enable/disable oscillator.

Note
This is a dummy function to solve backward compatibility issues.
Parameters
[in]oscThe oscillator to enable/disable.
[in]enable
  • true - enable specified oscillator.
  • false - disable specified oscillator.
[in]waitOnly used if enable is true.
  • true - wait for oscillator start-up time to timeout before returning.
  • false - do not wait for oscillator start-up time to timeout before returning.

Definition at line 914 of file em_cmu.h.

Referenced by BSP_initClocks(), DBG_SWOEnable(), and UDELAY_Calibrate().

uint32_t CMU_OscillatorTuningGet ( CMU_Osc_TypeDef  osc)

Get oscillator frequency tuning setting.

Parameters
[in]oscOscillator to get tuning value for.
Returns
The oscillator frequency tuning setting in use.

Definition at line 2190 of file em_cmu.c.

References _HFRCO_CAL_TUNING_MASK, _HFRCO_CAL_TUNING_SHIFT, _LFRCO_CAL_FREQTRIM_MASK, _LFRCO_CAL_FREQTRIM_SHIFT, CMU, cmuOsc_HFRCODPLL, cmuOsc_HFRCOEM23, cmuOsc_LFRCO, HFRCO0, HFRCOEM23, and LFRCO.

void CMU_OscillatorTuningSet ( CMU_Osc_TypeDef  osc,
uint32_t  val 
)

Set the oscillator frequency tuning control.

Note
Oscillator tuning is done during production, and the tuning value is automatically loaded after a reset. Changing the tuning value from the calibrated value is for more advanced use. Certain oscillators also have build-in tuning optimization.
Parameters
[in]oscOscillator to set tuning value for.
[in]valThe oscillator frequency tuning setting to use.

Definition at line 2240 of file em_cmu.c.

References _HFRCO_CAL_TUNING_MASK, _HFRCO_CAL_TUNING_SHIFT, _LFRCO_CAL_FREQTRIM_MASK, _LFRCO_CAL_FREQTRIM_SHIFT, CMU, cmuOsc_HFRCODPLL, cmuOsc_HFRCOEM23, cmuOsc_LFRCO, HFRCO0, HFRCO_STATUS_SYNCBUSY, HFRCOEM23, and LFRCO.

__STATIC_INLINE uint32_t CMU_PrescToLog2 ( uint32_t  presc)

Convert prescaler dividend to a logarithmic value. It only works for even numbers equal to 2^n.

Parameters
[in]prescAn unscaled dividend (dividend = presc + 1).
Returns
Logarithm of 2, as used by fixed 2^n prescalers.

Definition at line 2945 of file em_cmu.h.

References SL_Log2ToDiv().

void CMU_UpdateWaitStates ( uint32_t  freq,
int  vscale 
)

Configure wait state settings necessary to switch to a given core clock frequency at a certain voltage scale level.

This function will set up the necessary flash wait states. Updating the wait state configuration must be done before increasing the clock frequency and it must be done after decreasing the clock frequency. Updating the wait state configuration must be done before core voltage is decreased and it must be done after a core voltage is increased.

Parameters
[in]freqThe core clock frequency to configure wait-states.
[in]vscaleThe voltage scale to configure wait-states. Expected values are 0 or 1, higher number is lower voltage.
  • 0 = 1.1 V (VSCALE2)
  • 1 = 1.0 V (VSCALE1)

Definition at line 2306 of file em_cmu.c.

References flashWaitStateControl().

Referenced by CMU_ClockDivSet(), CMU_ClockSelectSet(), CMU_DPLLLock(), and CMU_HFRCODPLLBandSet().

__STATIC_INLINE void CMU_WdogLock ( void  )

Lock WDOG register access in order to protect registers contents against unintended modification.

Note
If locking the WDOG registers, they must be unlocked prior to using any emlib API functions modifying registers protected by the lock.

Definition at line 941 of file em_cmu.h.

References CMU, and CMU_WDOGLOCK_LOCKKEY_UNLOCK.

static void dpllRefClkGet ( uint32_t *  freq,
CMU_Select_TypeDef sel 
)
static
static void em01GrpaClkGet ( uint32_t *  freq,
CMU_Select_TypeDef sel 
)
static
static void em23GrpaClkGet ( uint32_t *  freq,
CMU_Select_TypeDef sel 
)
static

Get selected oscillator and frequency for cmuClock_EM23GRPACLK clock tree.

Parameters
[out]freqThe frequency.
[out]selThe selected oscillator.

Definition at line 2429 of file em_cmu.c.

References _CMU_EM23GRPACLKCTRL_CLKSEL_LFRCO, _CMU_EM23GRPACLKCTRL_CLKSEL_LFXO, _CMU_EM23GRPACLKCTRL_CLKSEL_MASK, _CMU_EM23GRPACLKCTRL_CLKSEL_ULFRCO, CMU, cmuSelect_Error, cmuSelect_LFRCO, cmuSelect_LFXO, cmuSelect_ULFRCO, SystemLFRCOClockGet(), SystemLFXOClockGet(), and SystemULFRCOClockGet().

Referenced by CMU_ClockFreqGet(), and CMU_ClockSelectGet().

static void em4GrpaClkGet ( uint32_t *  freq,
CMU_Select_TypeDef sel 
)
static

Get selected oscillator and frequency for cmuClock_EM4GRPACLK clock tree.

Parameters
[out]freqThe frequency.
[out]selThe selected oscillator.

Definition at line 2475 of file em_cmu.c.

References _CMU_EM4GRPACLKCTRL_CLKSEL_LFRCO, _CMU_EM4GRPACLKCTRL_CLKSEL_LFXO, _CMU_EM4GRPACLKCTRL_CLKSEL_MASK, _CMU_EM4GRPACLKCTRL_CLKSEL_ULFRCO, CMU, cmuSelect_Error, cmuSelect_LFRCO, cmuSelect_LFXO, cmuSelect_ULFRCO, SystemLFRCOClockGet(), SystemLFXOClockGet(), and SystemULFRCOClockGet().

Referenced by CMU_ClockFreqGet(), and CMU_ClockSelectGet().

static void flashWaitStateControl ( uint32_t  coreFreq,
int  vscale 
)
static

Configure flash access wait states to support the given core clock frequency and vscale level.

Note
Current implementation sets wait states depending on frequency only. This assumes that applications running on Series 2 Config 2 devices never attemtps to set core frequency above 40MHz at VSCALE1 (1.0V). Series 2 Config 1 devices does not support vscale.
Parameters
[in]coreFreqThe core clock frequency to configure flash wait-states.
[in]vscaleVoltage Scale level. Supported levels are 0 and 1 where 0 is the default.

Definition at line 2526 of file em_cmu.c.

References _MSC_READCTRL_MODE_MASK, _MSC_STATUS_REGLOCK_MASK, _SYSCFG_DMEM0RAMCTRL_RAMWSEN_MASK, _SYSCFG_DMEM0RAMCTRL_RAMWSEN_SHIFT, CMU, MSC, MSC_LOCK_LOCKKEY_LOCK, MSC_LOCK_LOCKKEY_UNLOCK, MSC_READCTRL_MODE_WS0, MSC_READCTRL_MODE_WS1, MSC_STATUS_REGLOCK_LOCKED, and SYSCFG.

Referenced by CMU_UpdateWaitStates(), and waitStateMax().

static uint32_t HFRCODPLLDevinfoGet ( CMU_HFRCODPLLFreq_TypeDef  freq)
static

Get calibrated HFRCODPLL tuning value from Device information (DI) page for a given frequency. Calibration value is not available for all frequency bands.

Parameters
[in]freqHFRCODPLL frequency band

Definition at line 2577 of file em_cmu.c.

References cmuHFRCODPLLFreq_13M0Hz, cmuHFRCODPLLFreq_16M0Hz, cmuHFRCODPLLFreq_19M0Hz, cmuHFRCODPLLFreq_1M0Hz, cmuHFRCODPLLFreq_26M0Hz, cmuHFRCODPLLFreq_2M0Hz, cmuHFRCODPLLFreq_32M0Hz, cmuHFRCODPLLFreq_38M0Hz, cmuHFRCODPLLFreq_48M0Hz, cmuHFRCODPLLFreq_4M0Hz, cmuHFRCODPLLFreq_56M0Hz, cmuHFRCODPLLFreq_64M0Hz, cmuHFRCODPLLFreq_7M0Hz, cmuHFRCODPLLFreq_80M0Hz, and DEVINFO.

Referenced by CMU_DPLLLock(), and CMU_HFRCODPLLBandSet().

static void iadcClkGet ( uint32_t *  freq,
CMU_Select_TypeDef sel 
)
static

Get selected oscillator and frequency for cmuClock_IADCCLK clock tree.

Parameters
[out]freqThe frequency.
[out]selThe selected oscillator.

Definition at line 2654 of file em_cmu.c.

References _CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK, _CMU_IADCCLKCTRL_CLKSEL_FSRCO, _CMU_IADCCLKCTRL_CLKSEL_HFRCOEM23, _CMU_IADCCLKCTRL_CLKSEL_MASK, CMU, cmuSelect_EM01GRPACLK, cmuSelect_Error, cmuSelect_FSRCO, cmuSelect_HFRCOEM23, em01GrpaClkGet(), SystemFSRCOClockGet(), and SystemHFRCOEM23ClockGet().

Referenced by CMU_ClockFreqGet(), and CMU_ClockSelectGet().

static void rtccClkGet ( uint32_t *  freq,
CMU_Select_TypeDef sel 
)
static

Get selected oscillator and frequency for cmuClock_RTCCCLK clock tree.

Parameters
[out]freqThe frequency.
[out]selThe selected oscillator.

Definition at line 2727 of file em_cmu.c.

References _CMU_RTCCCLKCTRL_CLKSEL_LFRCO, _CMU_RTCCCLKCTRL_CLKSEL_LFXO, _CMU_RTCCCLKCTRL_CLKSEL_MASK, _CMU_RTCCCLKCTRL_CLKSEL_ULFRCO, CMU, cmuSelect_Error, cmuSelect_LFRCO, cmuSelect_LFXO, cmuSelect_ULFRCO, SystemLFRCOClockGet(), SystemLFXOClockGet(), and SystemULFRCOClockGet().

Referenced by CMU_ClockFreqGet(), and CMU_ClockSelectGet().

static void wdog0ClkGet ( uint32_t *  freq,
CMU_Select_TypeDef sel 
)
static