Pseudo-Static Random Access Memory (PSRAM) Developer Guide#
Pseudo-static random access memory (PSRAM) combines the high density of dynamic random access memory (DRAM) with the simple interface of static random access memory (SRAM). Internally, PSRAM uses a DRAM core with an integrated self-refresh mechanism, which allows it to behave like SRAM while providing higher capacity and low power consumption.
On SiWx917 devices, PSRAM connects through the quad serial peripheral interface (QSPI) controller and can be used as high-speed external memory for data buffers, graphics, and temporary storage.
This guide introduces PSRAM usage on SiWx917 and explains how to connect, configure, and use PSRAM in an application.
Audience#
This guide is intended for developers and integrators working with PSRAM-based applications on SiWx917 devices:
Firmware and embedded software engineers
Hardware and platform designers integrating external memory
Application engineers optimizing for performance or low power
System integrators validating SiWx917-based boards
PSRAM on SiWx917 Key Concepts#
On the SiWx917 platform, PSRAM:
Is accessed through the QSPI controller
Supports memory-mapped access (auto mode) for seamless reads and writes
Can be used for both data and, in some configurations, instruction fetches
Main Features#
Feature | Description |
|---|---|
High-density storage | Provides larger memory capacity than on-chip SRAM for code, buffers, and caches. |
Self-refresh capability | Automatically refreshes DRAM cells during standby, maintaining data without external refresh logic. |
Quad SPI support | Uses the SiWx917 QSPI controller for high-speed serial access. |
Page and burst access | Supports burst and sequential transfers to improve throughput. |
Fast read and write | Delivers low-latency access suitable for time-sensitive workloads. |
Low power | Offers reduced active and standby power, ideal for battery-powered designs. |
Advantages of Using PSRAM on SiWx917#
Using PSRAM with SiWx917 provides several system-level benefits:
Simplified interface that behaves like SRAM while hiding DRAM refresh details
Scalable performance by offloading large buffers from internal RAM
Flexible memory architecture that supports graphics, networking, and artificial intelligence or machine learning (AI or ML) workloads
Low-leakage designs that support always-on, low-power Internet of Things (IoT) devices when combined with appropriate power modes
Best Practices#
To integrate PSRAM effectively with SiWx917:
Use QSPI auto (memory-mapped) mode where possible to reduce access latency.
Validate power modes and confirm standby retention and wake-up timing for your specific PSRAM part.
Ensure QSPI clocks are stable before starting high-speed transfers.
Avoid unnecessary deep power-down cycles that may drop PSRAM contents or add wake-up overhead.
Use verified configuration data, such as master boot record (MBR) or user configuration (UC) settings, to ensure correct QSPI timing and mode.
Benchmark read and write performance under real power-state conditions to confirm expected behavior.
Subsequent sections of this guide describe the architecture, initialization steps, application programming interfaces (APIs), low-power operation, debugging techniques, and common PSRAM scenarios for SiWx917.