Pseudo-Static Random Access Memory (PSRAM) Low-Power Instance#

Pseudo-static random access memory (PSRAM) on SiWx917 devices supports multiple power states to balance performance and energy efficiency. Because PSRAM access depends on the quad serial peripheral interface (QSPI) controller, you must coordinate the following elements:

• QSPI clocks

• Power-state transitions (PS4, PS3, PS2, and PS1)

• PSRAM self-refresh behavior

This section explains how PSRAM behaves across different power states and how to design low-power systems that rely on external memory.

Driver and Controller Dependencies#

The PSRAM driver uses the QSPI controller for all PSRAM read and write operations.

• In PS4 active and PS3 active, QSPI remains available and PSRAM is accessible.

• In PS4 sleep and PS3 sleep, PSRAM typically enters self-refresh to retain contents while QSPI and the CPU are idle.

• In PS2 active, PS2 sleep, and PS1 retention states, PSRAM is not accessible and usually requires reinitialization after transitioning to hight power states (PS4 and PS3 active).

PSRAM Power States#

Note: The PSRAM driver must manage transitions between PS4/PS3 Active to PS4/PS3 sleep to ensure data integrity and resume operation seamlessly after wakeup.

Managing Low-Power Transitions#

1. Entering Low Power#

Before transitioning from PS4 or PS3 active to PS4 or PS3 sleep, complete the following steps:

• Finish all pending PSRAM read and write operations.

• Ensure that any direct memory access (DMA) transfers involving PSRAM have completed.

• If required by the PSRAM device, place it into self-refresh mode.

• Disable or gate the QSPI clock only after transactions are complete.

2. Exiting Low Power#

After waking from PS4 or PS3 sleep to PS4 or PS3 active:

• Re-enable the QSPI clock if it was gated.

• Call sl_si91x_psram_init() again if your design requires full reinitialization.

• Optionally run a short memory test (for example, pattern write/read) to verify retention.

Best Practices for Low-Power PSRAM Design#

1. Leverage Self-Refresh: Use PSRAM devices that support self-refresh to minimize firmware overhead.

2. Use Power-State APIs: Manage sleep transitions through WiseConnect Power Manager APIs.

3. Ensure Safe Clock Control: Disable QSPI after completing transactions.

4. Validate Retention Behavior: Confirm data retention time across power states via hardware validation.

5. Avoid Frequent Transitions: Minimize switching between deep-sleep and active modes to extend memory life.

6. Test Wake-up Scenarios: Simulate wakeup cycles to ensure the PSRAM reinitializes correctly without data loss.