I2C#

sl_i2c_clock_hlr_t#

sl_i2c_clock_hlr_t

Enumeration for I2C bus speed.

sl_i2c_direction_t#

sl_i2c_direction_t

Enumeration for I2C direction i.e., read/write.

sl_i2c_mode_t#

sl_i2c_mode_t

Enumeration for I2C mode i.e., leader/follower.

I2C_TypeDef#

typedef I2C0_Type I2C_TypeDef

Renaming the I2C register set.

sl_si91x_i2c_init#

void sl_si91x_i2c_init (I2C_TypeDef * i2c, const sl_i2c_init_params_t * p_config)

Initialize the I2C i.e., set the parameters to the respective registers.

It needs to be called at the beginning of the code. It sets the frequency as per the input given in freq_scl and chlr. It accepts the following members for initialization parameters:

• mode (Leader/Follower) sl_i2c_mode_t.

• freq_scl (I2C SCL frequency).

• chlr (Bus Speed) sl_i2c_clock_hlr_t.

• address (Follower address).

• is_10bit_addr (pass true if address is of 10 bit).

Returns

• none

sl_si91x_i2c_reset#

void sl_si91x_i2c_reset (I2C_TypeDef * i2c)

Reset the I2C peripheral.

It resets the initialization parameters to zero and clears all the interrupts. It resets the target and slave addresses.

Returns

• none

sl_si91x_i2c_tx#

void sl_si91x_i2c_tx (I2C_TypeDef * i2c, uint8_t data)

Transmit one byte on SDA line.

Threshold needs to be set before calling this API sl_si91x_i2c_set_tx_threshold. Direction needs to be selected before calling this API sl_si91x_i2c_control_direction.

• sl_si91x_i2c_init(); sl_si91x_i2c_set_tx_threshold(); sl_si91x_i2c_control_direction(); sl_si91x_i2c_enable();

Returns

• none

sl_si91x_i2c_rx#

uint8_t sl_si91x_i2c_rx (I2C_TypeDef * i2c)

Receive one byte on SDA line.

Threshold needs to be set before calling this API sl_si91x_i2c_set_rx_threshold. Direction needs to be selected before calling this API sl_si91x_i2c_control_direction.

• sl_si91x_i2c_init(); sl_si91x_i2c_set_rx_threshold(); sl_si91x_i2c_control_direction(); sl_si91x_i2c_enable();

Returns

• data (uint8_t) Data that is received on the I2C bus.

sl_si91x_i2c_set_frequency#

void sl_si91x_i2c_set_frequency (I2C_TypeDef * i2c, uint32_t ref_freq, uint32_t freq_scl, sl_i2c_clock_hlr_t clhr)

Configure the frequency of the I2C transmission.

This API is called inside sl_si91x_i2c_init, but can be called separately to change the frequency. According the input of freq_scl frequency is calculated and filled in the register appropriately as the speed selected in chlr. The accepted parameters for chlr are: sl_i2c_clock_hlr_t.

• SL_I2C_STANDARD_BUS_SPEED = 1, ///< Standard bus speed, 100 Kbps

• SL_I2C_FAST_BUS_SPEED, ///< Fast bus speed, 400 Kbps

• SL_I2C_FAST_PLUS_BUS_SPEED, ///< Fast plus bus speed, 1 Mbps

• SL_I2C_HIGH_BUS_SPEED, ///< High bus speed, 3.4 Mbps

Returns

• none

sl_si91x_i2c_get_frequency#

uint32_t sl_si91x_i2c_get_frequency (I2C_TypeDef * i2c)

Fetch the frequency of I2C peripheral clock.

It returns uint32_t value of the SystemCoreClock frequency.

Returns

• frequency (uint32_t) The frequency of the System.

sl_si91x_i2c_get_version#

sl_i2c_version_t sl_si91x_i2c_get_version (void )

Get the release, sqa and dev version of I2C.

Returns

• (sl_i2c_version_t) type structure

sl_si91x_i2c_enable#

__STATIC_INLINE void sl_si91x_i2c_enable (I2C_TypeDef * i2c)

Enable the I2C interface.

It sets the register bit which enabled the I2C interface.

• sl_si91x_i2c_init();

Returns

• none

sl_si91x_i2c_disable#

__STATIC_INLINE void sl_si91x_i2c_disable (I2C_TypeDef * i2c)

Disable the I2C interface.

It clears the register bit which enabled the I2C interface.

• sl_si91x_i2c_enable();

Returns

• none

sl_si91x_i2c_start_cmd#

__STATIC_INLINE void sl_si91x_i2c_start_cmd (I2C_TypeDef * i2c)

Hold the SCL line low and stalls the leader until new command is available in TX FIFO.

STOP condition is not issued after completion of transfer irrespective of TX FIFO status.

• sl_si91x_i2c_enable();

Returns

• none

sl_si91x_i2c_stop_cmd#

__STATIC_INLINE void sl_si91x_i2c_stop_cmd (I2C_TypeDef * i2c)

Issue the STOP after completion of transfer irrespective of TX FIFO status.

If TX FIFO has data, leader sends start byte and starts the transmission.

• sl_si91x_i2c_enable(); sl_si91x_i2c_start_cmd();

Returns

• none

sl_si91x_i2c_get_status#

__STATIC_INLINE uint32_t sl_si91x_i2c_get_status (I2C_TypeDef * i2c)

Get the I2C IC status.

The bits of status are set according to the events. The macros are written in this file that can be directly used to mask the value of this register.

• sl_si91x_i2c_enable();

Returns

• none

sl_si91x_i2c_disable_interrupts#

__STATIC_INLINE void sl_si91x_i2c_disable_interrupts (I2C_TypeDef * i2c, uint32_t flags)

Disable the I2C interrupts.

It is mandatory to disable interrupts before configuring the I2C parameters.

• sl_si91x_i2c_enable_interrupts

Returns

• none

sl_si91x_i2c_enable_interrupts#

__STATIC_INLINE void sl_si91x_i2c_enable_interrupts (I2C_TypeDef * i2c, uint32_t flags)

Enable the I2C interrupts.

Returns

• none

sl_si91x_i2c_set_interrupts#

__STATIC_INLINE void sl_si91x_i2c_set_interrupts (I2C_TypeDef * i2c, uint32_t flags)

Set the interrupts i.e., unmask according to the flags passed in the parameter.

• sl_si91x_i2c_disable_interrupts();

Returns

• none

sl_si91x_i2c_clear_interrupts#

__STATIC_INLINE void sl_si91x_i2c_clear_interrupts (I2C_TypeDef * i2c, uint32_t flags)

Clear the interrupts i.e., mask according to the flags passed in the parameter.

• sl_si91x_i2c_disable_interrupts(); sl_si91x_i2c_set_interrupts();

Returns

• none

sl_si91x_i2c_get_pending_interrupts#

__STATIC_INLINE uint32_t sl_si91x_i2c_get_pending_interrupts (I2C_TypeDef * i2c)

Get the pending interrupts.

It returns the uint32_t type interrupt status register. The macros are written in this file that can be directly used to mask the value of this register.

• sl_si91x_i2c_enable_interrupts();

Returns

• status (uint32_t) Interrupts which are pending.

sl_si91x_i2c_get_enabled_interrupts#

__STATIC_INLINE uint32_t sl_si91x_i2c_get_enabled_interrupts (I2C_TypeDef * i2c)

Get the enabled interrupts.

It returns the uint32_t type interrupt mask register. The macros are written in this file that can be directly used to mask the value of this register.

• sl_si91x_i2c_set_interrupts();

Returns

• status (uint32_t) Interrupts which are unmasked.

sl_si91x_i2c_get_enabled_pending_interrupts#

__STATIC_INLINE uint32_t sl_si91x_i2c_get_enabled_pending_interrupts (I2C_TypeDef * i2c)

Get the enabled and pending interrupts.

It returns the uint32_t type value which is bitwise end of enabled interrupts and pending interrupts. The macros are written in this file that can be directly used to mask the value of this register.

• sl_si91x_i2c_set_interrupts(); sl_si91x_i2c_enable_interrupts();

Returns

• status (uint32_t) Interrupts which are unmasked and pending.

sl_si91x_i2c_wait_ready#

__STATIC_INLINE void sl_si91x_i2c_wait_ready (I2C_TypeDef * i2c, uint32_t mask)

Wait till the process is completed.

Mask takes the interrupt flags and waits until it is triggered. Interrupt is cleared once it is triggered.

Returns

• none

sl_si91x_i2c_wait_sync#

__STATIC_INLINE void sl_si91x_i2c_wait_sync (I2C_TypeDef * i2c)

Wait till the synchronization is completed.

It checks whether the I2C interface is enabled and the bus is free i.e., no activity is pending on the bus.

Returns

• none

sl_si91x_i2c_set_follower_address#

__STATIC_INLINE void sl_si91x_i2c_set_follower_address (I2C_TypeDef * i2c, uint16_t addr, bool is_10bit_addr)

Set the follower address when I2C is in leader mode.

It validates the is_10bit_addr parameter and sets the 10 bit address register. It updates the register of follower address with the value passed in the parameter. This API is called in sl_si91x_i2c_init function sl_si91x_i2c_init It can also be called separately from to update the follower address.

Returns

• none

sl_si91x_i2c_get_follower_address#

__STATIC_INLINE uint16_t sl_si91x_i2c_get_follower_address (I2C_TypeDef * i2c)

Fetch the current follower address.

It returns uint8_t value as the current follower address.

• sl_si91x_i2c_set_follower_address();

Returns

• address(uint8_t) address of the follower.

sl_si91x_i2c_set_follower_mask_address#

__STATIC_INLINE void sl_si91x_i2c_set_follower_mask_address (I2C_TypeDef * i2c, uint16_t mask)

Update the address of leader when it is in follower mode.

It updates the register of follower address with the value passed in the parameter. This API is called in sl_si91x_i2c_init function sl_si91x_i2c_init It can also be called separately from to update the address.

Returns

• none

sl_si91x_i2c_get_follower_mask_address#

__STATIC_INLINE uint16_t sl_si91x_i2c_get_follower_mask_address (I2C_TypeDef * i2c)

Fetch the masked follower address i.e.

leader address when it is in follower mode. It returns uint8_t value as the current masked follower address.

• sl_si91x_i2c_set_follower_mask_address();

Returns

• address(uint8_t) leader's address when it is in follower mode

sl_si91x_i2c_send_nack#

__STATIC_INLINE void sl_si91x_i2c_send_nack (I2C_TypeDef * i2c)

Generate NACK only when it is in follower-receiver mode.

It generates NACK after a byte is received and the transfer will be aborted.

• sl_si91x_i2c_enable(); sl_si91x_i2c_inti();

Returns

• none

sl_si91x_i2c_abort_transfer#

__STATIC_INLINE void sl_si91x_i2c_abort_transfer (I2C_TypeDef * i2c)

Abort the transfer.

It disables the interrupts, I2C interface and waits till the abort is completed. Abort issues the stop condition and flushes the TX FIFO and sets the SL_I2C_EVENT_TRANSMIT_ABORT interrupt after the operation is completed. For abort it is necessary to keep to I2C instance in enable mode.

• sl_si91x_i2c_enable();

Returns

• none

sl_si91x_i2c_clear_bus#

__STATIC_INLINE void sl_si91x_i2c_clear_bus (I2C_TypeDef * i2c)

Clear the I2C bus.

It disables the I2C interface, loads the SCL and SDA timeout values and again enabled the I2C interface.

• sl_si91x_i2c_enable();

Returns

• none

sl_si91x_i2c_set_rx_threshold#

__STATIC_INLINE void sl_si91x_i2c_set_rx_threshold (I2C_TypeDef * i2c, uint8_t threshold)

Update the RX threshold values.

• sl_si91x_i2c_disable();

Returns

• none

sl_si91x_i2c_set_tx_threshold#

__STATIC_INLINE void sl_si91x_i2c_set_tx_threshold (I2C_TypeDef * i2c, uint8_t threshold)

Update the TX threshold values.

• sl_si91x_i2c_disable();

Returns

• none

sl_si91x_i2c_control_direction#

__STATIC_INLINE void sl_si91x_i2c_control_direction (I2C_TypeDef * i2c, sl_i2c_direction_t direction)

Control the direction of the I2C interface.

It updates the register with the read mask / write mask value sl_i2c_direction_t

• sl_si91x_i2c_enable();

Note

• I2C instance should be enabled before calling this API.

Returns

• none

sl_si91x_i2c_set_sda_hold_time#

__STATIC_INLINE void sl_si91x_i2c_set_sda_hold_time (I2C_TypeDef * i2c, sl_i2c_direction_t direction, uint32_t time)

Configure the SDA hold time.

According to the direction sl_i2c_direction_t, it updates the registers with the time value which is passed as the function parameter. It holds the SDA in the units of clock period.

Returns

• none

sl_si91x_i2c_send_ack#

__STATIC_INLINE void sl_si91x_i2c_send_ack (I2C_TypeDef * i2c, p_config)

Returns

• none

SL_I2C_ASSERT#

#define SL_I2C_ASSERT

(expr)

Macro function to assert the I2C instance.

I2C_NUM#

#define I2C_NUM

(ref)

Macro to validate I2C instance number.

I2C_REF_VALID#

#define I2C_REF_VALID

(ref)

Macro function to validate the user input and I2C instance.

UNUSED_VARIABLE#

#define UNUSED_VARIABLE

(var)

SL_I2C_ENABLE_MASK#

#define SL_I2C_ENABLE_MASK

0x01

I2C enable mask.

SL_I2C_WRITE_MASK#

#define SL_I2C_WRITE_MASK

0x00

I2C write mask.

SL_I2C_READ_MASK#

#define SL_I2C_READ_MASK

0x01

I2C read mask.

SL_I2C_CLEAR_MASK#

#define SL_I2C_CLEAR_MASK

0x00

I2C clear mask.

SL_I2C_SCL_STUCK_TIMEOUT#

#define SL_I2C_SCL_STUCK_TIMEOUT

20

SCL stuck timeout, used to clear the I2C bus.

SL_I2C_SDA_STUCK_TIMEOUT#

#define SL_I2C_SDA_STUCK_TIMEOUT

20

SDA stick timeout, used to clear the I2C bus.

SL_16_BIT_MASK#

#define SL_16_BIT_MASK

0xFFFF

16 bit mask value

SL_8_BIT_MASK#

#define SL_8_BIT_MASK

0xFF

8 bit mask value

SL_4_BIT_MASK#

#define SL_4_BIT_MASK

0xF

4 bit mask value

SL_I2C_DMA_ENABLE#

#define SL_I2C_DMA_ENABLE

0x1

DMA enable.

SL_I2C_DMA_DISABLE#

#define SL_I2C_DMA_DISABLE

0x0

DMA disable.

SL_I2C_EVENT_RECEIVE_UNDER#

#define SL_I2C_EVENT_RECEIVE_UNDER

(1UL << 0)

If processor attempts to read receive buffer when buffer is empty.

SL_I2C_EVENT_RECEIVE_OVER#

#define SL_I2C_EVENT_RECEIVE_OVER

  (1UL << 1)

If receive buffer is full and another byte is received (extra bytes are lost)

SL_I2C_EVENT_RECEIVE_FULL#

#define SL_I2C_EVENT_RECEIVE_FULL

(1UL << 2)

When receive buffer is full up to the RX_TL threshold level.

SL_I2C_EVENT_TRANSMIT_OVER#

#define SL_I2C_EVENT_TRANSMIT_OVER

(1UL << 3)

If transmit buffer is full and user attempts to transmit another byte.

SL_I2C_EVENT_TRANSMIT_EMPTY#

#define SL_I2C_EVENT_TRANSMIT_EMPTY

(1UL << 4)

When transmit buffer is filled over the TX_TL threshold level.

SL_I2C_EVENT_READ_REQ#

#define SL_I2C_EVENT_READ_REQ

(1UL << 5)

SCL is on hold in follower mode when another leader attempts to read data.

SL_I2C_EVENT_TRANSMIT_ABORT#

#define SL_I2C_EVENT_TRANSMIT_ABORT

  (1UL << 6)

Transmit is aborted, to validate the reason, read IC_TX_ABRT_SOURCE register.

SL_I2C_EVENT_RECEIVE_DONE#

#define SL_I2C_EVENT_RECEIVE_DONE

(1UL << 7)

In follower mode if leader does not acknowledge, happens on last byte.

SL_I2C_EVENT_ACTIVITY_ON_BUS#

#define SL_I2C_EVENT_ACTIVITY_ON_BUS

  (1UL << 8)

Ongoing or previous activity was there on bus, to clear read IC_CLR_INTR / IC_CLR_ACTIVITY register.

SL_I2C_EVENT_STOP_DETECT#

#define SL_I2C_EVENT_STOP_DETECT

(1UL << 9)

Stop condition is detected on the bus (leader and follower both mode)

SL_I2C_EVENT_START_DETECT#

#define SL_I2C_EVENT_START_DETECT

  (1UL << 10)

Start or Restart condition is detected on the bus (leader and follower both mode)

SL_I2C_EVENT_GENERAL_CALL#

#define SL_I2C_EVENT_GENERAL_CALL

  (1UL << 11)

General call address is received, to clear read IC_CLR_GEN_CALL register.

SL_I2C_EVENT_RESTART_DET#

#define SL_I2C_EVENT_RESTART_DET

(1UL << 12)

Restart condition is detected on bus (follower mode)

SL_I2C_EVENT_MST_ON_HOLD#

#define SL_I2C_EVENT_MST_ON_HOLD

(1UL << 13)

Leader is holding the bus and FIFO is empty.

SL_I2C_EVENT_SCL_STUCK_AT_LOW#

#define SL_I2C_EVENT_SCL_STUCK_AT_LOW

(1UL << 14)

SCL line is stuck at low.

SL_I2C_ABORT_7B_ADDRESS_NOACK#

#define SL_I2C_ABORT_7B_ADDRESS_NOACK

(1UL << 0)

Address sent was not acknowledged by follower in 7-bit mode.

SL_I2C_ABORT_10B_ADDRESS1_NOACK#

#define SL_I2C_ABORT_10B_ADDRESS1_NOACK

(1UL << 1)

First 10-bit address byte sent was not acknowledged by follower.

SL_I2C_ABORT_10B_ADDRESS2_NOACK#

#define SL_I2C_ABORT_10B_ADDRESS2_NOACK

(1UL << 2)

Second 10-bit address byte sent was not acknowledged by follower.

SL_I2C_ABORT_TX_DATA_NOACK#

#define SL_I2C_ABORT_TX_DATA_NOACK

  (1UL << 3)

Received acknowledgement for address bu did not receive acknowledgement for data.

SL_I2C_ABORT_GENERAL_CALL_NOACK#

#define SL_I2C_ABORT_GENERAL_CALL_NOACK

(1UL << 4)

No follower acknowledged General call.

SL_I2C_ABORT_GENERAL_CALL_READ#

#define SL_I2C_ABORT_GENERAL_CALL_READ

(1UL << 5)

Leader send general call but program was to read it from bus.

SL_I2C_ABORT_HIGH_SPEED_ACK#

#define SL_I2C_ABORT_HIGH_SPEED_ACK

(1UL << 6)

High speed leader call was acknowledged by follower.

SL_I2C_ABORT_START_BYTE_ACK#

#define SL_I2C_ABORT_START_BYTE_ACK

(1UL << 7)

Start byte was acknowledged by follower.

SL_I2C_ABORT_HIGH_SPEED_NO_RESTART#

#define SL_I2C_ABORT_HIGH_SPEED_NO_RESTART

(1UL << 8)

Restart is disabled and data transfer is in high speed mode.

SL_I2C_ABORT_START_BYTE_NO_RESTART#

#define SL_I2C_ABORT_START_BYTE_NO_RESTART

(1UL << 9)

Restart is disabled and user tries to send start byte.

SL_I2C_ABORT_10B_READ_NO_RESTART#

#define SL_I2C_ABORT_10B_READ_NO_RESTART

  (1UL << 10)

Restart is disabled and 10-bit address read command is received.

SL_I2C_ABORT_MASTER_DISABLED#

#define SL_I2C_ABORT_MASTER_DISABLED

(1UL << 11)

Leader mode is disabled and leader mode operation is preformed.

SL_I2C_ABORT_MASTER_ARBITRATION_LOST#

#define SL_I2C_ABORT_MASTER_ARBITRATION_LOST

(1UL << 12)

Leader has lost arbitration.

SL_I2C_ABORT_SLAVE_FLUSH_TX_FIFO#

#define SL_I2C_ABORT_SLAVE_FLUSH_TX_FIFO

(1UL << 13)

Follower flushes old TX FIFO to respond new read command.

SL_I2C_ABORT_SLAVE_ARBITRATION_LOST#

#define SL_I2C_ABORT_SLAVE_ARBITRATION_LOST

(1UL << 14)

Follower lost the bus.

SL_I2C_ABORT_SLAVE_READ_INTX#

#define SL_I2C_ABORT_SLAVE_READ_INTX

(1UL << 15)

Follower requests for data and user writes 1 in CMD register.

SL_I2C_ABORT_USER_ABORT#

#define SL_I2C_ABORT_USER_ABORT

(1UL << 16)

Leader has detected transfer abort.

SL_I2C_ABORT_SDA_STUCK_AT_LOW#

#define SL_I2C_ABORT_SDA_STUCK_AT_LOW

(1UL << 17)

SDA is stuck at low.

SL_I2C_ABORT_DEVICE_NOACK#

#define SL_I2C_ABORT_DEVICE_NOACK

(1UL << 18)

No acknowledgement for Device ID transfer by leader.

SL_I2C_ABORT_DEVICE_SLAVE_ADDRESS_NOACK#

#define SL_I2C_ABORT_DEVICE_SLAVE_ADDRESS_NOACK

(1UL << 19)

No acknowledgement for follower address to leader.

SL_I2C_ABORT_WRITE#

#define SL_I2C_ABORT_WRITE

(1UL << 20)

Leader sends device ID transfer and TX FIFO has write command.

SL_I2C_ACTIVITY_STATUS#

#define SL_I2C_ACTIVITY_STATUS

(1U << 0)

'OR' of Leader and Follower activity

SL_I2C_TRANSFER_FIFO_NOT_FULL_STATUS#

#define SL_I2C_TRANSFER_FIFO_NOT_FULL_STATUS

(1U << 1)

Transmit FIFO is not full.

SL_I2C_TRANSFER_FIFO_EMPTY_STATUS#

#define SL_I2C_TRANSFER_FIFO_EMPTY_STATUS

(1U << 2)

Transmit FIFO is completely empty.

SL_I2C_RECEIVE_FIFO_NOT_EMPTY_STATUS#

#define SL_I2C_RECEIVE_FIFO_NOT_EMPTY_STATUS

(1U << 3)

Receive FIFO is not empty.

SL_I2C_RECEIVE_FIFO_FULL_STATUS#

#define SL_I2C_RECEIVE_FIFO_FULL_STATUS

(1U << 4)

Receive FIFO is completely full.

SL_I2C_MASTER_ACTIVITY_STATUS#

#define SL_I2C_MASTER_ACTIVITY_STATUS

(1U << 5)

Leader is not in idle state.

SL_I2C_SLAVE_ACTIVITY_STATUS#

#define SL_I2C_SLAVE_ACTIVITY_STATUS

(1U << 6)

Follower is not in idle state.

SL_I2C_MASTER_HOLD_TX_FIFO_EMPTY_STATUS#

#define SL_I2C_MASTER_HOLD_TX_FIFO_EMPTY_STATUS

  (1U << 7)

Leader holds SCL as previous command did not have a STOP bit.

SL_I2C_MASTER_HOLD_RX_FIFO_FULL_STATUS#

#define SL_I2C_MASTER_HOLD_RX_FIFO_FULL_STATUS

  (1U << 8)

Leader holds SCL as RX FIFO is full and additional byte is received.

SL_I2C_SLAVE_HOLD_TX_FIFO_EMPTY_STATUS#

#define SL_I2C_SLAVE_HOLD_TX_FIFO_EMPTY_STATUS

  (1U << 9)

Follower holds SCL to request read data when TX FIFO is empty.

SL_I2C_SLAVE_HOLD_RX_FIFO_FULL_STATUS#

#define SL_I2C_SLAVE_HOLD_RX_FIFO_FULL_STATUS

  (1U << 10)

Follower holds SCL as RX FIFO is full and additional byte is received.

SL_I2C_SDA_STUCK_NOT_RECOVERED_STATUS#

#define SL_I2C_SDA_STUCK_NOT_RECOVERED_STATUS

(1U << 11)

SDA is stuck at low and has not recovered.