Extended Custom Feature Bitmap#

SL_SI91X_EXT_FEAT_RSA_KEY_WITH_4096_SUPPORT#

#define SL_SI91X_EXT_FEAT_RSA_KEY_WITH_4096_SUPPORT

BIT(1)

To support 4096 size RSA KEY certificate.

SL_SI91X_EXT_FEAT_SSL_CERT_WITH_4096_KEY_SUPPORT#

#define SL_SI91X_EXT_FEAT_SSL_CERT_WITH_4096_KEY_SUPPORT

BIT(3)

To support 4096 size KEY SSL certificate.

Note

• Bit 2 is reserved

SL_SI91X_EXT_FEAT_AP_BROADCAST_PKT_SND_B4_DTIM#

#define SL_SI91X_EXT_FEAT_AP_BROADCAST_PKT_SND_B4_DTIM

BIT(4)

Extended custom bitmap for AP Broadcast customization.

Note

• If this bit is enable then connected client who is in power save may miss the packet.

SL_SI91X_EXT_FEAT_FCC_LOW_PWR#

#define SL_SI91X_EXT_FEAT_FCC_LOW_PWR

BIT(5)

Extended custom bitmap to support FCC.

SL_SI91X_EXT_FEAT_PUF#

#define SL_SI91X_EXT_FEAT_PUF

BIT(7)

To enable PUF.

SL_SI91X_EXT_FEAT_SPECTRAL_MASK_NOKIA#

#define SL_SI91X_EXT_FEAT_SPECTRAL_MASK_NOKIA

BIT(8)

Nokia Spectral mask extended custom bitmap.

SL_SI91X_EXT_HTTP_SKIP_DEFAULT_LEADING_CHARACTER#

#define SL_SI91X_EXT_HTTP_SKIP_DEFAULT_LEADING_CHARACTER

BIT(9)

Extended feature bit map to skip default leading character '\' in HTTP header.

SL_SI91X_EXT_FEAT_PUF_PRIVATE_KEY#

#define SL_SI91X_EXT_FEAT_PUF_PRIVATE_KEY

BIT(10)

To enable PUF private key.

SL_SI91X_EXT_FEAT_ENABLE_11R_OTA#

#define SL_SI91X_EXT_FEAT_ENABLE_11R_OTA

BIT(11)

To enable 802.11R Over The Air Roaming.

Note

• Resource Request Support is not Present

• If both BIT[11] and BIT[16] are not enabled then it will select as Legacy Roaming.

SL_SI91X_EXT_FEAT_IEEE_80211J#

#define SL_SI91X_EXT_FEAT_IEEE_80211J

BIT(12)

To enable 802.11J protocol.

Note

• If this bit is enable, set region command is mandatory with setting it to Japan region and band value must be 1 (5GHz).

SL_SI91X_EXT_FEAT_IEEE_80211W#

#define SL_SI91X_EXT_FEAT_IEEE_80211W

BIT(13)

To enable 802.11W protocol.

Note

• This bit must be set for enabling WPA3 Personal Mode and WPA3 Personal Transition mode.

SL_SI91X_EXT_FEAT_SSL_VERSIONS_SUPPORT#

#define SL_SI91X_EXT_FEAT_SSL_VERSIONS_SUPPORT

BIT(14)

To enable the Multi-version TCP over SSL support.

SL_SI91X_EXT_FEAT_16th_STATION_IN_AP_MODE#

#define SL_SI91X_EXT_FEAT_16th_STATION_IN_AP_MODE

BIT(15)

To Enable 16 client support.

Note

• If this bit is enable then 16 stations can connect in AP mode otherwise Maximum of 8 stations can connect.

SL_SI91X_EXT_FEAT_ENABLE_11R_ODS#

#define SL_SI91X_EXT_FEAT_ENABLE_11R_ODS

BIT(16)

To enable 802.11R Over the Distribution System Roaming.

Note

• 1. Resource Request Support is not Present. 2. If both BIT[11] and BIT[16] are not enabled then it will select as Legacy Roaming.

SL_SI91X_EXT_FEAT_WOWLAN_DISABLE#

#define SL_SI91X_EXT_FEAT_WOWLAN_DISABLE

BIT(17)

To disable WoWLAN feature.

SL_SI91X_EXT_FEAT_LOW_POWER_MODE#

#define SL_SI91X_EXT_FEAT_LOW_POWER_MODE

BIT(19)

To enable low power mode in Wlan.

Note

• Bit 18 is reserved

• EXT_FEAT_LOW_POWER_MODE is not supported for 1.3 version chipset.

SL_SI91X_EXT_FEAT_352K_M4SS_320K#

#define SL_SI91X_EXT_FEAT_352K_M4SS_320K

0

To enable 352K memory for NWP and 320K memory for M4.

To enable 352K memory for NWP (For NCP mode ONLY, to be deprecated soon)

SL_SI91X_EXT_FEAT_352K_M4SS_320K#

#define SL_SI91X_EXT_FEAT_352K_M4SS_320K

SL_SI91X_EXT_FEAT_352K

To enable 352K memory for NWP and 320K memory for M4.

To enable 352K memory for NWP (For NCP mode ONLY, to be deprecated soon)

SL_SI91X_RAM_LEVEL_NWP_BASIC_MCU_ADV#

#define SL_SI91X_RAM_LEVEL_NWP_BASIC_MCU_ADV

SL_SI91X_EXT_FEAT_352K_M4SS_320K

To enable basic NWP and advance MCU RAM level configuration.

To enable basic NWP RAM level configuration (For NCP mode ONLY, to be deprecated soon)

SL_SI91X_RAM_LEVEL_NWP_BASIC_MCU_ADV#

#define SL_SI91X_RAM_LEVEL_NWP_BASIC_MCU_ADV

SL_SI91X_EXT_FEAT_352K

To enable basic NWP and advance MCU RAM level configuration.

To enable basic NWP RAM level configuration (For NCP mode ONLY, to be deprecated soon)

SL_SI91X_EXT_FEAT_416K_M4SS_256K#

#define SL_SI91X_EXT_FEAT_416K_M4SS_256K

BIT(21)

To enable 416K memory for NWP and 256K memory for M4.

SL_SI91X_RAM_LEVEL_NWP_MEDIUM_MCU_MEDIUM#

#define SL_SI91X_RAM_LEVEL_NWP_MEDIUM_MCU_MEDIUM

SL_SI91X_EXT_FEAT_416K_M4SS_256K

To enable medium NWP and medium MCU RAM level configuration.

SL_SI91X_RAM_LEVEL_NWP_MEDIUM_MCU_MEDIUM#

#define SL_SI91X_RAM_LEVEL_NWP_MEDIUM_MCU_MEDIUM

SL_SI91X_EXT_FEAT_256K_MODE

To enable medium NWP and medium MCU RAM level configuration.

SL_SI91X_EXT_FEAT_480K_M4SS_192K#

#define SL_SI91X_EXT_FEAT_480K_M4SS_192K

BIT(20)

To enable 480K memory for NWP and 192K memory for M4.

SL_SI91X_RAM_LEVEL_NWP_ADV_MCU_BASIC#

#define SL_SI91X_RAM_LEVEL_NWP_ADV_MCU_BASIC

SL_SI91X_EXT_FEAT_480K_M4SS_192K

To enable advance NWP and basic MCU RAM level configuration.

SL_SI91X_RAM_LEVEL_NWP_ADV_MCU_BASIC#

#define SL_SI91X_RAM_LEVEL_NWP_ADV_MCU_BASIC

SL_SI91X_EXT_FEAT_320K_MODE

To enable advance NWP and basic MCU RAM level configuration.

SL_SI91X_EXT_FEAT_352K#

#define SL_SI91X_EXT_FEAT_352K

0

To enable 352K memory for NWP.

SL_SI91X_RAM_LEVEL_NWP_BASIC#

#define SL_SI91X_RAM_LEVEL_NWP_BASIC

SL_SI91X_EXT_FEAT_352K

To enable basic NWP RAM level configuration.

SL_SI91X_EXT_FEAT_672K#

#define SL_SI91X_EXT_FEAT_672K

(BIT(20) | BIT(21))

To enable 672K memory for NWP.

SL_SI91X_RAM_LEVEL_NWP_ALL_AVAILABLE#

#define SL_SI91X_RAM_LEVEL_NWP_ALL_AVAILABLE

SL_SI91X_EXT_FEAT_672K

To enable full NWP RAM level configuration.

SL_SI91X_RAM_LEVEL_NWP_ALL_AVAILABLE#

#define SL_SI91X_RAM_LEVEL_NWP_ALL_AVAILABLE

SL_SI91X_RAM_LEVEL_NWP_ALL_MCU_ZERO

To enable full NWP RAM level configuration.

SL_SI91X_EXT_FEAT_672K_M4SS_0K#

#define SL_SI91X_EXT_FEAT_672K_M4SS_0K

SL_SI91X_EXT_FEAT_672K

To enable 672K memory for NWP and 0K memory for M4 (For NCP mode ONLY, to be deprecated soon)

SL_SI91X_RAM_LEVEL_NWP_ALL_MCU_ZERO#

#define SL_SI91X_RAM_LEVEL_NWP_ALL_MCU_ZERO

SL_SI91X_EXT_FEAT_672K

To enable full NWP RAM level configuration (For NCP mode ONLY, to be deprecated soon)

SL_SI91X_RAM_LEVEL_NWP_ALL_MCU_ZERO#

#define SL_SI91X_RAM_LEVEL_NWP_ALL_MCU_ZERO

SL_SI91X_EXT_FEAT_384K_MODE

To enable full NWP RAM level configuration (For NCP mode ONLY, to be deprecated soon)

SL_SI91X_EXT_FEAT_XTAL_CLK_ENABLE#

#define SL_SI91X_EXT_FEAT_XTAL_CLK_ENABLE

(xtal_clk_enable)

To enable crystal clock for TA.

Based on sleep clock source selection, User can choose one of the following

Note

• For 917 V2 radio boards set SL_SI91X_EXT_FEAT_XTAL_CLK_ENABLE to 1, for other variants 2 is recommended

SL_SI91X_EXT_FEAT_XTAL_CLK#

#define SL_SI91X_EXT_FEAT_XTAL_CLK

SL_SI91X_EXT_FEAT_XTAL_CLK_ENABLE(2)

SL_SI91X_EXT_FEAT_HOMEKIT_WAC_ENABLED#

#define SL_SI91X_EXT_FEAT_HOMEKIT_WAC_ENABLED

BIT(24)

To intimate FW not to modify MDNS text record.

SL_SI91X_EXT_FEAT_1P8V_SUPPORT#

#define SL_SI91X_EXT_FEAT_1P8V_SUPPORT

BIT(25)

To enable 1.8v support for TA.

SL_SI91X_EXT_FEAT_UART_SEL_FOR_DEBUG_PRINTS#

#define SL_SI91X_EXT_FEAT_UART_SEL_FOR_DEBUG_PRINTS

BIT(27)

To select UART debug prints pin selection If BIT(27) is enabled,Debug prints are supported on UART1 If BIT(27) is disabled,Debug prints are supported on UART2.

Note

• Bit 26 is reserved

• By default all the debug prints from device network processor will be coming on UART2 if this bit is not enabled. UART1 pins are mapped to the following pins w.r.t to the device network processor. User needs to ensure that these pins are not used in MCU applications in SoC mode to avoid conflicts of pins usage based on the requirement. This bit is valid only if BIT[28] in ext_custom_feature_bit_map is set to 0. UART1-TX: GPIO_9 UART1-RX: GPIO_8 UART2-TX: GPIO_6 UART2-RX: GPIO_10 There is no functionality on rx pins for debug prints.

SL_SI91X_EXT_FEAT_DISABLE_DEBUG_PRINTS#

#define SL_SI91X_EXT_FEAT_DISABLE_DEBUG_PRINTS

BIT(28)

If this bit is enabled,NWP disables Debug prints support.

SL_SI91X_EXT_FEAT_FRONT_END_SWITCH_PINS_ULP_GPIO_4_5_0#

#define SL_SI91X_EXT_FEAT_FRONT_END_SWITCH_PINS_ULP_GPIO_4_5_0

BIT(29)

To Configure Frontend with selection BIT[30:29].

For 917B0

Note

• SiWx917 has an integrated on-chip transmit/receive (T/R) switch. This Internal RF Switch configuration uses internal logic present in the IC, and GPIOs are not needed. RF_BLE_TX (8dbm) mode is not supported in this configuration.

• VC1, VC2 and VC3 are control voltage pins of RF Switch

SL_SI91X_EXT_FEAT_FRONT_END_INTERNAL_SWITCH#

#define SL_SI91X_EXT_FEAT_FRONT_END_INTERNAL_SWITCH

BIT(30)

SL_SI91X_EXT_FEAT_BT_CUSTOM_FEAT_ENABLE#

#define SL_SI91X_EXT_FEAT_BT_CUSTOM_FEAT_ENABLE

BIT(31)

Enable BT Custom Features.