Structure to hold the clock configuration members for the GSPI peripheral.

This structure contains the clock configuration members for the GSPI peripheral, including SoC PLL count value, interface PLL control value, clock frequencies, and division factor.

Public Attributes#

uint8_t

SoC PLL count value.

uint16_t

Interface PLL control value.

uint32_t

Interface PLL clock frequency.

uint32_t

Interface PLL reference clock frequency.

uint32_t

SoC PLL clock frequency.

uint32_t

SoC PLL reference clock frequency.

uint16_t

Clock division factor.

Public Attribute Documentation#

soc_pll_mm_count_value#

uint8_t sl_gspi_clock_config_t::soc_pll_mm_count_value

SoC PLL count value.


intf_pll_500_control_value#

uint16_t sl_gspi_clock_config_t::intf_pll_500_control_value

Interface PLL control value.


intf_pll_clock#

uint32_t sl_gspi_clock_config_t::intf_pll_clock

Interface PLL clock frequency.


intf_pll_reference_clock#

uint32_t sl_gspi_clock_config_t::intf_pll_reference_clock

Interface PLL reference clock frequency.


soc_pll_clock#

uint32_t sl_gspi_clock_config_t::soc_pll_clock

SoC PLL clock frequency.


soc_pll_reference_clock#

uint32_t sl_gspi_clock_config_t::soc_pll_reference_clock

SoC PLL reference clock frequency.


division_factor#

uint16_t sl_gspi_clock_config_t::division_factor

Clock division factor.