Structure to hold the parameters for the configuration of the SSI peripheral.
Public Attributes#
uint8_t
Bit width, 4 - 16 bits.
uint32_t
Mode such as Master or Slave mode.
uint32_t
Clock mode such as CPOL0 CPHA1.
uint32_t
Baud rate for SSI.
uint32_t
Delay for the receive input signal.
Public Attribute Documentation#
bit_width#
uint8_t sl_ssi_control_config_t::bit_width
Bit width, 4 - 16 bits.
Definition at line
136 of file components/device/silabs/si91x/mcu/drivers/unified_api/inc/sl_si91x_ssi.hdevice_mode#
uint32_t sl_ssi_control_config_t::device_mode
Mode such as Master or Slave mode.
Definition at line
137 of file components/device/silabs/si91x/mcu/drivers/unified_api/inc/sl_si91x_ssi.hclock_mode#
uint32_t sl_ssi_control_config_t::clock_mode
Clock mode such as CPOL0 CPHA1.
Definition at line
138 of file components/device/silabs/si91x/mcu/drivers/unified_api/inc/sl_si91x_ssi.hbaud_rate#
uint32_t sl_ssi_control_config_t::baud_rate
Baud rate for SSI.
Definition at line
139 of file components/device/silabs/si91x/mcu/drivers/unified_api/inc/sl_si91x_ssi.hreceive_sample_delay#
uint32_t sl_ssi_control_config_t::receive_sample_delay
Delay for the receive input signal.
Definition at line
140 of file components/device/silabs/si91x/mcu/drivers/unified_api/inc/sl_si91x_ssi.h