debug_run#

bool sl_hal_wdog_init_t::debug_run

Counter keeps running during debug halt.

clear_source#

bool sl_hal_wdog_init_t::clear_source

Select WDOG clear source: False: Write to the clear bit will clear the WDOG counter.

True: Rising edge on the PRS Source 0 will clear the WDOG counter.

em2_run#

bool sl_hal_wdog_init_t::em2_run

Counter keeps running when in EM2.

em3_run#

bool sl_hal_wdog_init_t::em3_run

Counter keeps running when in EM3.

em4_block#

bool sl_hal_wdog_init_t::em4_block

Block EMU from entering EM4.

prs0_missing_reset_enable#

bool sl_hal_wdog_init_t::prs0_missing_reset_enable

When set, a PRS Source 0 missing event will trigger a WDOG reset.

prs1_missing_reset_enable#

bool sl_hal_wdog_init_t::prs1_missing_reset_enable

When set, a PRS Source 1 missing event will trigger a WDOG reset.

lock#

bool sl_hal_wdog_init_t::lock

Block SW from modifying the configuration (a reset is needed to reconfigure).

period_select#

sl_hal_wdog_period_select_t sl_hal_wdog_init_t::period_select

Watchdog timeout period.

warning_time_select#

sl_hal_wdog_warning_timeout_select_t sl_hal_wdog_init_t::warning_time_select

Select warning time as % of the Watchdog timeout.

window_time_select#

sl_hal_wdog_illegal_window_select_t sl_hal_wdog_init_t::window_time_select

Select illegal window time as % of the Watchdog timeout.

reset_disable#

bool sl_hal_wdog_init_t::reset_disable

Disable Watchdog reset output if true.