|
#define
|
_CMU_ADCCTRL_ADC0CLKINV_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_ADCCTRL_ADC0CLKINV_MASK
0x100UL
|
|
#define
|
_CMU_ADCCTRL_ADC0CLKINV_SHIFT
8
|
|
#define
|
_CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO
0x00000001UL
|
|
#define
|
_CMU_ADCCTRL_ADC0CLKSEL_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_ADCCTRL_ADC0CLKSEL_DISABLED
0x00000000UL
|
|
#define
|
_CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK
0x00000003UL
|
|
#define
|
_CMU_ADCCTRL_ADC0CLKSEL_HFXO
0x00000002UL
|
|
#define
|
_CMU_ADCCTRL_ADC0CLKSEL_MASK
0x30UL
|
|
#define
|
_CMU_ADCCTRL_ADC0CLKSEL_SHIFT
4
|
|
#define
|
_CMU_ADCCTRL_MASK
0x00000130UL
|
|
#define
|
_CMU_ADCCTRL_RESETVALUE
0x00000000UL
|
|
#define
|
_CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_AUXHFRCOCTRL_CLKDIV_DIV1
0x00000000UL
|
|
#define
|
_CMU_AUXHFRCOCTRL_CLKDIV_DIV2
0x00000001UL
|
|
#define
|
_CMU_AUXHFRCOCTRL_CLKDIV_DIV4
0x00000002UL
|
|
#define
|
_CMU_AUXHFRCOCTRL_CLKDIV_MASK
0x6000000UL
|
|
#define
|
_CMU_AUXHFRCOCTRL_CLKDIV_SHIFT
25
|
|
#define
|
_CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT
0x00000002UL
|
|
#define
|
_CMU_AUXHFRCOCTRL_CMPBIAS_MASK
0xE00000UL
|
|
#define
|
_CMU_AUXHFRCOCTRL_CMPBIAS_SHIFT
21
|
|
#define
|
_CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT
0x0000001FUL
|
|
#define
|
_CMU_AUXHFRCOCTRL_FINETUNING_MASK
0x3F00UL
|
|
#define
|
_CMU_AUXHFRCOCTRL_FINETUNING_SHIFT
8
|
|
#define
|
_CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_AUXHFRCOCTRL_FINETUNINGEN_MASK
0x8000000UL
|
|
#define
|
_CMU_AUXHFRCOCTRL_FINETUNINGEN_SHIFT
27
|
|
#define
|
_CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT
0x00000008UL
|
|
#define
|
_CMU_AUXHFRCOCTRL_FREQRANGE_MASK
0x1F0000UL
|
|
#define
|
_CMU_AUXHFRCOCTRL_FREQRANGE_SHIFT
16
|
|
#define
|
_CMU_AUXHFRCOCTRL_LDOHP_DEFAULT
0x00000001UL
|
|
#define
|
_CMU_AUXHFRCOCTRL_LDOHP_MASK
0x1000000UL
|
|
#define
|
_CMU_AUXHFRCOCTRL_LDOHP_SHIFT
24
|
|
#define
|
_CMU_AUXHFRCOCTRL_MASK
0xFFFF3F7FUL
|
|
#define
|
_CMU_AUXHFRCOCTRL_RESETVALUE
0xB1481F3CUL
|
|
#define
|
_CMU_AUXHFRCOCTRL_TUNING_DEFAULT
0x0000003CUL
|
|
#define
|
_CMU_AUXHFRCOCTRL_TUNING_MASK
0x7FUL
|
|
#define
|
_CMU_AUXHFRCOCTRL_TUNING_SHIFT
0
|
|
#define
|
_CMU_AUXHFRCOCTRL_VREFTC_DEFAULT
0x0000000BUL
|
|
#define
|
_CMU_AUXHFRCOCTRL_VREFTC_MASK
0xF0000000UL
|
|
#define
|
_CMU_AUXHFRCOCTRL_VREFTC_SHIFT
28
|
|
#define
|
_CMU_CALCNT_CALCNT_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_CALCNT_CALCNT_MASK
0xFFFFFUL
|
|
#define
|
_CMU_CALCNT_CALCNT_SHIFT
0
|
|
#define
|
_CMU_CALCNT_MASK
0x000FFFFFUL
|
|
#define
|
_CMU_CALCNT_RESETVALUE
0x00000000UL
|
|
#define
|
_CMU_CALCTRL_CONT_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_CALCTRL_CONT_MASK
0x100UL
|
|
#define
|
_CMU_CALCTRL_CONT_SHIFT
8
|
|
#define
|
_CMU_CALCTRL_DOWNSEL_AUXHFRCO
0x00000005UL
|
|
#define
|
_CMU_CALCTRL_DOWNSEL_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_CALCTRL_DOWNSEL_HFCLK
0x00000000UL
|
|
#define
|
_CMU_CALCTRL_DOWNSEL_HFRCO
0x00000003UL
|
|
#define
|
_CMU_CALCTRL_DOWNSEL_HFXO
0x00000001UL
|
|
#define
|
_CMU_CALCTRL_DOWNSEL_LFRCO
0x00000004UL
|
|
#define
|
_CMU_CALCTRL_DOWNSEL_LFXO
0x00000002UL
|
|
#define
|
_CMU_CALCTRL_DOWNSEL_MASK
0x70UL
|
|
#define
|
_CMU_CALCTRL_DOWNSEL_PRS
0x00000006UL
|
|
#define
|
_CMU_CALCTRL_DOWNSEL_SHIFT
4
|
|
#define
|
_CMU_CALCTRL_MASK
0x0F0F0177UL
|
|
#define
|
_CMU_CALCTRL_PRSDOWNSEL_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_CALCTRL_PRSDOWNSEL_MASK
0xF000000UL
|
|
#define
|
_CMU_CALCTRL_PRSDOWNSEL_PRSCH0
0x00000000UL
|
|
#define
|
_CMU_CALCTRL_PRSDOWNSEL_PRSCH1
0x00000001UL
|
|
#define
|
_CMU_CALCTRL_PRSDOWNSEL_PRSCH10
0x0000000AUL
|
|
#define
|
_CMU_CALCTRL_PRSDOWNSEL_PRSCH11
0x0000000BUL
|
|
#define
|
_CMU_CALCTRL_PRSDOWNSEL_PRSCH2
0x00000002UL
|
|
#define
|
_CMU_CALCTRL_PRSDOWNSEL_PRSCH3
0x00000003UL
|
|
#define
|
_CMU_CALCTRL_PRSDOWNSEL_PRSCH4
0x00000004UL
|
|
#define
|
_CMU_CALCTRL_PRSDOWNSEL_PRSCH5
0x00000005UL
|
|
#define
|
_CMU_CALCTRL_PRSDOWNSEL_PRSCH6
0x00000006UL
|
|
#define
|
_CMU_CALCTRL_PRSDOWNSEL_PRSCH7
0x00000007UL
|
|
#define
|
_CMU_CALCTRL_PRSDOWNSEL_PRSCH8
0x00000008UL
|
|
#define
|
_CMU_CALCTRL_PRSDOWNSEL_PRSCH9
0x00000009UL
|
|
#define
|
_CMU_CALCTRL_PRSDOWNSEL_SHIFT
24
|
|
#define
|
_CMU_CALCTRL_PRSUPSEL_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_CALCTRL_PRSUPSEL_MASK
0xF0000UL
|
|
#define
|
_CMU_CALCTRL_PRSUPSEL_PRSCH0
0x00000000UL
|
|
#define
|
_CMU_CALCTRL_PRSUPSEL_PRSCH1
0x00000001UL
|
|
#define
|
_CMU_CALCTRL_PRSUPSEL_PRSCH10
0x0000000AUL
|
|
#define
|
_CMU_CALCTRL_PRSUPSEL_PRSCH11
0x0000000BUL
|
|
#define
|
_CMU_CALCTRL_PRSUPSEL_PRSCH2
0x00000002UL
|
|
#define
|
_CMU_CALCTRL_PRSUPSEL_PRSCH3
0x00000003UL
|
|
#define
|
_CMU_CALCTRL_PRSUPSEL_PRSCH4
0x00000004UL
|
|
#define
|
_CMU_CALCTRL_PRSUPSEL_PRSCH5
0x00000005UL
|
|
#define
|
_CMU_CALCTRL_PRSUPSEL_PRSCH6
0x00000006UL
|
|
#define
|
_CMU_CALCTRL_PRSUPSEL_PRSCH7
0x00000007UL
|
|
#define
|
_CMU_CALCTRL_PRSUPSEL_PRSCH8
0x00000008UL
|
|
#define
|
_CMU_CALCTRL_PRSUPSEL_PRSCH9
0x00000009UL
|
|
#define
|
_CMU_CALCTRL_PRSUPSEL_SHIFT
16
|
|
#define
|
_CMU_CALCTRL_RESETVALUE
0x00000000UL
|
|
#define
|
_CMU_CALCTRL_UPSEL_AUXHFRCO
0x00000004UL
|
|
#define
|
_CMU_CALCTRL_UPSEL_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_CALCTRL_UPSEL_HFRCO
0x00000002UL
|
|
#define
|
_CMU_CALCTRL_UPSEL_HFXO
0x00000000UL
|
|
#define
|
_CMU_CALCTRL_UPSEL_LFRCO
0x00000003UL
|
|
#define
|
_CMU_CALCTRL_UPSEL_LFXO
0x00000001UL
|
|
#define
|
_CMU_CALCTRL_UPSEL_MASK
0x7UL
|
|
#define
|
_CMU_CALCTRL_UPSEL_PRS
0x00000005UL
|
|
#define
|
_CMU_CALCTRL_UPSEL_SHIFT
0
|
|
#define
|
_CMU_CMD_CALSTART_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_CMD_CALSTART_MASK
0x1UL
|
|
#define
|
_CMU_CMD_CALSTART_SHIFT
0
|
|
#define
|
_CMU_CMD_CALSTOP_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_CMD_CALSTOP_MASK
0x2UL
|
|
#define
|
_CMU_CMD_CALSTOP_SHIFT
1
|
|
#define
|
_CMU_CMD_HFXOPEAKDETSTART_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_CMD_HFXOPEAKDETSTART_MASK
0x10UL
|
|
#define
|
_CMU_CMD_HFXOPEAKDETSTART_SHIFT
4
|
|
#define
|
_CMU_CMD_HFXOSHUNTOPTSTART_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_CMD_HFXOSHUNTOPTSTART_MASK
0x20UL
|
|
#define
|
_CMU_CMD_HFXOSHUNTOPTSTART_SHIFT
5
|
|
#define
|
_CMU_CMD_MASK
0x00000033UL
|
|
#define
|
_CMU_CMD_RESETVALUE
0x00000000UL
|
|
#define
|
_CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ
0x0000000DUL
|
|
#define
|
_CMU_CTRL_CLKOUTSEL0_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_CTRL_CLKOUTSEL0_DISABLED
0x00000000UL
|
|
#define
|
_CMU_CTRL_CLKOUTSEL0_HFEXPCLK
0x00000007UL
|
|
#define
|
_CMU_CTRL_CLKOUTSEL0_HFRCOQ
0x0000000CUL
|
|
#define
|
_CMU_CTRL_CLKOUTSEL0_HFSRCCLK
0x0000000FUL
|
|
#define
|
_CMU_CTRL_CLKOUTSEL0_HFXO
0x00000006UL
|
|
#define
|
_CMU_CTRL_CLKOUTSEL0_HFXOQ
0x0000000EUL
|
|
#define
|
_CMU_CTRL_CLKOUTSEL0_LFRCO
0x00000002UL
|
|
#define
|
_CMU_CTRL_CLKOUTSEL0_LFRCOQ
0x0000000AUL
|
|
#define
|
_CMU_CTRL_CLKOUTSEL0_LFXO
0x00000003UL
|
|
#define
|
_CMU_CTRL_CLKOUTSEL0_LFXOQ
0x0000000BUL
|
|
#define
|
_CMU_CTRL_CLKOUTSEL0_MASK
0xFUL
|
|
#define
|
_CMU_CTRL_CLKOUTSEL0_SHIFT
0
|
|
#define
|
_CMU_CTRL_CLKOUTSEL0_ULFRCO
0x00000001UL
|
|
#define
|
_CMU_CTRL_CLKOUTSEL0_ULFRCOQ
0x00000009UL
|
|
#define
|
_CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ
0x0000000DUL
|
|
#define
|
_CMU_CTRL_CLKOUTSEL1_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_CTRL_CLKOUTSEL1_DISABLED
0x00000000UL
|
|
#define
|
_CMU_CTRL_CLKOUTSEL1_HFEXPCLK
0x00000007UL
|
|
#define
|
_CMU_CTRL_CLKOUTSEL1_HFRCOQ
0x0000000CUL
|
|
#define
|
_CMU_CTRL_CLKOUTSEL1_HFSRCCLK
0x0000000FUL
|
|
#define
|
_CMU_CTRL_CLKOUTSEL1_HFXO
0x00000006UL
|
|
#define
|
_CMU_CTRL_CLKOUTSEL1_HFXOQ
0x0000000EUL
|
|
#define
|
_CMU_CTRL_CLKOUTSEL1_LFRCO
0x00000002UL
|
|
#define
|
_CMU_CTRL_CLKOUTSEL1_LFRCOQ
0x0000000AUL
|
|
#define
|
_CMU_CTRL_CLKOUTSEL1_LFXO
0x00000003UL
|
|
#define
|
_CMU_CTRL_CLKOUTSEL1_LFXOQ
0x0000000BUL
|
|
#define
|
_CMU_CTRL_CLKOUTSEL1_MASK
0x1E0UL
|
|
#define
|
_CMU_CTRL_CLKOUTSEL1_SHIFT
5
|
|
#define
|
_CMU_CTRL_CLKOUTSEL1_ULFRCO
0x00000001UL
|
|
#define
|
_CMU_CTRL_CLKOUTSEL1_ULFRCOQ
0x00000009UL
|
|
#define
|
_CMU_CTRL_HFPERCLKEN_DEFAULT
0x00000001UL
|
|
#define
|
_CMU_CTRL_HFPERCLKEN_MASK
0x100000UL
|
|
#define
|
_CMU_CTRL_HFPERCLKEN_SHIFT
20
|
|
#define
|
_CMU_CTRL_MASK
0x001101EFUL
|
|
#define
|
_CMU_CTRL_RESETVALUE
0x00300000UL
|
|
#define
|
_CMU_CTRL_WSHFLE_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_CTRL_WSHFLE_MASK
0x10000UL
|
|
#define
|
_CMU_CTRL_WSHFLE_SHIFT
16
|
|
#define
|
_CMU_DBGCLKSEL_DBG_AUXHFRCO
0x00000000UL
|
|
#define
|
_CMU_DBGCLKSEL_DBG_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_DBGCLKSEL_DBG_HFCLK
0x00000001UL
|
|
#define
|
_CMU_DBGCLKSEL_DBG_MASK
0x1UL
|
|
#define
|
_CMU_DBGCLKSEL_DBG_SHIFT
0
|
|
#define
|
_CMU_DBGCLKSEL_MASK
0x00000001UL
|
|
#define
|
_CMU_DBGCLKSEL_RESETVALUE
0x00000000UL
|
|
#define
|
_CMU_FREEZE_MASK
0x00000001UL
|
|
#define
|
_CMU_FREEZE_REGFREEZE_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_FREEZE_REGFREEZE_FREEZE
0x00000001UL
|
|
#define
|
_CMU_FREEZE_REGFREEZE_MASK
0x1UL
|
|
#define
|
_CMU_FREEZE_REGFREEZE_SHIFT
0
|
|
#define
|
_CMU_FREEZE_REGFREEZE_UPDATE
0x00000000UL
|
|
#define
|
_CMU_FREEZE_RESETVALUE
0x00000000UL
|
|
#define
|
_CMU_HFBUSCLKEN0_CRYPTO_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_HFBUSCLKEN0_CRYPTO_MASK
0x2UL
|
|
#define
|
_CMU_HFBUSCLKEN0_CRYPTO_SHIFT
1
|
|
#define
|
_CMU_HFBUSCLKEN0_GPCRC_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_HFBUSCLKEN0_GPCRC_MASK
0x20UL
|
|
#define
|
_CMU_HFBUSCLKEN0_GPCRC_SHIFT
5
|
|
#define
|
_CMU_HFBUSCLKEN0_GPIO_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_HFBUSCLKEN0_GPIO_MASK
0x4UL
|
|
#define
|
_CMU_HFBUSCLKEN0_GPIO_SHIFT
2
|
|
#define
|
_CMU_HFBUSCLKEN0_LDMA_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_HFBUSCLKEN0_LDMA_MASK
0x10UL
|
|
#define
|
_CMU_HFBUSCLKEN0_LDMA_SHIFT
4
|
|
#define
|
_CMU_HFBUSCLKEN0_LE_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_HFBUSCLKEN0_LE_MASK
0x1UL
|
|
#define
|
_CMU_HFBUSCLKEN0_LE_SHIFT
0
|
|
#define
|
_CMU_HFBUSCLKEN0_MASK
0x0000003FUL
|
|
#define
|
_CMU_HFBUSCLKEN0_PRS_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_HFBUSCLKEN0_PRS_MASK
0x8UL
|
|
#define
|
_CMU_HFBUSCLKEN0_PRS_SHIFT
3
|
|
#define
|
_CMU_HFBUSCLKEN0_RESETVALUE
0x00000000UL
|
|
#define
|
_CMU_HFCLKSEL_HF_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_HFCLKSEL_HF_HFRCO
0x00000001UL
|
|
#define
|
_CMU_HFCLKSEL_HF_HFXO
0x00000002UL
|
|
#define
|
_CMU_HFCLKSEL_HF_LFRCO
0x00000003UL
|
|
#define
|
_CMU_HFCLKSEL_HF_LFXO
0x00000004UL
|
|
#define
|
_CMU_HFCLKSEL_HF_MASK
0x7UL
|
|
#define
|
_CMU_HFCLKSEL_HF_SHIFT
0
|
|
#define
|
_CMU_HFCLKSEL_MASK
0x00000007UL
|
|
#define
|
_CMU_HFCLKSEL_RESETVALUE
0x00000000UL
|
|
#define
|
_CMU_HFCLKSTATUS_MASK
0x00000007UL
|
|
#define
|
_CMU_HFCLKSTATUS_RESETVALUE
0x00000001UL
|
|
#define
|
_CMU_HFCLKSTATUS_SELECTED_DEFAULT
0x00000001UL
|
|
#define
|
_CMU_HFCLKSTATUS_SELECTED_HFRCO
0x00000001UL
|
|
#define
|
_CMU_HFCLKSTATUS_SELECTED_HFXO
0x00000002UL
|
|
#define
|
_CMU_HFCLKSTATUS_SELECTED_LFRCO
0x00000003UL
|
|
#define
|
_CMU_HFCLKSTATUS_SELECTED_LFXO
0x00000004UL
|
|
#define
|
_CMU_HFCLKSTATUS_SELECTED_MASK
0x7UL
|
|
#define
|
_CMU_HFCLKSTATUS_SELECTED_SHIFT
0
|
|
#define
|
_CMU_HFCOREPRESC_MASK
0x0001FF00UL
|
|
#define
|
_CMU_HFCOREPRESC_PRESC_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_HFCOREPRESC_PRESC_MASK
0x1FF00UL
|
|
#define
|
_CMU_HFCOREPRESC_PRESC_NODIVISION
0x00000000UL
|
|
#define
|
_CMU_HFCOREPRESC_PRESC_SHIFT
8
|
|
#define
|
_CMU_HFCOREPRESC_RESETVALUE
0x00000000UL
|
|
#define
|
_CMU_HFEXPPRESC_MASK
0x00001F00UL
|
|
#define
|
_CMU_HFEXPPRESC_PRESC_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_HFEXPPRESC_PRESC_MASK
0x1F00UL
|
|
#define
|
_CMU_HFEXPPRESC_PRESC_NODIVISION
0x00000000UL
|
|
#define
|
_CMU_HFEXPPRESC_PRESC_SHIFT
8
|
|
#define
|
_CMU_HFEXPPRESC_RESETVALUE
0x00000000UL
|
|
#define
|
_CMU_HFPERCLKEN0_ACMP0_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_HFPERCLKEN0_ACMP0_MASK
0x10UL
|
|
#define
|
_CMU_HFPERCLKEN0_ACMP0_SHIFT
4
|
|
#define
|
_CMU_HFPERCLKEN0_ACMP1_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_HFPERCLKEN0_ACMP1_MASK
0x20UL
|
|
#define
|
_CMU_HFPERCLKEN0_ACMP1_SHIFT
5
|
|
#define
|
_CMU_HFPERCLKEN0_ADC0_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_HFPERCLKEN0_ADC0_MASK
0x100UL
|
|
#define
|
_CMU_HFPERCLKEN0_ADC0_SHIFT
8
|
|
#define
|
_CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_HFPERCLKEN0_CRYOTIMER_MASK
0x40UL
|
|
#define
|
_CMU_HFPERCLKEN0_CRYOTIMER_SHIFT
6
|
|
#define
|
_CMU_HFPERCLKEN0_I2C0_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_HFPERCLKEN0_I2C0_MASK
0x80UL
|
|
#define
|
_CMU_HFPERCLKEN0_I2C0_SHIFT
7
|
|
#define
|
_CMU_HFPERCLKEN0_IDAC0_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_HFPERCLKEN0_IDAC0_MASK
0x200UL
|
|
#define
|
_CMU_HFPERCLKEN0_IDAC0_SHIFT
9
|
|
#define
|
_CMU_HFPERCLKEN0_MASK
0x000003FFUL
|
|
#define
|
_CMU_HFPERCLKEN0_RESETVALUE
0x00000000UL
|
|
#define
|
_CMU_HFPERCLKEN0_TIMER0_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_HFPERCLKEN0_TIMER0_MASK
0x1UL
|
|
#define
|
_CMU_HFPERCLKEN0_TIMER0_SHIFT
0
|
|
#define
|
_CMU_HFPERCLKEN0_TIMER1_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_HFPERCLKEN0_TIMER1_MASK
0x2UL
|
|
#define
|
_CMU_HFPERCLKEN0_TIMER1_SHIFT
1
|
|
#define
|
_CMU_HFPERCLKEN0_USART0_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_HFPERCLKEN0_USART0_MASK
0x4UL
|
|
#define
|
_CMU_HFPERCLKEN0_USART0_SHIFT
2
|
|
#define
|
_CMU_HFPERCLKEN0_USART1_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_HFPERCLKEN0_USART1_MASK
0x8UL
|
|
#define
|
_CMU_HFPERCLKEN0_USART1_SHIFT
3
|
|
#define
|
_CMU_HFPERPRESC_MASK
0x0001FF00UL
|
|
#define
|
_CMU_HFPERPRESC_PRESC_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_HFPERPRESC_PRESC_MASK
0x1FF00UL
|
|
#define
|
_CMU_HFPERPRESC_PRESC_NODIVISION
0x00000000UL
|
|
#define
|
_CMU_HFPERPRESC_PRESC_SHIFT
8
|
|
#define
|
_CMU_HFPERPRESC_RESETVALUE
0x00000000UL
|
|
#define
|
_CMU_HFPRESC_HFCLKLEPRESC_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_HFPRESC_HFCLKLEPRESC_DIV2
0x00000000UL
|
|
#define
|
_CMU_HFPRESC_HFCLKLEPRESC_DIV4
0x00000001UL
|
|
#define
|
_CMU_HFPRESC_HFCLKLEPRESC_MASK
0x1000000UL
|
|
#define
|
_CMU_HFPRESC_HFCLKLEPRESC_SHIFT
24
|
|
#define
|
_CMU_HFPRESC_MASK
0x01001F00UL
|
|
#define
|
_CMU_HFPRESC_PRESC_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_HFPRESC_PRESC_MASK
0x1F00UL
|
|
#define
|
_CMU_HFPRESC_PRESC_NODIVISION
0x00000000UL
|
|
#define
|
_CMU_HFPRESC_PRESC_SHIFT
8
|
|
#define
|
_CMU_HFPRESC_RESETVALUE
0x00000000UL
|
|
#define
|
_CMU_HFRCOCTRL_CLKDIV_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_HFRCOCTRL_CLKDIV_DIV1
0x00000000UL
|
|
#define
|
_CMU_HFRCOCTRL_CLKDIV_DIV2
0x00000001UL
|
|
#define
|
_CMU_HFRCOCTRL_CLKDIV_DIV4
0x00000002UL
|
|
#define
|
_CMU_HFRCOCTRL_CLKDIV_MASK
0x6000000UL
|
|
#define
|
_CMU_HFRCOCTRL_CLKDIV_SHIFT
25
|
|
#define
|
_CMU_HFRCOCTRL_CMPBIAS_DEFAULT
0x00000002UL
|
|
#define
|
_CMU_HFRCOCTRL_CMPBIAS_MASK
0xE00000UL
|
|
#define
|
_CMU_HFRCOCTRL_CMPBIAS_SHIFT
21
|
|
#define
|
_CMU_HFRCOCTRL_FINETUNING_DEFAULT
0x0000001FUL
|
|
#define
|
_CMU_HFRCOCTRL_FINETUNING_MASK
0x3F00UL
|
|
#define
|
_CMU_HFRCOCTRL_FINETUNING_SHIFT
8
|
|
#define
|
_CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_HFRCOCTRL_FINETUNINGEN_MASK
0x8000000UL
|
|
#define
|
_CMU_HFRCOCTRL_FINETUNINGEN_SHIFT
27
|
|
#define
|
_CMU_HFRCOCTRL_FREQRANGE_DEFAULT
0x00000008UL
|
|
#define
|
_CMU_HFRCOCTRL_FREQRANGE_MASK
0x1F0000UL
|
|
#define
|
_CMU_HFRCOCTRL_FREQRANGE_SHIFT
16
|
|
#define
|
_CMU_HFRCOCTRL_LDOHP_DEFAULT
0x00000001UL
|
|
#define
|
_CMU_HFRCOCTRL_LDOHP_MASK
0x1000000UL
|
|
#define
|
_CMU_HFRCOCTRL_LDOHP_SHIFT
24
|
|
#define
|
_CMU_HFRCOCTRL_MASK
0xFFFF3F7FUL
|
|
#define
|
_CMU_HFRCOCTRL_RESETVALUE
0xB1481F3CUL
|
|
#define
|
_CMU_HFRCOCTRL_TUNING_DEFAULT
0x0000003CUL
|
|
#define
|
_CMU_HFRCOCTRL_TUNING_MASK
0x7FUL
|
|
#define
|
_CMU_HFRCOCTRL_TUNING_SHIFT
0
|
|
#define
|
_CMU_HFRCOCTRL_VREFTC_DEFAULT
0x0000000BUL
|
|
#define
|
_CMU_HFRCOCTRL_VREFTC_MASK
0xF0000000UL
|
|
#define
|
_CMU_HFRCOCTRL_VREFTC_SHIFT
28
|
|
#define
|
_CMU_HFXOCTRL1_MASK
0x00000277UL
|
|
#define
|
_CMU_HFXOCTRL1_PEAKDETTHR_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_HFXOCTRL1_PEAKDETTHR_MASK
0x7UL
|
|
#define
|
_CMU_HFXOCTRL1_PEAKDETTHR_SHIFT
0
|
|
#define
|
_CMU_HFXOCTRL1_REGLVL_DEFAULT
0x00000004UL
|
|
#define
|
_CMU_HFXOCTRL1_REGLVL_MASK
0x70UL
|
|
#define
|
_CMU_HFXOCTRL1_REGLVL_SHIFT
4
|
|
#define
|
_CMU_HFXOCTRL1_RESETVALUE
0x00000240UL
|
|
#define
|
_CMU_HFXOCTRL1_XTIBIASEN_DEFAULT
0x00000001UL
|
|
#define
|
_CMU_HFXOCTRL1_XTIBIASEN_MASK
0x200UL
|
|
#define
|
_CMU_HFXOCTRL1_XTIBIASEN_SHIFT
9
|
|
#define
|
_CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_HFXOCTRL_AUTOSTARTEM0EM1_MASK
0x10000000UL
|
|
#define
|
_CMU_HFXOCTRL_AUTOSTARTEM0EM1_SHIFT
28
|
|
#define
|
_CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_MASK
0x20000000UL
|
|
#define
|
_CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_SHIFT
29
|
|
#define
|
_CMU_HFXOCTRL_LFTIMEOUT_0CYCLES
0x00000000UL
|
|
#define
|
_CMU_HFXOCTRL_LFTIMEOUT_16CYCLES
0x00000003UL
|
|
#define
|
_CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES
0x00000006UL
|
|
#define
|
_CMU_HFXOCTRL_LFTIMEOUT_2CYCLES
0x00000001UL
|
|
#define
|
_CMU_HFXOCTRL_LFTIMEOUT_32CYCLES
0x00000004UL
|
|
#define
|
_CMU_HFXOCTRL_LFTIMEOUT_4CYCLES
0x00000002UL
|
|
#define
|
_CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES
0x00000007UL
|
|
#define
|
_CMU_HFXOCTRL_LFTIMEOUT_64CYCLES
0x00000005UL
|
|
#define
|
_CMU_HFXOCTRL_LFTIMEOUT_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_HFXOCTRL_LFTIMEOUT_MASK
0x7000000UL
|
|
#define
|
_CMU_HFXOCTRL_LFTIMEOUT_SHIFT
24
|
|
#define
|
_CMU_HFXOCTRL_LOWPOWER_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_HFXOCTRL_LOWPOWER_MASK
0x100UL
|
|
#define
|
_CMU_HFXOCTRL_LOWPOWER_SHIFT
8
|
|
#define
|
_CMU_HFXOCTRL_MASK
0x37000731UL
|
|
#define
|
_CMU_HFXOCTRL_MODE_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_HFXOCTRL_MODE_EXTCLK
0x00000001UL
|
|
#define
|
_CMU_HFXOCTRL_MODE_MASK
0x1UL
|
|
#define
|
_CMU_HFXOCTRL_MODE_SHIFT
0
|
|
#define
|
_CMU_HFXOCTRL_MODE_XTAL
0x00000000UL
|
|
#define
|
_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_AUTOCMD
0x00000000UL
|
|
#define
|
_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_CMD
0x00000001UL
|
|
#define
|
_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MANUAL
0x00000002UL
|
|
#define
|
_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK
0x30UL
|
|
#define
|
_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_SHIFT
4
|
|
#define
|
_CMU_HFXOCTRL_RESETVALUE
0x00000000UL
|
|
#define
|
_CMU_HFXOCTRL_XTI2GND_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_HFXOCTRL_XTI2GND_MASK
0x200UL
|
|
#define
|
_CMU_HFXOCTRL_XTI2GND_SHIFT
9
|
|
#define
|
_CMU_HFXOCTRL_XTO2GND_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_HFXOCTRL_XTO2GND_MASK
0x400UL
|
|
#define
|
_CMU_HFXOCTRL_XTO2GND_SHIFT
10
|
|
#define
|
_CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT
0x000000A0UL
|
|
#define
|
_CMU_HFXOSTARTUPCTRL_CTUNE_MASK
0xFF800UL
|
|
#define
|
_CMU_HFXOSTARTUPCTRL_CTUNE_SHIFT
11
|
|
#define
|
_CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT
0x00000060UL
|
|
#define
|
_CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_MASK
0x7FUL
|
|
#define
|
_CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_SHIFT
0
|
|
#define
|
_CMU_HFXOSTARTUPCTRL_MASK
0xFFEFF87FUL
|
|
#define
|
_CMU_HFXOSTARTUPCTRL_RESERVED0_DEFAULT
0x00000009UL
|
|
#define
|
_CMU_HFXOSTARTUPCTRL_RESERVED0_MASK
0xFE00000UL
|
|
#define
|
_CMU_HFXOSTARTUPCTRL_RESERVED0_SHIFT
21
|
|
#define
|
_CMU_HFXOSTARTUPCTRL_RESERVED1_DEFAULT
0x0000000AUL
|
|
#define
|
_CMU_HFXOSTARTUPCTRL_RESERVED1_MASK
0xF0000000UL
|
|
#define
|
_CMU_HFXOSTARTUPCTRL_RESERVED1_SHIFT
28
|
|
#define
|
_CMU_HFXOSTARTUPCTRL_RESETVALUE
0xA1250060UL
|
|
#define
|
_CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT
0x00000155UL
|
|
#define
|
_CMU_HFXOSTEADYSTATECTRL_CTUNE_MASK
0xFF800UL
|
|
#define
|
_CMU_HFXOSTEADYSTATECTRL_CTUNE_SHIFT
11
|
|
#define
|
_CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT
0x00000009UL
|
|
#define
|
_CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_MASK
0x7FUL
|
|
#define
|
_CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_SHIFT
0
|
|
#define
|
_CMU_HFXOSTEADYSTATECTRL_MASK
0xF70FFFFFUL
|
|
#define
|
_CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_MASK
0x4000000UL
|
|
#define
|
_CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_SHIFT
26
|
|
#define
|
_CMU_HFXOSTEADYSTATECTRL_REGISH_DEFAULT
0x0000000AUL
|
|
#define
|
_CMU_HFXOSTEADYSTATECTRL_REGISH_MASK
0x780UL
|
|
#define
|
_CMU_HFXOSTEADYSTATECTRL_REGISH_SHIFT
7
|
|
#define
|
_CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_DEFAULT
0x0000000AUL
|
|
#define
|
_CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_MASK
0xF0000000UL
|
|
#define
|
_CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_SHIFT
28
|
|
#define
|
_CMU_HFXOSTEADYSTATECTRL_REGSELILOW_DEFAULT
0x00000003UL
|
|
#define
|
_CMU_HFXOSTEADYSTATECTRL_REGSELILOW_MASK
0x3000000UL
|
|
#define
|
_CMU_HFXOSTEADYSTATECTRL_REGSELILOW_SHIFT
24
|
|
#define
|
_CMU_HFXOSTEADYSTATECTRL_RESETVALUE
0xA30AAD09UL
|
|
#define
|
_CMU_HFXOTIMEOUTCTRL_MASK
0x000FFFFFUL
|
|
#define
|
_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES
0x00000002UL
|
|
#define
|
_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES
0x00000009UL
|
|
#define
|
_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES
0x00000005UL
|
|
#define
|
_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES
0x00000004UL
|
|
#define
|
_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES
0x00000000UL
|
|
#define
|
_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES
0x00000006UL
|
|
#define
|
_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES
0x00000003UL
|
|
#define
|
_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES
0x0000000AUL
|
|
#define
|
_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES
0x00000001UL
|
|
#define
|
_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES
0x00000007UL
|
|
#define
|
_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES
0x00000008UL
|
|
#define
|
_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT
0x00000006UL
|
|
#define
|
_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_MASK
0xF000UL
|
|
#define
|
_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_SHIFT
12
|
|
#define
|
_CMU_HFXOTIMEOUTCTRL_RESERVED2_DEFAULT
0x00000006UL
|
|
#define
|
_CMU_HFXOTIMEOUTCTRL_RESERVED2_MASK
0xF00UL
|
|
#define
|
_CMU_HFXOTIMEOUTCTRL_RESERVED2_SHIFT
8
|
|
#define
|
_CMU_HFXOTIMEOUTCTRL_RESETVALUE
0x00026667UL
|
|
#define
|
_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_16CYCLES
0x00000002UL
|
|
#define
|
_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_16KCYCLES
0x00000009UL
|
|
#define
|
_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_1KCYCLES
0x00000005UL
|
|
#define
|
_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_256CYCLES
0x00000004UL
|
|
#define
|
_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_2CYCLES
0x00000000UL
|
|
#define
|
_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_2KCYCLES
0x00000006UL
|
|
#define
|
_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_32CYCLES
0x00000003UL
|
|
#define
|
_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_32KCYCLES
0x0000000AUL
|
|
#define
|
_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_4CYCLES
0x00000001UL
|
|
#define
|
_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_4KCYCLES
0x00000007UL
|
|
#define
|
_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_8KCYCLES
0x00000008UL
|
|
#define
|
_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_DEFAULT
0x00000002UL
|
|
#define
|
_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_MASK
0xF0000UL
|
|
#define
|
_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_SHIFT
16
|
|
#define
|
_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES
0x00000002UL
|
|
#define
|
_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES
0x00000009UL
|
|
#define
|
_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES
0x00000005UL
|
|
#define
|
_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES
0x00000004UL
|
|
#define
|
_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES
0x00000000UL
|
|
#define
|
_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES
0x00000006UL
|
|
#define
|
_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES
0x00000003UL
|
|
#define
|
_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES
0x0000000AUL
|
|
#define
|
_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES
0x00000001UL
|
|
#define
|
_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES
0x00000007UL
|
|
#define
|
_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES
0x00000008UL
|
|
#define
|
_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT
0x00000007UL
|
|
#define
|
_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_MASK
0xFUL
|
|
#define
|
_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_SHIFT
0
|
|
#define
|
_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES
0x00000002UL
|
|
#define
|
_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES
0x00000009UL
|
|
#define
|
_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES
0x00000005UL
|
|
#define
|
_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES
0x00000004UL
|
|
#define
|
_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES
0x00000000UL
|
|
#define
|
_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES
0x00000006UL
|
|
#define
|
_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES
0x00000003UL
|
|
#define
|
_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES
0x0000000AUL
|
|
#define
|
_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES
0x00000001UL
|
|
#define
|
_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES
0x00000007UL
|
|
#define
|
_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES
0x00000008UL
|
|
#define
|
_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT
0x00000006UL
|
|
#define
|
_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_MASK
0xF0UL
|
|
#define
|
_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_SHIFT
4
|
|
#define
|
_CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_MASK
0x7FUL
|
|
#define
|
_CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_SHIFT
0
|
|
#define
|
_CMU_HFXOTRIMSTATUS_MASK
0x000007FFUL
|
|
#define
|
_CMU_HFXOTRIMSTATUS_REGISH_DEFAULT
0x0000000AUL
|
|
#define
|
_CMU_HFXOTRIMSTATUS_REGISH_MASK
0x780UL
|
|
#define
|
_CMU_HFXOTRIMSTATUS_REGISH_SHIFT
7
|
|
#define
|
_CMU_HFXOTRIMSTATUS_RESETVALUE
0x00000500UL
|
|
#define
|
_CMU_IEN_AUXHFRCORDY_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_IEN_AUXHFRCORDY_MASK
0x10UL
|
|
#define
|
_CMU_IEN_AUXHFRCORDY_SHIFT
4
|
|
#define
|
_CMU_IEN_CALOF_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_IEN_CALOF_MASK
0x40UL
|
|
#define
|
_CMU_IEN_CALOF_SHIFT
6
|
|
#define
|
_CMU_IEN_CALRDY_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_IEN_CALRDY_MASK
0x20UL
|
|
#define
|
_CMU_IEN_CALRDY_SHIFT
5
|
|
#define
|
_CMU_IEN_CMUERR_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_IEN_CMUERR_MASK
0x80000000UL
|
|
#define
|
_CMU_IEN_CMUERR_SHIFT
31
|
|
#define
|
_CMU_IEN_HFRCODIS_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_IEN_HFRCODIS_MASK
0x2000UL
|
|
#define
|
_CMU_IEN_HFRCODIS_SHIFT
13
|
|
#define
|
_CMU_IEN_HFRCORDY_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_IEN_HFRCORDY_MASK
0x1UL
|
|
#define
|
_CMU_IEN_HFRCORDY_SHIFT
0
|
|
#define
|
_CMU_IEN_HFXOAUTOSW_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_IEN_HFXOAUTOSW_MASK
0x200UL
|
|
#define
|
_CMU_IEN_HFXOAUTOSW_SHIFT
9
|
|
#define
|
_CMU_IEN_HFXODISERR_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_IEN_HFXODISERR_MASK
0x100UL
|
|
#define
|
_CMU_IEN_HFXODISERR_SHIFT
8
|
|
#define
|
_CMU_IEN_HFXOPEAKDETERR_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_IEN_HFXOPEAKDETERR_MASK
0x400UL
|
|
#define
|
_CMU_IEN_HFXOPEAKDETERR_SHIFT
10
|
|
#define
|
_CMU_IEN_HFXOPEAKDETRDY_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_IEN_HFXOPEAKDETRDY_MASK
0x800UL
|
|
#define
|
_CMU_IEN_HFXOPEAKDETRDY_SHIFT
11
|
|
#define
|
_CMU_IEN_HFXORDY_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_IEN_HFXORDY_MASK
0x2UL
|
|
#define
|
_CMU_IEN_HFXORDY_SHIFT
1
|
|
#define
|
_CMU_IEN_HFXOSHUNTOPTRDY_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_IEN_HFXOSHUNTOPTRDY_MASK
0x1000UL
|
|
#define
|
_CMU_IEN_HFXOSHUNTOPTRDY_SHIFT
12
|
|
#define
|
_CMU_IEN_LFRCORDY_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_IEN_LFRCORDY_MASK
0x4UL
|
|
#define
|
_CMU_IEN_LFRCORDY_SHIFT
2
|
|
#define
|
_CMU_IEN_LFTIMEOUTERR_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_IEN_LFTIMEOUTERR_MASK
0x4000UL
|
|
#define
|
_CMU_IEN_LFTIMEOUTERR_SHIFT
14
|
|
#define
|
_CMU_IEN_LFXORDY_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_IEN_LFXORDY_MASK
0x8UL
|
|
#define
|
_CMU_IEN_LFXORDY_SHIFT
3
|
|
#define
|
_CMU_IEN_MASK
0x80007F7FUL
|
|
#define
|
_CMU_IEN_RESETVALUE
0x00000000UL
|
|
#define
|
_CMU_IF_AUXHFRCORDY_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_IF_AUXHFRCORDY_MASK
0x10UL
|
|
#define
|
_CMU_IF_AUXHFRCORDY_SHIFT
4
|
|
#define
|
_CMU_IF_CALOF_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_IF_CALOF_MASK
0x40UL
|
|
#define
|
_CMU_IF_CALOF_SHIFT
6
|
|
#define
|
_CMU_IF_CALRDY_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_IF_CALRDY_MASK
0x20UL
|
|
#define
|
_CMU_IF_CALRDY_SHIFT
5
|
|
#define
|
_CMU_IF_CMUERR_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_IF_CMUERR_MASK
0x80000000UL
|
|
#define
|
_CMU_IF_CMUERR_SHIFT
31
|
|
#define
|
_CMU_IF_HFRCODIS_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_IF_HFRCODIS_MASK
0x2000UL
|
|
#define
|
_CMU_IF_HFRCODIS_SHIFT
13
|
|
#define
|
_CMU_IF_HFRCORDY_DEFAULT
0x00000001UL
|
|
#define
|
_CMU_IF_HFRCORDY_MASK
0x1UL
|
|
#define
|
_CMU_IF_HFRCORDY_SHIFT
0
|
|
#define
|
_CMU_IF_HFXOAUTOSW_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_IF_HFXOAUTOSW_MASK
0x200UL
|
|
#define
|
_CMU_IF_HFXOAUTOSW_SHIFT
9
|
|
#define
|
_CMU_IF_HFXODISERR_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_IF_HFXODISERR_MASK
0x100UL
|
|
#define
|
_CMU_IF_HFXODISERR_SHIFT
8
|
|
#define
|
_CMU_IF_HFXOPEAKDETERR_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_IF_HFXOPEAKDETERR_MASK
0x400UL
|
|
#define
|
_CMU_IF_HFXOPEAKDETERR_SHIFT
10
|
|
#define
|
_CMU_IF_HFXOPEAKDETRDY_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_IF_HFXOPEAKDETRDY_MASK
0x800UL
|
|
#define
|
_CMU_IF_HFXOPEAKDETRDY_SHIFT
11
|
|
#define
|
_CMU_IF_HFXORDY_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_IF_HFXORDY_MASK
0x2UL
|
|
#define
|
_CMU_IF_HFXORDY_SHIFT
1
|
|
#define
|
_CMU_IF_HFXOSHUNTOPTRDY_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_IF_HFXOSHUNTOPTRDY_MASK
0x1000UL
|
|
#define
|
_CMU_IF_HFXOSHUNTOPTRDY_SHIFT
12
|
|
#define
|
_CMU_IF_LFRCORDY_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_IF_LFRCORDY_MASK
0x4UL
|
|
#define
|
_CMU_IF_LFRCORDY_SHIFT
2
|
|
#define
|
_CMU_IF_LFTIMEOUTERR_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_IF_LFTIMEOUTERR_MASK
0x4000UL
|
|
#define
|
_CMU_IF_LFTIMEOUTERR_SHIFT
14
|
|
#define
|
_CMU_IF_LFXORDY_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_IF_LFXORDY_MASK
0x8UL
|
|
#define
|
_CMU_IF_LFXORDY_SHIFT
3
|
|
#define
|
_CMU_IF_MASK
0x80007F7FUL
|
|
#define
|
_CMU_IF_RESETVALUE
0x00000001UL
|
|
#define
|
_CMU_IFC_AUXHFRCORDY_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_IFC_AUXHFRCORDY_MASK
0x10UL
|
|
#define
|
_CMU_IFC_AUXHFRCORDY_SHIFT
4
|
|
#define
|
_CMU_IFC_CALOF_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_IFC_CALOF_MASK
0x40UL
|
|
#define
|
_CMU_IFC_CALOF_SHIFT
6
|
|
#define
|
_CMU_IFC_CALRDY_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_IFC_CALRDY_MASK
0x20UL
|
|
#define
|
_CMU_IFC_CALRDY_SHIFT
5
|
|
#define
|
_CMU_IFC_CMUERR_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_IFC_CMUERR_MASK
0x80000000UL
|
|
#define
|
_CMU_IFC_CMUERR_SHIFT
31
|
|
#define
|
_CMU_IFC_HFRCODIS_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_IFC_HFRCODIS_MASK
0x2000UL
|
|
#define
|
_CMU_IFC_HFRCODIS_SHIFT
13
|
|
#define
|
_CMU_IFC_HFRCORDY_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_IFC_HFRCORDY_MASK
0x1UL
|
|
#define
|
_CMU_IFC_HFRCORDY_SHIFT
0
|
|
#define
|
_CMU_IFC_HFXOAUTOSW_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_IFC_HFXOAUTOSW_MASK
0x200UL
|
|
#define
|
_CMU_IFC_HFXOAUTOSW_SHIFT
9
|
|
#define
|
_CMU_IFC_HFXODISERR_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_IFC_HFXODISERR_MASK
0x100UL
|
|
#define
|
_CMU_IFC_HFXODISERR_SHIFT
8
|
|
#define
|
_CMU_IFC_HFXOPEAKDETERR_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_IFC_HFXOPEAKDETERR_MASK
0x400UL
|
|
#define
|
_CMU_IFC_HFXOPEAKDETERR_SHIFT
10
|
|
#define
|
_CMU_IFC_HFXOPEAKDETRDY_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_IFC_HFXOPEAKDETRDY_MASK
0x800UL
|
|
#define
|
_CMU_IFC_HFXOPEAKDETRDY_SHIFT
11
|
|
#define
|
_CMU_IFC_HFXORDY_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_IFC_HFXORDY_MASK
0x2UL
|
|
#define
|
_CMU_IFC_HFXORDY_SHIFT
1
|
|
#define
|
_CMU_IFC_HFXOSHUNTOPTRDY_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_IFC_HFXOSHUNTOPTRDY_MASK
0x1000UL
|
|
#define
|
_CMU_IFC_HFXOSHUNTOPTRDY_SHIFT
12
|
|
#define
|
_CMU_IFC_LFRCORDY_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_IFC_LFRCORDY_MASK
0x4UL
|
|
#define
|
_CMU_IFC_LFRCORDY_SHIFT
2
|
|
#define
|
_CMU_IFC_LFTIMEOUTERR_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_IFC_LFTIMEOUTERR_MASK
0x4000UL
|
|
#define
|
_CMU_IFC_LFTIMEOUTERR_SHIFT
14
|
|
#define
|
_CMU_IFC_LFXORDY_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_IFC_LFXORDY_MASK
0x8UL
|
|
#define
|
_CMU_IFC_LFXORDY_SHIFT
3
|
|
#define
|
_CMU_IFC_MASK
0x80007F7FUL
|
|
#define
|
_CMU_IFC_RESETVALUE
0x00000000UL
|
|
#define
|
_CMU_IFS_AUXHFRCORDY_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_IFS_AUXHFRCORDY_MASK
0x10UL
|
|
#define
|
_CMU_IFS_AUXHFRCORDY_SHIFT
4
|
|
#define
|
_CMU_IFS_CALOF_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_IFS_CALOF_MASK
0x40UL
|
|
#define
|
_CMU_IFS_CALOF_SHIFT
6
|
|
#define
|
_CMU_IFS_CALRDY_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_IFS_CALRDY_MASK
0x20UL
|
|
#define
|
_CMU_IFS_CALRDY_SHIFT
5
|
|
#define
|
_CMU_IFS_CMUERR_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_IFS_CMUERR_MASK
0x80000000UL
|
|
#define
|
_CMU_IFS_CMUERR_SHIFT
31
|
|
#define
|
_CMU_IFS_HFRCODIS_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_IFS_HFRCODIS_MASK
0x2000UL
|
|
#define
|
_CMU_IFS_HFRCODIS_SHIFT
13
|
|
#define
|
_CMU_IFS_HFRCORDY_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_IFS_HFRCORDY_MASK
0x1UL
|
|
#define
|
_CMU_IFS_HFRCORDY_SHIFT
0
|
|
#define
|
_CMU_IFS_HFXOAUTOSW_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_IFS_HFXOAUTOSW_MASK
0x200UL
|
|
#define
|
_CMU_IFS_HFXOAUTOSW_SHIFT
9
|
|
#define
|
_CMU_IFS_HFXODISERR_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_IFS_HFXODISERR_MASK
0x100UL
|
|
#define
|
_CMU_IFS_HFXODISERR_SHIFT
8
|
|
#define
|
_CMU_IFS_HFXOPEAKDETERR_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_IFS_HFXOPEAKDETERR_MASK
0x400UL
|
|
#define
|
_CMU_IFS_HFXOPEAKDETERR_SHIFT
10
|
|
#define
|
_CMU_IFS_HFXOPEAKDETRDY_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_IFS_HFXOPEAKDETRDY_MASK
0x800UL
|
|
#define
|
_CMU_IFS_HFXOPEAKDETRDY_SHIFT
11
|
|
#define
|
_CMU_IFS_HFXORDY_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_IFS_HFXORDY_MASK
0x2UL
|
|
#define
|
_CMU_IFS_HFXORDY_SHIFT
1
|
|
#define
|
_CMU_IFS_HFXOSHUNTOPTRDY_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_IFS_HFXOSHUNTOPTRDY_MASK
0x1000UL
|
|
#define
|
_CMU_IFS_HFXOSHUNTOPTRDY_SHIFT
12
|
|
#define
|
_CMU_IFS_LFRCORDY_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_IFS_LFRCORDY_MASK
0x4UL
|
|
#define
|
_CMU_IFS_LFRCORDY_SHIFT
2
|
|
#define
|
_CMU_IFS_LFTIMEOUTERR_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_IFS_LFTIMEOUTERR_MASK
0x4000UL
|
|
#define
|
_CMU_IFS_LFTIMEOUTERR_SHIFT
14
|
|
#define
|
_CMU_IFS_LFXORDY_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_IFS_LFXORDY_MASK
0x8UL
|
|
#define
|
_CMU_IFS_LFXORDY_SHIFT
3
|
|
#define
|
_CMU_IFS_MASK
0x80007F7FUL
|
|
#define
|
_CMU_IFS_RESETVALUE
0x00000000UL
|
|
#define
|
_CMU_LFACLKEN0_LETIMER0_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_LFACLKEN0_LETIMER0_MASK
0x1UL
|
|
#define
|
_CMU_LFACLKEN0_LETIMER0_SHIFT
0
|
|
#define
|
_CMU_LFACLKEN0_MASK
0x00000001UL
|
|
#define
|
_CMU_LFACLKEN0_RESETVALUE
0x00000000UL
|
|
#define
|
_CMU_LFACLKSEL_LFA_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_LFACLKSEL_LFA_DISABLED
0x00000000UL
|
|
#define
|
_CMU_LFACLKSEL_LFA_LFRCO
0x00000001UL
|
|
#define
|
_CMU_LFACLKSEL_LFA_LFXO
0x00000002UL
|
|
#define
|
_CMU_LFACLKSEL_LFA_MASK
0x7UL
|
|
#define
|
_CMU_LFACLKSEL_LFA_SHIFT
0
|
|
#define
|
_CMU_LFACLKSEL_LFA_ULFRCO
0x00000004UL
|
|
#define
|
_CMU_LFACLKSEL_MASK
0x00000007UL
|
|
#define
|
_CMU_LFACLKSEL_RESETVALUE
0x00000000UL
|
|
#define
|
_CMU_LFAPRESC0_LETIMER0_DIV1
0x00000000UL
|
|
#define
|
_CMU_LFAPRESC0_LETIMER0_DIV1024
0x0000000AUL
|
|
#define
|
_CMU_LFAPRESC0_LETIMER0_DIV128
0x00000007UL
|
|
#define
|
_CMU_LFAPRESC0_LETIMER0_DIV16
0x00000004UL
|
|
#define
|
_CMU_LFAPRESC0_LETIMER0_DIV16384
0x0000000EUL
|
|
#define
|
_CMU_LFAPRESC0_LETIMER0_DIV2
0x00000001UL
|
|
#define
|
_CMU_LFAPRESC0_LETIMER0_DIV2048
0x0000000BUL
|
|
#define
|
_CMU_LFAPRESC0_LETIMER0_DIV256
0x00000008UL
|
|
#define
|
_CMU_LFAPRESC0_LETIMER0_DIV32
0x00000005UL
|
|
#define
|
_CMU_LFAPRESC0_LETIMER0_DIV32768
0x0000000FUL
|
|
#define
|
_CMU_LFAPRESC0_LETIMER0_DIV4
0x00000002UL
|
|
#define
|
_CMU_LFAPRESC0_LETIMER0_DIV4096
0x0000000CUL
|
|
#define
|
_CMU_LFAPRESC0_LETIMER0_DIV512
0x00000009UL
|
|
#define
|
_CMU_LFAPRESC0_LETIMER0_DIV64
0x00000006UL
|
|
#define
|
_CMU_LFAPRESC0_LETIMER0_DIV8
0x00000003UL
|
|
#define
|
_CMU_LFAPRESC0_LETIMER0_DIV8192
0x0000000DUL
|
|
#define
|
_CMU_LFAPRESC0_LETIMER0_MASK
0xFUL
|
|
#define
|
_CMU_LFAPRESC0_LETIMER0_SHIFT
0
|
|
#define
|
_CMU_LFAPRESC0_MASK
0x0000000FUL
|
|
#define
|
_CMU_LFAPRESC0_RESETVALUE
0x00000000UL
|
|
#define
|
_CMU_LFBCLKEN0_LEUART0_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_LFBCLKEN0_LEUART0_MASK
0x1UL
|
|
#define
|
_CMU_LFBCLKEN0_LEUART0_SHIFT
0
|
|
#define
|
_CMU_LFBCLKEN0_MASK
0x00000001UL
|
|
#define
|
_CMU_LFBCLKEN0_RESETVALUE
0x00000000UL
|
|
#define
|
_CMU_LFBCLKSEL_LFB_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_LFBCLKSEL_LFB_DISABLED
0x00000000UL
|
|
#define
|
_CMU_LFBCLKSEL_LFB_HFCLKLE
0x00000003UL
|
|
#define
|
_CMU_LFBCLKSEL_LFB_LFRCO
0x00000001UL
|
|
#define
|
_CMU_LFBCLKSEL_LFB_LFXO
0x00000002UL
|
|
#define
|
_CMU_LFBCLKSEL_LFB_MASK
0x7UL
|
|
#define
|
_CMU_LFBCLKSEL_LFB_SHIFT
0
|
|
#define
|
_CMU_LFBCLKSEL_LFB_ULFRCO
0x00000004UL
|
|
#define
|
_CMU_LFBCLKSEL_MASK
0x00000007UL
|
|
#define
|
_CMU_LFBCLKSEL_RESETVALUE
0x00000000UL
|
|
#define
|
_CMU_LFBPRESC0_LEUART0_DIV1
0x00000000UL
|
|
#define
|
_CMU_LFBPRESC0_LEUART0_DIV2
0x00000001UL
|
|
#define
|
_CMU_LFBPRESC0_LEUART0_DIV4
0x00000002UL
|
|
#define
|
_CMU_LFBPRESC0_LEUART0_DIV8
0x00000003UL
|
|
#define
|
_CMU_LFBPRESC0_LEUART0_MASK
0x3UL
|
|
#define
|
_CMU_LFBPRESC0_LEUART0_SHIFT
0
|
|
#define
|
_CMU_LFBPRESC0_MASK
0x00000003UL
|
|
#define
|
_CMU_LFBPRESC0_RESETVALUE
0x00000000UL
|
|
#define
|
_CMU_LFECLKEN0_MASK
0x00000001UL
|
|
#define
|
_CMU_LFECLKEN0_RESETVALUE
0x00000000UL
|
|
#define
|
_CMU_LFECLKEN0_RTCC_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_LFECLKEN0_RTCC_MASK
0x1UL
|
|
#define
|
_CMU_LFECLKEN0_RTCC_SHIFT
0
|
|
#define
|
_CMU_LFECLKSEL_LFE_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_LFECLKSEL_LFE_DISABLED
0x00000000UL
|
|
#define
|
_CMU_LFECLKSEL_LFE_LFRCO
0x00000001UL
|
|
#define
|
_CMU_LFECLKSEL_LFE_LFXO
0x00000002UL
|
|
#define
|
_CMU_LFECLKSEL_LFE_MASK
0x7UL
|
|
#define
|
_CMU_LFECLKSEL_LFE_SHIFT
0
|
|
#define
|
_CMU_LFECLKSEL_LFE_ULFRCO
0x00000004UL
|
|
#define
|
_CMU_LFECLKSEL_MASK
0x00000007UL
|
|
#define
|
_CMU_LFECLKSEL_RESETVALUE
0x00000000UL
|
|
#define
|
_CMU_LFEPRESC0_MASK
0x0000000FUL
|
|
#define
|
_CMU_LFEPRESC0_RESETVALUE
0x00000000UL
|
|
#define
|
_CMU_LFEPRESC0_RTCC_DIV1
0x00000000UL
|
|
#define
|
_CMU_LFEPRESC0_RTCC_MASK
0xFUL
|
|
#define
|
_CMU_LFEPRESC0_RTCC_SHIFT
0
|
|
#define
|
_CMU_LFRCOCTRL_ENCHOP_DEFAULT
0x00000001UL
|
|
#define
|
_CMU_LFRCOCTRL_ENCHOP_MASK
0x20000UL
|
|
#define
|
_CMU_LFRCOCTRL_ENCHOP_SHIFT
17
|
|
#define
|
_CMU_LFRCOCTRL_ENDEM_DEFAULT
0x00000001UL
|
|
#define
|
_CMU_LFRCOCTRL_ENDEM_MASK
0x40000UL
|
|
#define
|
_CMU_LFRCOCTRL_ENDEM_SHIFT
18
|
|
#define
|
_CMU_LFRCOCTRL_ENVREF_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_LFRCOCTRL_ENVREF_MASK
0x10000UL
|
|
#define
|
_CMU_LFRCOCTRL_ENVREF_SHIFT
16
|
|
#define
|
_CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT
0x00000008UL
|
|
#define
|
_CMU_LFRCOCTRL_GMCCURTUNE_MASK
0xF0000000UL
|
|
#define
|
_CMU_LFRCOCTRL_GMCCURTUNE_SHIFT
28
|
|
#define
|
_CMU_LFRCOCTRL_MASK
0xF30701FFUL
|
|
#define
|
_CMU_LFRCOCTRL_RESETVALUE
0x81060100UL
|
|
#define
|
_CMU_LFRCOCTRL_TIMEOUT_16CYCLES
0x00000001UL
|
|
#define
|
_CMU_LFRCOCTRL_TIMEOUT_2CYCLES
0x00000000UL
|
|
#define
|
_CMU_LFRCOCTRL_TIMEOUT_32CYCLES
0x00000002UL
|
|
#define
|
_CMU_LFRCOCTRL_TIMEOUT_DEFAULT
0x00000001UL
|
|
#define
|
_CMU_LFRCOCTRL_TIMEOUT_MASK
0x3000000UL
|
|
#define
|
_CMU_LFRCOCTRL_TIMEOUT_SHIFT
24
|
|
#define
|
_CMU_LFRCOCTRL_TUNING_DEFAULT
0x00000100UL
|
|
#define
|
_CMU_LFRCOCTRL_TUNING_MASK
0x1FFUL
|
|
#define
|
_CMU_LFRCOCTRL_TUNING_SHIFT
0
|
|
#define
|
_CMU_LFXOCTRL_AGC_DEFAULT
0x00000001UL
|
|
#define
|
_CMU_LFXOCTRL_AGC_MASK
0x8000UL
|
|
#define
|
_CMU_LFXOCTRL_AGC_SHIFT
15
|
|
#define
|
_CMU_LFXOCTRL_BUFCUR_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_LFXOCTRL_BUFCUR_MASK
0x100000UL
|
|
#define
|
_CMU_LFXOCTRL_BUFCUR_SHIFT
20
|
|
#define
|
_CMU_LFXOCTRL_CUR_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_LFXOCTRL_CUR_MASK
0x30000UL
|
|
#define
|
_CMU_LFXOCTRL_CUR_SHIFT
16
|
|
#define
|
_CMU_LFXOCTRL_GAIN_DEFAULT
0x00000002UL
|
|
#define
|
_CMU_LFXOCTRL_GAIN_MASK
0x1800UL
|
|
#define
|
_CMU_LFXOCTRL_GAIN_SHIFT
11
|
|
#define
|
_CMU_LFXOCTRL_HIGHAMPL_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_LFXOCTRL_HIGHAMPL_MASK
0x4000UL
|
|
#define
|
_CMU_LFXOCTRL_HIGHAMPL_SHIFT
14
|
|
#define
|
_CMU_LFXOCTRL_MASK
0x0713DB7FUL
|
|
#define
|
_CMU_LFXOCTRL_MODE_BUFEXTCLK
0x00000001UL
|
|
#define
|
_CMU_LFXOCTRL_MODE_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_LFXOCTRL_MODE_DIGEXTCLK
0x00000002UL
|
|
#define
|
_CMU_LFXOCTRL_MODE_MASK
0x300UL
|
|
#define
|
_CMU_LFXOCTRL_MODE_SHIFT
8
|
|
#define
|
_CMU_LFXOCTRL_MODE_XTAL
0x00000000UL
|
|
#define
|
_CMU_LFXOCTRL_RESETVALUE
0x07009000UL
|
|
#define
|
_CMU_LFXOCTRL_TIMEOUT_16KCYCLES
0x00000006UL
|
|
#define
|
_CMU_LFXOCTRL_TIMEOUT_1KCYCLES
0x00000002UL
|
|
#define
|
_CMU_LFXOCTRL_TIMEOUT_256CYCLES
0x00000001UL
|
|
#define
|
_CMU_LFXOCTRL_TIMEOUT_2CYCLES
0x00000000UL
|
|
#define
|
_CMU_LFXOCTRL_TIMEOUT_2KCYCLES
0x00000003UL
|
|
#define
|
_CMU_LFXOCTRL_TIMEOUT_32KCYCLES
0x00000007UL
|
|
#define
|
_CMU_LFXOCTRL_TIMEOUT_4KCYCLES
0x00000004UL
|
|
#define
|
_CMU_LFXOCTRL_TIMEOUT_8KCYCLES
0x00000005UL
|
|
#define
|
_CMU_LFXOCTRL_TIMEOUT_DEFAULT
0x00000007UL
|
|
#define
|
_CMU_LFXOCTRL_TIMEOUT_MASK
0x7000000UL
|
|
#define
|
_CMU_LFXOCTRL_TIMEOUT_SHIFT
24
|
|
#define
|
_CMU_LFXOCTRL_TUNING_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_LFXOCTRL_TUNING_MASK
0x7FUL
|
|
#define
|
_CMU_LFXOCTRL_TUNING_SHIFT
0
|
|
#define
|
_CMU_LOCK_LOCKKEY_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_LOCK_LOCKKEY_LOCK
0x00000000UL
|
|
#define
|
_CMU_LOCK_LOCKKEY_LOCKED
0x00000001UL
|
|
#define
|
_CMU_LOCK_LOCKKEY_MASK
0xFFFFUL
|
|
#define
|
_CMU_LOCK_LOCKKEY_SHIFT
0
|
|
#define
|
_CMU_LOCK_LOCKKEY_UNLOCK
0x0000580EUL
|
|
#define
|
_CMU_LOCK_LOCKKEY_UNLOCKED
0x00000000UL
|
|
#define
|
_CMU_LOCK_MASK
0x0000FFFFUL
|
|
#define
|
_CMU_LOCK_RESETVALUE
0x00000000UL
|
|
#define
|
_CMU_OSCENCMD_AUXHFRCODIS_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_OSCENCMD_AUXHFRCODIS_MASK
0x20UL
|
|
#define
|
_CMU_OSCENCMD_AUXHFRCODIS_SHIFT
5
|
|
#define
|
_CMU_OSCENCMD_AUXHFRCOEN_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_OSCENCMD_AUXHFRCOEN_MASK
0x10UL
|
|
#define
|
_CMU_OSCENCMD_AUXHFRCOEN_SHIFT
4
|
|
#define
|
_CMU_OSCENCMD_HFRCODIS_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_OSCENCMD_HFRCODIS_MASK
0x2UL
|
|
#define
|
_CMU_OSCENCMD_HFRCODIS_SHIFT
1
|
|
#define
|
_CMU_OSCENCMD_HFRCOEN_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_OSCENCMD_HFRCOEN_MASK
0x1UL
|
|
#define
|
_CMU_OSCENCMD_HFRCOEN_SHIFT
0
|
|
#define
|
_CMU_OSCENCMD_HFXODIS_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_OSCENCMD_HFXODIS_MASK
0x8UL
|
|
#define
|
_CMU_OSCENCMD_HFXODIS_SHIFT
3
|
|
#define
|
_CMU_OSCENCMD_HFXOEN_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_OSCENCMD_HFXOEN_MASK
0x4UL
|
|
#define
|
_CMU_OSCENCMD_HFXOEN_SHIFT
2
|
|
#define
|
_CMU_OSCENCMD_LFRCODIS_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_OSCENCMD_LFRCODIS_MASK
0x80UL
|
|
#define
|
_CMU_OSCENCMD_LFRCODIS_SHIFT
7
|
|
#define
|
_CMU_OSCENCMD_LFRCOEN_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_OSCENCMD_LFRCOEN_MASK
0x40UL
|
|
#define
|
_CMU_OSCENCMD_LFRCOEN_SHIFT
6
|
|
#define
|
_CMU_OSCENCMD_LFXODIS_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_OSCENCMD_LFXODIS_MASK
0x200UL
|
|
#define
|
_CMU_OSCENCMD_LFXODIS_SHIFT
9
|
|
#define
|
_CMU_OSCENCMD_LFXOEN_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_OSCENCMD_LFXOEN_MASK
0x100UL
|
|
#define
|
_CMU_OSCENCMD_LFXOEN_SHIFT
8
|
|
#define
|
_CMU_OSCENCMD_MASK
0x000003FFUL
|
|
#define
|
_CMU_OSCENCMD_RESETVALUE
0x00000000UL
|
|
#define
|
_CMU_PCNTCTRL_MASK
0x00000003UL
|
|
#define
|
_CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_PCNTCTRL_PCNT0CLKEN_MASK
0x1UL
|
|
#define
|
_CMU_PCNTCTRL_PCNT0CLKEN_SHIFT
0
|
|
#define
|
_CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK
0x00000000UL
|
|
#define
|
_CMU_PCNTCTRL_PCNT0CLKSEL_MASK
0x2UL
|
|
#define
|
_CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0
0x00000001UL
|
|
#define
|
_CMU_PCNTCTRL_PCNT0CLKSEL_SHIFT
1
|
|
#define
|
_CMU_PCNTCTRL_RESETVALUE
0x00000000UL
|
|
#define
|
_CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_ROUTELOC0_CLKOUT0LOC_LOC0
0x00000000UL
|
|
#define
|
_CMU_ROUTELOC0_CLKOUT0LOC_LOC1
0x00000001UL
|
|
#define
|
_CMU_ROUTELOC0_CLKOUT0LOC_LOC2
0x00000002UL
|
|
#define
|
_CMU_ROUTELOC0_CLKOUT0LOC_LOC3
0x00000003UL
|
|
#define
|
_CMU_ROUTELOC0_CLKOUT0LOC_LOC4
0x00000004UL
|
|
#define
|
_CMU_ROUTELOC0_CLKOUT0LOC_LOC5
0x00000005UL
|
|
#define
|
_CMU_ROUTELOC0_CLKOUT0LOC_LOC6
0x00000006UL
|
|
#define
|
_CMU_ROUTELOC0_CLKOUT0LOC_LOC7
0x00000007UL
|
|
#define
|
_CMU_ROUTELOC0_CLKOUT0LOC_MASK
0x7UL
|
|
#define
|
_CMU_ROUTELOC0_CLKOUT0LOC_SHIFT
0
|
|
#define
|
_CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_ROUTELOC0_CLKOUT1LOC_LOC0
0x00000000UL
|
|
#define
|
_CMU_ROUTELOC0_CLKOUT1LOC_LOC1
0x00000001UL
|
|
#define
|
_CMU_ROUTELOC0_CLKOUT1LOC_LOC2
0x00000002UL
|
|
#define
|
_CMU_ROUTELOC0_CLKOUT1LOC_LOC3
0x00000003UL
|
|
#define
|
_CMU_ROUTELOC0_CLKOUT1LOC_LOC4
0x00000004UL
|
|
#define
|
_CMU_ROUTELOC0_CLKOUT1LOC_LOC5
0x00000005UL
|
|
#define
|
_CMU_ROUTELOC0_CLKOUT1LOC_LOC6
0x00000006UL
|
|
#define
|
_CMU_ROUTELOC0_CLKOUT1LOC_LOC7
0x00000007UL
|
|
#define
|
_CMU_ROUTELOC0_CLKOUT1LOC_MASK
0x700UL
|
|
#define
|
_CMU_ROUTELOC0_CLKOUT1LOC_SHIFT
8
|
|
#define
|
_CMU_ROUTELOC0_MASK
0x00000707UL
|
|
#define
|
_CMU_ROUTELOC0_RESETVALUE
0x00000000UL
|
|
#define
|
_CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_ROUTEPEN_CLKOUT0PEN_MASK
0x1UL
|
|
#define
|
_CMU_ROUTEPEN_CLKOUT0PEN_SHIFT
0
|
|
#define
|
_CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_ROUTEPEN_CLKOUT1PEN_MASK
0x2UL
|
|
#define
|
_CMU_ROUTEPEN_CLKOUT1PEN_SHIFT
1
|
|
#define
|
_CMU_ROUTEPEN_MASK
0x00000003UL
|
|
#define
|
_CMU_ROUTEPEN_RESETVALUE
0x00000000UL
|
|
#define
|
_CMU_STATUS_AUXHFRCOENS_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_STATUS_AUXHFRCOENS_MASK
0x10UL
|
|
#define
|
_CMU_STATUS_AUXHFRCOENS_SHIFT
4
|
|
#define
|
_CMU_STATUS_AUXHFRCORDY_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_STATUS_AUXHFRCORDY_MASK
0x20UL
|
|
#define
|
_CMU_STATUS_AUXHFRCORDY_SHIFT
5
|
|
#define
|
_CMU_STATUS_CALRDY_DEFAULT
0x00000001UL
|
|
#define
|
_CMU_STATUS_CALRDY_MASK
0x10000UL
|
|
#define
|
_CMU_STATUS_CALRDY_SHIFT
16
|
|
#define
|
_CMU_STATUS_HFRCOENS_DEFAULT
0x00000001UL
|
|
#define
|
_CMU_STATUS_HFRCOENS_MASK
0x1UL
|
|
#define
|
_CMU_STATUS_HFRCOENS_SHIFT
0
|
|
#define
|
_CMU_STATUS_HFRCORDY_DEFAULT
0x00000001UL
|
|
#define
|
_CMU_STATUS_HFRCORDY_MASK
0x2UL
|
|
#define
|
_CMU_STATUS_HFRCORDY_SHIFT
1
|
|
#define
|
_CMU_STATUS_HFXOAMPHIGH_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_STATUS_HFXOAMPHIGH_MASK
0x1000000UL
|
|
#define
|
_CMU_STATUS_HFXOAMPHIGH_SHIFT
24
|
|
#define
|
_CMU_STATUS_HFXOAMPLOW_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_STATUS_HFXOAMPLOW_MASK
0x2000000UL
|
|
#define
|
_CMU_STATUS_HFXOAMPLOW_SHIFT
25
|
|
#define
|
_CMU_STATUS_HFXOENS_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_STATUS_HFXOENS_MASK
0x4UL
|
|
#define
|
_CMU_STATUS_HFXOENS_SHIFT
2
|
|
#define
|
_CMU_STATUS_HFXOPEAKDETRDY_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_STATUS_HFXOPEAKDETRDY_MASK
0x400000UL
|
|
#define
|
_CMU_STATUS_HFXOPEAKDETRDY_SHIFT
22
|
|
#define
|
_CMU_STATUS_HFXORDY_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_STATUS_HFXORDY_MASK
0x8UL
|
|
#define
|
_CMU_STATUS_HFXORDY_SHIFT
3
|
|
#define
|
_CMU_STATUS_HFXOREGILOW_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_STATUS_HFXOREGILOW_MASK
0x4000000UL
|
|
#define
|
_CMU_STATUS_HFXOREGILOW_SHIFT
26
|
|
#define
|
_CMU_STATUS_HFXOREQ_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_STATUS_HFXOREQ_MASK
0x200000UL
|
|
#define
|
_CMU_STATUS_HFXOREQ_SHIFT
21
|
|
#define
|
_CMU_STATUS_HFXOSHUNTOPTRDY_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_STATUS_HFXOSHUNTOPTRDY_MASK
0x800000UL
|
|
#define
|
_CMU_STATUS_HFXOSHUNTOPTRDY_SHIFT
23
|
|
#define
|
_CMU_STATUS_LFRCOENS_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_STATUS_LFRCOENS_MASK
0x40UL
|
|
#define
|
_CMU_STATUS_LFRCOENS_SHIFT
6
|
|
#define
|
_CMU_STATUS_LFRCORDY_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_STATUS_LFRCORDY_MASK
0x80UL
|
|
#define
|
_CMU_STATUS_LFRCORDY_SHIFT
7
|
|
#define
|
_CMU_STATUS_LFXOENS_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_STATUS_LFXOENS_MASK
0x100UL
|
|
#define
|
_CMU_STATUS_LFXOENS_SHIFT
8
|
|
#define
|
_CMU_STATUS_LFXORDY_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_STATUS_LFXORDY_MASK
0x200UL
|
|
#define
|
_CMU_STATUS_LFXORDY_SHIFT
9
|
|
#define
|
_CMU_STATUS_MASK
0x07E103FFUL
|
|
#define
|
_CMU_STATUS_RESETVALUE
0x00010003UL
|
|
#define
|
_CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_SYNCBUSY_AUXHFRCOBSY_MASK
0x2000000UL
|
|
#define
|
_CMU_SYNCBUSY_AUXHFRCOBSY_SHIFT
25
|
|
#define
|
_CMU_SYNCBUSY_HFRCOBSY_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_SYNCBUSY_HFRCOBSY_MASK
0x1000000UL
|
|
#define
|
_CMU_SYNCBUSY_HFRCOBSY_SHIFT
24
|
|
#define
|
_CMU_SYNCBUSY_HFXOBSY_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_SYNCBUSY_HFXOBSY_MASK
0x10000000UL
|
|
#define
|
_CMU_SYNCBUSY_HFXOBSY_SHIFT
28
|
|
#define
|
_CMU_SYNCBUSY_LFACLKEN0_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_SYNCBUSY_LFACLKEN0_MASK
0x1UL
|
|
#define
|
_CMU_SYNCBUSY_LFACLKEN0_SHIFT
0
|
|
#define
|
_CMU_SYNCBUSY_LFAPRESC0_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_SYNCBUSY_LFAPRESC0_MASK
0x4UL
|
|
#define
|
_CMU_SYNCBUSY_LFAPRESC0_SHIFT
2
|
|
#define
|
_CMU_SYNCBUSY_LFBCLKEN0_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_SYNCBUSY_LFBCLKEN0_MASK
0x10UL
|
|
#define
|
_CMU_SYNCBUSY_LFBCLKEN0_SHIFT
4
|
|
#define
|
_CMU_SYNCBUSY_LFBPRESC0_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_SYNCBUSY_LFBPRESC0_MASK
0x40UL
|
|
#define
|
_CMU_SYNCBUSY_LFBPRESC0_SHIFT
6
|
|
#define
|
_CMU_SYNCBUSY_LFECLKEN0_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_SYNCBUSY_LFECLKEN0_MASK
0x10000UL
|
|
#define
|
_CMU_SYNCBUSY_LFECLKEN0_SHIFT
16
|
|
#define
|
_CMU_SYNCBUSY_LFEPRESC0_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_SYNCBUSY_LFEPRESC0_MASK
0x40000UL
|
|
#define
|
_CMU_SYNCBUSY_LFEPRESC0_SHIFT
18
|
|
#define
|
_CMU_SYNCBUSY_LFRCOBSY_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_SYNCBUSY_LFRCOBSY_MASK
0x4000000UL
|
|
#define
|
_CMU_SYNCBUSY_LFRCOBSY_SHIFT
26
|
|
#define
|
_CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_SYNCBUSY_LFRCOVREFBSY_MASK
0x8000000UL
|
|
#define
|
_CMU_SYNCBUSY_LFRCOVREFBSY_SHIFT
27
|
|
#define
|
_CMU_SYNCBUSY_LFXOBSY_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_SYNCBUSY_LFXOBSY_MASK
0x20000000UL
|
|
#define
|
_CMU_SYNCBUSY_LFXOBSY_SHIFT
29
|
|
#define
|
_CMU_SYNCBUSY_MASK
0x3F050055UL
|
|
#define
|
_CMU_SYNCBUSY_RESETVALUE
0x00000000UL
|
|
#define
|
_CMU_ULFRCOCTRL_MASK
0x00030C3FUL
|
|
#define
|
_CMU_ULFRCOCTRL_MODE_1KHZ
0x00000000UL
|
|
#define
|
_CMU_ULFRCOCTRL_MODE_2KHZ
0x00000001UL
|
|
#define
|
_CMU_ULFRCOCTRL_MODE_32KHZ
0x00000003UL
|
|
#define
|
_CMU_ULFRCOCTRL_MODE_4KHZ
0x00000002UL
|
|
#define
|
_CMU_ULFRCOCTRL_MODE_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_ULFRCOCTRL_MODE_MASK
0xC00UL
|
|
#define
|
_CMU_ULFRCOCTRL_MODE_SHIFT
10
|
|
#define
|
_CMU_ULFRCOCTRL_RESETVALUE
0x00020020UL
|
|
#define
|
_CMU_ULFRCOCTRL_RESTRIM_DEFAULT
0x00000002UL
|
|
#define
|
_CMU_ULFRCOCTRL_RESTRIM_MASK
0x30000UL
|
|
#define
|
_CMU_ULFRCOCTRL_RESTRIM_SHIFT
16
|
|
#define
|
_CMU_ULFRCOCTRL_TUNING_DEFAULT
0x00000020UL
|
|
#define
|
_CMU_ULFRCOCTRL_TUNING_MASK
0x3FUL
|
|
#define
|
_CMU_ULFRCOCTRL_TUNING_SHIFT
0
|
|
#define
|
CMU_ADCCTRL_ADC0CLKINV
(0x1UL << 8)
|
|
#define
|
CMU_ADCCTRL_ADC0CLKINV_DEFAULT
(
_CMU_ADCCTRL_ADC0CLKINV_DEFAULT
<< 8)
|
|
#define
|
CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO
(
_CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO
<< 4)
|
|
#define
|
CMU_ADCCTRL_ADC0CLKSEL_DEFAULT
(
_CMU_ADCCTRL_ADC0CLKSEL_DEFAULT
<< 4)
|
|
#define
|
CMU_ADCCTRL_ADC0CLKSEL_DISABLED
(
_CMU_ADCCTRL_ADC0CLKSEL_DISABLED
<< 4)
|
|
#define
|
CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK
(
_CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK
<< 4)
|
|
#define
|
CMU_ADCCTRL_ADC0CLKSEL_HFXO
(
_CMU_ADCCTRL_ADC0CLKSEL_HFXO
<< 4)
|
|
#define
|
CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT
(
_CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT
<< 25)
|
|
#define
|
CMU_AUXHFRCOCTRL_CLKDIV_DIV1
(
_CMU_AUXHFRCOCTRL_CLKDIV_DIV1
<< 25)
|
|
#define
|
CMU_AUXHFRCOCTRL_CLKDIV_DIV2
(
_CMU_AUXHFRCOCTRL_CLKDIV_DIV2
<< 25)
|
|
#define
|
CMU_AUXHFRCOCTRL_CLKDIV_DIV4
(
_CMU_AUXHFRCOCTRL_CLKDIV_DIV4
<< 25)
|
|
#define
|
CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT
(
_CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT
<< 21)
|
|
#define
|
CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT
(
_CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT
<< 8)
|
|
#define
|
CMU_AUXHFRCOCTRL_FINETUNINGEN
(0x1UL << 27)
|
|
#define
|
CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT
(
_CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT
<< 27)
|
|
#define
|
CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT
(
_CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT
<< 16)
|
|
#define
|
CMU_AUXHFRCOCTRL_LDOHP
(0x1UL << 24)
|
|
#define
|
CMU_AUXHFRCOCTRL_LDOHP_DEFAULT
(
_CMU_AUXHFRCOCTRL_LDOHP_DEFAULT
<< 24)
|
|
#define
|
CMU_AUXHFRCOCTRL_TUNING_DEFAULT
(
_CMU_AUXHFRCOCTRL_TUNING_DEFAULT
<< 0)
|
|
#define
|
CMU_AUXHFRCOCTRL_VREFTC_DEFAULT
(
_CMU_AUXHFRCOCTRL_VREFTC_DEFAULT
<< 28)
|
|
#define
|
CMU_CALCNT_CALCNT_DEFAULT
(
_CMU_CALCNT_CALCNT_DEFAULT
<< 0)
|
|
#define
|
CMU_CALCTRL_CONT
(0x1UL << 8)
|
|
#define
|
CMU_CALCTRL_CONT_DEFAULT
(
_CMU_CALCTRL_CONT_DEFAULT
<< 8)
|
|
#define
|
CMU_CALCTRL_DOWNSEL_AUXHFRCO
(
_CMU_CALCTRL_DOWNSEL_AUXHFRCO
<< 4)
|
|
#define
|
CMU_CALCTRL_DOWNSEL_DEFAULT
(
_CMU_CALCTRL_DOWNSEL_DEFAULT
<< 4)
|
|
#define
|
CMU_CALCTRL_DOWNSEL_HFCLK
(
_CMU_CALCTRL_DOWNSEL_HFCLK
<< 4)
|
|
#define
|
CMU_CALCTRL_DOWNSEL_HFRCO
(
_CMU_CALCTRL_DOWNSEL_HFRCO
<< 4)
|
|
#define
|
CMU_CALCTRL_DOWNSEL_HFXO
(
_CMU_CALCTRL_DOWNSEL_HFXO
<< 4)
|
|
#define
|
CMU_CALCTRL_DOWNSEL_LFRCO
(
_CMU_CALCTRL_DOWNSEL_LFRCO
<< 4)
|
|
#define
|
CMU_CALCTRL_DOWNSEL_LFXO
(
_CMU_CALCTRL_DOWNSEL_LFXO
<< 4)
|
|
#define
|
CMU_CALCTRL_DOWNSEL_PRS
(
_CMU_CALCTRL_DOWNSEL_PRS
<< 4)
|
|
#define
|
CMU_CALCTRL_PRSDOWNSEL_DEFAULT
(
_CMU_CALCTRL_PRSDOWNSEL_DEFAULT
<< 24)
|
|
#define
|
CMU_CALCTRL_PRSDOWNSEL_PRSCH0
(
_CMU_CALCTRL_PRSDOWNSEL_PRSCH0
<< 24)
|
|
#define
|
CMU_CALCTRL_PRSDOWNSEL_PRSCH1
(
_CMU_CALCTRL_PRSDOWNSEL_PRSCH1
<< 24)
|
|
#define
|
CMU_CALCTRL_PRSDOWNSEL_PRSCH10
(
_CMU_CALCTRL_PRSDOWNSEL_PRSCH10
<< 24)
|
|
#define
|
CMU_CALCTRL_PRSDOWNSEL_PRSCH11
(
_CMU_CALCTRL_PRSDOWNSEL_PRSCH11
<< 24)
|
|
#define
|
CMU_CALCTRL_PRSDOWNSEL_PRSCH2
(
_CMU_CALCTRL_PRSDOWNSEL_PRSCH2
<< 24)
|
|
#define
|
CMU_CALCTRL_PRSDOWNSEL_PRSCH3
(
_CMU_CALCTRL_PRSDOWNSEL_PRSCH3
<< 24)
|
|
#define
|
CMU_CALCTRL_PRSDOWNSEL_PRSCH4
(
_CMU_CALCTRL_PRSDOWNSEL_PRSCH4
<< 24)
|
|
#define
|
CMU_CALCTRL_PRSDOWNSEL_PRSCH5
(
_CMU_CALCTRL_PRSDOWNSEL_PRSCH5
<< 24)
|
|
#define
|
CMU_CALCTRL_PRSDOWNSEL_PRSCH6
(
_CMU_CALCTRL_PRSDOWNSEL_PRSCH6
<< 24)
|
|
#define
|
CMU_CALCTRL_PRSDOWNSEL_PRSCH7
(
_CMU_CALCTRL_PRSDOWNSEL_PRSCH7
<< 24)
|
|
#define
|
CMU_CALCTRL_PRSDOWNSEL_PRSCH8
(
_CMU_CALCTRL_PRSDOWNSEL_PRSCH8
<< 24)
|
|
#define
|
CMU_CALCTRL_PRSDOWNSEL_PRSCH9
(
_CMU_CALCTRL_PRSDOWNSEL_PRSCH9
<< 24)
|
|
#define
|
CMU_CALCTRL_PRSUPSEL_DEFAULT
(
_CMU_CALCTRL_PRSUPSEL_DEFAULT
<< 16)
|
|
#define
|
CMU_CALCTRL_PRSUPSEL_PRSCH0
(
_CMU_CALCTRL_PRSUPSEL_PRSCH0
<< 16)
|
|
#define
|
CMU_CALCTRL_PRSUPSEL_PRSCH1
(
_CMU_CALCTRL_PRSUPSEL_PRSCH1
<< 16)
|
|
|