CoreDevices > EFM32PG1B200F256GM48

Detailed Description

Processor and Core Peripheral Section.

Macros

#define __FPU_PRESENT   1
 
#define __MPU_PRESENT   1
 
#define __NVIC_PRIO_BITS   3
 
#define __Vendor_SysTickConfig   0
 
#define __VTOR_PRESENT   1
 

Macro Definition Documentation

#define __FPU_PRESENT   1

Presence of FPU

Definition at line 104 of file efm32pg1b200f256gm48.h.

#define __MPU_PRESENT   1

Presence of MPU

Definition at line 103 of file efm32pg1b200f256gm48.h.

#define __NVIC_PRIO_BITS   3

NVIC interrupt priority bits

Definition at line 106 of file efm32pg1b200f256gm48.h.

Referenced by CORE_AtomicDisableIrq(), CORE_EnterAtomic(), CORE_IrqIsBlocked(), CORE_IrqIsDisabled(), CORE_YieldAtomic(), and LDMA_Init().

#define __Vendor_SysTickConfig   0

Is 1 if different SysTick counter is used

Definition at line 107 of file efm32pg1b200f256gm48.h.

#define __VTOR_PRESENT   1

Presence of VTOR register in SCB

Definition at line 105 of file efm32pg1b200f256gm48.h.