CMU Bit FieldsDevices > CMU

Macros

#define _CMU_ADCCTRL_ADC0CLKINV_DEFAULT   0x00000000UL
 
#define _CMU_ADCCTRL_ADC0CLKINV_MASK   0x100UL
 
#define _CMU_ADCCTRL_ADC0CLKINV_SHIFT   8
 
#define _CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO   0x00000001UL
 
#define _CMU_ADCCTRL_ADC0CLKSEL_DEFAULT   0x00000000UL
 
#define _CMU_ADCCTRL_ADC0CLKSEL_DISABLED   0x00000000UL
 
#define _CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK   0x00000003UL
 
#define _CMU_ADCCTRL_ADC0CLKSEL_HFXO   0x00000002UL
 
#define _CMU_ADCCTRL_ADC0CLKSEL_MASK   0x30UL
 
#define _CMU_ADCCTRL_ADC0CLKSEL_SHIFT   4
 
#define _CMU_ADCCTRL_MASK   0x00000130UL
 
#define _CMU_ADCCTRL_RESETVALUE   0x00000000UL
 
#define _CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT   0x00000000UL
 
#define _CMU_AUXHFRCOCTRL_CLKDIV_DIV1   0x00000000UL
 
#define _CMU_AUXHFRCOCTRL_CLKDIV_DIV2   0x00000001UL
 
#define _CMU_AUXHFRCOCTRL_CLKDIV_DIV4   0x00000002UL
 
#define _CMU_AUXHFRCOCTRL_CLKDIV_MASK   0x6000000UL
 
#define _CMU_AUXHFRCOCTRL_CLKDIV_SHIFT   25
 
#define _CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT   0x00000002UL
 
#define _CMU_AUXHFRCOCTRL_CMPBIAS_MASK   0xE00000UL
 
#define _CMU_AUXHFRCOCTRL_CMPBIAS_SHIFT   21
 
#define _CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT   0x0000001FUL
 
#define _CMU_AUXHFRCOCTRL_FINETUNING_MASK   0x3F00UL
 
#define _CMU_AUXHFRCOCTRL_FINETUNING_SHIFT   8
 
#define _CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT   0x00000000UL
 
#define _CMU_AUXHFRCOCTRL_FINETUNINGEN_MASK   0x8000000UL
 
#define _CMU_AUXHFRCOCTRL_FINETUNINGEN_SHIFT   27
 
#define _CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT   0x00000008UL
 
#define _CMU_AUXHFRCOCTRL_FREQRANGE_MASK   0x1F0000UL
 
#define _CMU_AUXHFRCOCTRL_FREQRANGE_SHIFT   16
 
#define _CMU_AUXHFRCOCTRL_LDOHP_DEFAULT   0x00000001UL
 
#define _CMU_AUXHFRCOCTRL_LDOHP_MASK   0x1000000UL
 
#define _CMU_AUXHFRCOCTRL_LDOHP_SHIFT   24
 
#define _CMU_AUXHFRCOCTRL_MASK   0xFFFF3F7FUL
 
#define _CMU_AUXHFRCOCTRL_RESETVALUE   0xB1481F3CUL
 
#define _CMU_AUXHFRCOCTRL_TUNING_DEFAULT   0x0000003CUL
 
#define _CMU_AUXHFRCOCTRL_TUNING_MASK   0x7FUL
 
#define _CMU_AUXHFRCOCTRL_TUNING_SHIFT   0
 
#define _CMU_AUXHFRCOCTRL_VREFTC_DEFAULT   0x0000000BUL
 
#define _CMU_AUXHFRCOCTRL_VREFTC_MASK   0xF0000000UL
 
#define _CMU_AUXHFRCOCTRL_VREFTC_SHIFT   28
 
#define _CMU_CALCNT_CALCNT_DEFAULT   0x00000000UL
 
#define _CMU_CALCNT_CALCNT_MASK   0xFFFFFUL
 
#define _CMU_CALCNT_CALCNT_SHIFT   0
 
#define _CMU_CALCNT_MASK   0x000FFFFFUL
 
#define _CMU_CALCNT_RESETVALUE   0x00000000UL
 
#define _CMU_CALCTRL_CONT_DEFAULT   0x00000000UL
 
#define _CMU_CALCTRL_CONT_MASK   0x100UL
 
#define _CMU_CALCTRL_CONT_SHIFT   8
 
#define _CMU_CALCTRL_DOWNSEL_AUXHFRCO   0x00000005UL
 
#define _CMU_CALCTRL_DOWNSEL_DEFAULT   0x00000000UL
 
#define _CMU_CALCTRL_DOWNSEL_HFCLK   0x00000000UL
 
#define _CMU_CALCTRL_DOWNSEL_HFRCO   0x00000003UL
 
#define _CMU_CALCTRL_DOWNSEL_HFXO   0x00000001UL
 
#define _CMU_CALCTRL_DOWNSEL_LFRCO   0x00000004UL
 
#define _CMU_CALCTRL_DOWNSEL_LFXO   0x00000002UL
 
#define _CMU_CALCTRL_DOWNSEL_MASK   0x70UL
 
#define _CMU_CALCTRL_DOWNSEL_PRS   0x00000006UL
 
#define _CMU_CALCTRL_DOWNSEL_SHIFT   4
 
#define _CMU_CALCTRL_MASK   0x0F0F0177UL
 
#define _CMU_CALCTRL_PRSDOWNSEL_DEFAULT   0x00000000UL
 
#define _CMU_CALCTRL_PRSDOWNSEL_MASK   0xF000000UL
 
#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH0   0x00000000UL
 
#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH1   0x00000001UL
 
#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH10   0x0000000AUL
 
#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH11   0x0000000BUL
 
#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH2   0x00000002UL
 
#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH3   0x00000003UL
 
#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH4   0x00000004UL
 
#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH5   0x00000005UL
 
#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH6   0x00000006UL
 
#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH7   0x00000007UL
 
#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH8   0x00000008UL
 
#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH9   0x00000009UL
 
#define _CMU_CALCTRL_PRSDOWNSEL_SHIFT   24
 
#define _CMU_CALCTRL_PRSUPSEL_DEFAULT   0x00000000UL
 
#define _CMU_CALCTRL_PRSUPSEL_MASK   0xF0000UL
 
#define _CMU_CALCTRL_PRSUPSEL_PRSCH0   0x00000000UL
 
#define _CMU_CALCTRL_PRSUPSEL_PRSCH1   0x00000001UL
 
#define _CMU_CALCTRL_PRSUPSEL_PRSCH10   0x0000000AUL
 
#define _CMU_CALCTRL_PRSUPSEL_PRSCH11   0x0000000BUL
 
#define _CMU_CALCTRL_PRSUPSEL_PRSCH2   0x00000002UL
 
#define _CMU_CALCTRL_PRSUPSEL_PRSCH3   0x00000003UL
 
#define _CMU_CALCTRL_PRSUPSEL_PRSCH4   0x00000004UL
 
#define _CMU_CALCTRL_PRSUPSEL_PRSCH5   0x00000005UL
 
#define _CMU_CALCTRL_PRSUPSEL_PRSCH6   0x00000006UL
 
#define _CMU_CALCTRL_PRSUPSEL_PRSCH7   0x00000007UL
 
#define _CMU_CALCTRL_PRSUPSEL_PRSCH8   0x00000008UL
 
#define _CMU_CALCTRL_PRSUPSEL_PRSCH9   0x00000009UL
 
#define _CMU_CALCTRL_PRSUPSEL_SHIFT   16
 
#define _CMU_CALCTRL_RESETVALUE   0x00000000UL
 
#define _CMU_CALCTRL_UPSEL_AUXHFRCO   0x00000004UL
 
#define _CMU_CALCTRL_UPSEL_DEFAULT   0x00000000UL
 
#define _CMU_CALCTRL_UPSEL_HFRCO   0x00000002UL
 
#define _CMU_CALCTRL_UPSEL_HFXO   0x00000000UL
 
#define _CMU_CALCTRL_UPSEL_LFRCO   0x00000003UL
 
#define _CMU_CALCTRL_UPSEL_LFXO   0x00000001UL
 
#define _CMU_CALCTRL_UPSEL_MASK   0x7UL
 
#define _CMU_CALCTRL_UPSEL_PRS   0x00000005UL
 
#define _CMU_CALCTRL_UPSEL_SHIFT   0
 
#define _CMU_CMD_CALSTART_DEFAULT   0x00000000UL
 
#define _CMU_CMD_CALSTART_MASK   0x1UL
 
#define _CMU_CMD_CALSTART_SHIFT   0
 
#define _CMU_CMD_CALSTOP_DEFAULT   0x00000000UL
 
#define _CMU_CMD_CALSTOP_MASK   0x2UL
 
#define _CMU_CMD_CALSTOP_SHIFT   1
 
#define _CMU_CMD_HFXOPEAKDETSTART_DEFAULT   0x00000000UL
 
#define _CMU_CMD_HFXOPEAKDETSTART_MASK   0x10UL
 
#define _CMU_CMD_HFXOPEAKDETSTART_SHIFT   4
 
#define _CMU_CMD_HFXOSHUNTOPTSTART_DEFAULT   0x00000000UL
 
#define _CMU_CMD_HFXOSHUNTOPTSTART_MASK   0x20UL
 
#define _CMU_CMD_HFXOSHUNTOPTSTART_SHIFT   5
 
#define _CMU_CMD_MASK   0x00000033UL
 
#define _CMU_CMD_RESETVALUE   0x00000000UL
 
#define _CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ   0x0000000DUL
 
#define _CMU_CTRL_CLKOUTSEL0_DEFAULT   0x00000000UL
 
#define _CMU_CTRL_CLKOUTSEL0_DISABLED   0x00000000UL
 
#define _CMU_CTRL_CLKOUTSEL0_HFEXPCLK   0x00000007UL
 
#define _CMU_CTRL_CLKOUTSEL0_HFRCOQ   0x0000000CUL
 
#define _CMU_CTRL_CLKOUTSEL0_HFSRCCLK   0x0000000FUL
 
#define _CMU_CTRL_CLKOUTSEL0_HFXO   0x00000006UL
 
#define _CMU_CTRL_CLKOUTSEL0_HFXOQ   0x0000000EUL
 
#define _CMU_CTRL_CLKOUTSEL0_LFRCO   0x00000002UL
 
#define _CMU_CTRL_CLKOUTSEL0_LFRCOQ   0x0000000AUL
 
#define _CMU_CTRL_CLKOUTSEL0_LFXO   0x00000003UL
 
#define _CMU_CTRL_CLKOUTSEL0_LFXOQ   0x0000000BUL
 
#define _CMU_CTRL_CLKOUTSEL0_MASK   0xFUL
 
#define _CMU_CTRL_CLKOUTSEL0_SHIFT   0
 
#define _CMU_CTRL_CLKOUTSEL0_ULFRCO   0x00000001UL
 
#define _CMU_CTRL_CLKOUTSEL0_ULFRCOQ   0x00000009UL
 
#define _CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ   0x0000000DUL
 
#define _CMU_CTRL_CLKOUTSEL1_DEFAULT   0x00000000UL
 
#define _CMU_CTRL_CLKOUTSEL1_DISABLED   0x00000000UL
 
#define _CMU_CTRL_CLKOUTSEL1_HFEXPCLK   0x00000007UL
 
#define _CMU_CTRL_CLKOUTSEL1_HFRCOQ   0x0000000CUL
 
#define _CMU_CTRL_CLKOUTSEL1_HFSRCCLK   0x0000000FUL
 
#define _CMU_CTRL_CLKOUTSEL1_HFXO   0x00000006UL
 
#define _CMU_CTRL_CLKOUTSEL1_HFXOQ   0x0000000EUL
 
#define _CMU_CTRL_CLKOUTSEL1_LFRCO   0x00000002UL
 
#define _CMU_CTRL_CLKOUTSEL1_LFRCOQ   0x0000000AUL
 
#define _CMU_CTRL_CLKOUTSEL1_LFXO   0x00000003UL
 
#define _CMU_CTRL_CLKOUTSEL1_LFXOQ   0x0000000BUL
 
#define _CMU_CTRL_CLKOUTSEL1_MASK   0x1E0UL
 
#define _CMU_CTRL_CLKOUTSEL1_SHIFT   5
 
#define _CMU_CTRL_CLKOUTSEL1_ULFRCO   0x00000001UL
 
#define _CMU_CTRL_CLKOUTSEL1_ULFRCOQ   0x00000009UL
 
#define _CMU_CTRL_HFPERCLKEN_DEFAULT   0x00000001UL
 
#define _CMU_CTRL_HFPERCLKEN_MASK   0x100000UL
 
#define _CMU_CTRL_HFPERCLKEN_SHIFT   20
 
#define _CMU_CTRL_MASK   0x001101EFUL
 
#define _CMU_CTRL_RESETVALUE   0x00300000UL
 
#define _CMU_CTRL_WSHFLE_DEFAULT   0x00000000UL
 
#define _CMU_CTRL_WSHFLE_MASK   0x10000UL
 
#define _CMU_CTRL_WSHFLE_SHIFT   16
 
#define _CMU_DBGCLKSEL_DBG_AUXHFRCO   0x00000000UL
 
#define _CMU_DBGCLKSEL_DBG_DEFAULT   0x00000000UL
 
#define _CMU_DBGCLKSEL_DBG_HFCLK   0x00000001UL
 
#define _CMU_DBGCLKSEL_DBG_MASK   0x1UL
 
#define _CMU_DBGCLKSEL_DBG_SHIFT   0
 
#define _CMU_DBGCLKSEL_MASK   0x00000001UL
 
#define _CMU_DBGCLKSEL_RESETVALUE   0x00000000UL
 
#define _CMU_FREEZE_MASK   0x00000001UL
 
#define _CMU_FREEZE_REGFREEZE_DEFAULT   0x00000000UL
 
#define _CMU_FREEZE_REGFREEZE_FREEZE   0x00000001UL
 
#define _CMU_FREEZE_REGFREEZE_MASK   0x1UL
 
#define _CMU_FREEZE_REGFREEZE_SHIFT   0
 
#define _CMU_FREEZE_REGFREEZE_UPDATE   0x00000000UL
 
#define _CMU_FREEZE_RESETVALUE   0x00000000UL
 
#define _CMU_HFBUSCLKEN0_CRYPTO_DEFAULT   0x00000000UL
 
#define _CMU_HFBUSCLKEN0_CRYPTO_MASK   0x2UL
 
#define _CMU_HFBUSCLKEN0_CRYPTO_SHIFT   1
 
#define _CMU_HFBUSCLKEN0_GPCRC_DEFAULT   0x00000000UL
 
#define _CMU_HFBUSCLKEN0_GPCRC_MASK   0x20UL
 
#define _CMU_HFBUSCLKEN0_GPCRC_SHIFT   5
 
#define _CMU_HFBUSCLKEN0_GPIO_DEFAULT   0x00000000UL
 
#define _CMU_HFBUSCLKEN0_GPIO_MASK   0x4UL
 
#define _CMU_HFBUSCLKEN0_GPIO_SHIFT   2
 
#define _CMU_HFBUSCLKEN0_LDMA_DEFAULT   0x00000000UL
 
#define _CMU_HFBUSCLKEN0_LDMA_MASK   0x10UL
 
#define _CMU_HFBUSCLKEN0_LDMA_SHIFT   4
 
#define _CMU_HFBUSCLKEN0_LE_DEFAULT   0x00000000UL
 
#define _CMU_HFBUSCLKEN0_LE_MASK   0x1UL
 
#define _CMU_HFBUSCLKEN0_LE_SHIFT   0
 
#define _CMU_HFBUSCLKEN0_MASK   0x0000003FUL
 
#define _CMU_HFBUSCLKEN0_PRS_DEFAULT   0x00000000UL
 
#define _CMU_HFBUSCLKEN0_PRS_MASK   0x8UL
 
#define _CMU_HFBUSCLKEN0_PRS_SHIFT   3
 
#define _CMU_HFBUSCLKEN0_RESETVALUE   0x00000000UL
 
#define _CMU_HFCLKSEL_HF_DEFAULT   0x00000000UL
 
#define _CMU_HFCLKSEL_HF_HFRCO   0x00000001UL
 
#define _CMU_HFCLKSEL_HF_HFXO   0x00000002UL
 
#define _CMU_HFCLKSEL_HF_LFRCO   0x00000003UL
 
#define _CMU_HFCLKSEL_HF_LFXO   0x00000004UL
 
#define _CMU_HFCLKSEL_HF_MASK   0x7UL
 
#define _CMU_HFCLKSEL_HF_SHIFT   0
 
#define _CMU_HFCLKSEL_MASK   0x00000007UL
 
#define _CMU_HFCLKSEL_RESETVALUE   0x00000000UL
 
#define _CMU_HFCLKSTATUS_MASK   0x00000007UL
 
#define _CMU_HFCLKSTATUS_RESETVALUE   0x00000001UL
 
#define _CMU_HFCLKSTATUS_SELECTED_DEFAULT   0x00000001UL
 
#define _CMU_HFCLKSTATUS_SELECTED_HFRCO   0x00000001UL
 
#define _CMU_HFCLKSTATUS_SELECTED_HFXO   0x00000002UL
 
#define _CMU_HFCLKSTATUS_SELECTED_LFRCO   0x00000003UL
 
#define _CMU_HFCLKSTATUS_SELECTED_LFXO   0x00000004UL
 
#define _CMU_HFCLKSTATUS_SELECTED_MASK   0x7UL
 
#define _CMU_HFCLKSTATUS_SELECTED_SHIFT   0
 
#define _CMU_HFCOREPRESC_MASK   0x0001FF00UL
 
#define _CMU_HFCOREPRESC_PRESC_DEFAULT   0x00000000UL
 
#define _CMU_HFCOREPRESC_PRESC_MASK   0x1FF00UL
 
#define _CMU_HFCOREPRESC_PRESC_NODIVISION   0x00000000UL
 
#define _CMU_HFCOREPRESC_PRESC_SHIFT   8
 
#define _CMU_HFCOREPRESC_RESETVALUE   0x00000000UL
 
#define _CMU_HFEXPPRESC_MASK   0x00001F00UL
 
#define _CMU_HFEXPPRESC_PRESC_DEFAULT   0x00000000UL
 
#define _CMU_HFEXPPRESC_PRESC_MASK   0x1F00UL
 
#define _CMU_HFEXPPRESC_PRESC_NODIVISION   0x00000000UL
 
#define _CMU_HFEXPPRESC_PRESC_SHIFT   8
 
#define _CMU_HFEXPPRESC_RESETVALUE   0x00000000UL
 
#define _CMU_HFPERCLKEN0_ACMP0_DEFAULT   0x00000000UL
 
#define _CMU_HFPERCLKEN0_ACMP0_MASK   0x10UL
 
#define _CMU_HFPERCLKEN0_ACMP0_SHIFT   4
 
#define _CMU_HFPERCLKEN0_ACMP1_DEFAULT   0x00000000UL
 
#define _CMU_HFPERCLKEN0_ACMP1_MASK   0x20UL
 
#define _CMU_HFPERCLKEN0_ACMP1_SHIFT   5
 
#define _CMU_HFPERCLKEN0_ADC0_DEFAULT   0x00000000UL
 
#define _CMU_HFPERCLKEN0_ADC0_MASK   0x100UL
 
#define _CMU_HFPERCLKEN0_ADC0_SHIFT   8
 
#define _CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT   0x00000000UL
 
#define _CMU_HFPERCLKEN0_CRYOTIMER_MASK   0x40UL
 
#define _CMU_HFPERCLKEN0_CRYOTIMER_SHIFT   6
 
#define _CMU_HFPERCLKEN0_I2C0_DEFAULT   0x00000000UL
 
#define _CMU_HFPERCLKEN0_I2C0_MASK   0x80UL
 
#define _CMU_HFPERCLKEN0_I2C0_SHIFT   7
 
#define _CMU_HFPERCLKEN0_IDAC0_DEFAULT   0x00000000UL
 
#define _CMU_HFPERCLKEN0_IDAC0_MASK   0x200UL
 
#define _CMU_HFPERCLKEN0_IDAC0_SHIFT   9
 
#define _CMU_HFPERCLKEN0_MASK   0x000003FFUL
 
#define _CMU_HFPERCLKEN0_RESETVALUE   0x00000000UL
 
#define _CMU_HFPERCLKEN0_TIMER0_DEFAULT   0x00000000UL
 
#define _CMU_HFPERCLKEN0_TIMER0_MASK   0x1UL
 
#define _CMU_HFPERCLKEN0_TIMER0_SHIFT   0
 
#define _CMU_HFPERCLKEN0_TIMER1_DEFAULT   0x00000000UL
 
#define _CMU_HFPERCLKEN0_TIMER1_MASK   0x2UL
 
#define _CMU_HFPERCLKEN0_TIMER1_SHIFT   1
 
#define _CMU_HFPERCLKEN0_USART0_DEFAULT   0x00000000UL
 
#define _CMU_HFPERCLKEN0_USART0_MASK   0x4UL
 
#define _CMU_HFPERCLKEN0_USART0_SHIFT   2
 
#define _CMU_HFPERCLKEN0_USART1_DEFAULT   0x00000000UL
 
#define _CMU_HFPERCLKEN0_USART1_MASK   0x8UL
 
#define _CMU_HFPERCLKEN0_USART1_SHIFT   3
 
#define _CMU_HFPERPRESC_MASK   0x0001FF00UL
 
#define _CMU_HFPERPRESC_PRESC_DEFAULT   0x00000000UL
 
#define _CMU_HFPERPRESC_PRESC_MASK   0x1FF00UL
 
#define _CMU_HFPERPRESC_PRESC_NODIVISION   0x00000000UL
 
#define _CMU_HFPERPRESC_PRESC_SHIFT   8
 
#define _CMU_HFPERPRESC_RESETVALUE   0x00000000UL
 
#define _CMU_HFPRESC_HFCLKLEPRESC_DEFAULT   0x00000000UL
 
#define _CMU_HFPRESC_HFCLKLEPRESC_DIV2   0x00000000UL
 
#define _CMU_HFPRESC_HFCLKLEPRESC_DIV4   0x00000001UL
 
#define _CMU_HFPRESC_HFCLKLEPRESC_MASK   0x1000000UL
 
#define _CMU_HFPRESC_HFCLKLEPRESC_SHIFT   24
 
#define _CMU_HFPRESC_MASK   0x01001F00UL
 
#define _CMU_HFPRESC_PRESC_DEFAULT   0x00000000UL
 
#define _CMU_HFPRESC_PRESC_MASK   0x1F00UL
 
#define _CMU_HFPRESC_PRESC_NODIVISION   0x00000000UL
 
#define _CMU_HFPRESC_PRESC_SHIFT   8
 
#define _CMU_HFPRESC_RESETVALUE   0x00000000UL
 
#define _CMU_HFRCOCTRL_CLKDIV_DEFAULT   0x00000000UL
 
#define _CMU_HFRCOCTRL_CLKDIV_DIV1   0x00000000UL
 
#define _CMU_HFRCOCTRL_CLKDIV_DIV2   0x00000001UL
 
#define _CMU_HFRCOCTRL_CLKDIV_DIV4   0x00000002UL
 
#define _CMU_HFRCOCTRL_CLKDIV_MASK   0x6000000UL
 
#define _CMU_HFRCOCTRL_CLKDIV_SHIFT   25
 
#define _CMU_HFRCOCTRL_CMPBIAS_DEFAULT   0x00000002UL
 
#define _CMU_HFRCOCTRL_CMPBIAS_MASK   0xE00000UL
 
#define _CMU_HFRCOCTRL_CMPBIAS_SHIFT   21
 
#define _CMU_HFRCOCTRL_FINETUNING_DEFAULT   0x0000001FUL
 
#define _CMU_HFRCOCTRL_FINETUNING_MASK   0x3F00UL
 
#define _CMU_HFRCOCTRL_FINETUNING_SHIFT   8
 
#define _CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT   0x00000000UL
 
#define _CMU_HFRCOCTRL_FINETUNINGEN_MASK   0x8000000UL
 
#define _CMU_HFRCOCTRL_FINETUNINGEN_SHIFT   27
 
#define _CMU_HFRCOCTRL_FREQRANGE_DEFAULT   0x00000008UL
 
#define _CMU_HFRCOCTRL_FREQRANGE_MASK   0x1F0000UL
 
#define _CMU_HFRCOCTRL_FREQRANGE_SHIFT   16
 
#define _CMU_HFRCOCTRL_LDOHP_DEFAULT   0x00000001UL
 
#define _CMU_HFRCOCTRL_LDOHP_MASK   0x1000000UL
 
#define _CMU_HFRCOCTRL_LDOHP_SHIFT   24
 
#define _CMU_HFRCOCTRL_MASK   0xFFFF3F7FUL
 
#define _CMU_HFRCOCTRL_RESETVALUE   0xB1481F3CUL
 
#define _CMU_HFRCOCTRL_TUNING_DEFAULT   0x0000003CUL
 
#define _CMU_HFRCOCTRL_TUNING_MASK   0x7FUL
 
#define _CMU_HFRCOCTRL_TUNING_SHIFT   0
 
#define _CMU_HFRCOCTRL_VREFTC_DEFAULT   0x0000000BUL
 
#define _CMU_HFRCOCTRL_VREFTC_MASK   0xF0000000UL
 
#define _CMU_HFRCOCTRL_VREFTC_SHIFT   28
 
#define _CMU_HFXOCTRL1_MASK   0x00000277UL
 
#define _CMU_HFXOCTRL1_PEAKDETTHR_DEFAULT   0x00000000UL
 
#define _CMU_HFXOCTRL1_PEAKDETTHR_MASK   0x7UL
 
#define _CMU_HFXOCTRL1_PEAKDETTHR_SHIFT   0
 
#define _CMU_HFXOCTRL1_REGLVL_DEFAULT   0x00000004UL
 
#define _CMU_HFXOCTRL1_REGLVL_MASK   0x70UL
 
#define _CMU_HFXOCTRL1_REGLVL_SHIFT   4
 
#define _CMU_HFXOCTRL1_RESETVALUE   0x00000240UL
 
#define _CMU_HFXOCTRL1_XTIBIASEN_DEFAULT   0x00000001UL
 
#define _CMU_HFXOCTRL1_XTIBIASEN_MASK   0x200UL
 
#define _CMU_HFXOCTRL1_XTIBIASEN_SHIFT   9
 
#define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT   0x00000000UL
 
#define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_MASK   0x10000000UL
 
#define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_SHIFT   28
 
#define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT   0x00000000UL
 
#define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_MASK   0x20000000UL
 
#define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_SHIFT   29
 
#define _CMU_HFXOCTRL_LFTIMEOUT_0CYCLES   0x00000000UL
 
#define _CMU_HFXOCTRL_LFTIMEOUT_16CYCLES   0x00000003UL
 
#define _CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES   0x00000006UL
 
#define _CMU_HFXOCTRL_LFTIMEOUT_2CYCLES   0x00000001UL
 
#define _CMU_HFXOCTRL_LFTIMEOUT_32CYCLES   0x00000004UL
 
#define _CMU_HFXOCTRL_LFTIMEOUT_4CYCLES   0x00000002UL
 
#define _CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES   0x00000007UL
 
#define _CMU_HFXOCTRL_LFTIMEOUT_64CYCLES   0x00000005UL
 
#define _CMU_HFXOCTRL_LFTIMEOUT_DEFAULT   0x00000000UL
 
#define _CMU_HFXOCTRL_LFTIMEOUT_MASK   0x7000000UL
 
#define _CMU_HFXOCTRL_LFTIMEOUT_SHIFT   24
 
#define _CMU_HFXOCTRL_LOWPOWER_DEFAULT   0x00000000UL
 
#define _CMU_HFXOCTRL_LOWPOWER_MASK   0x100UL
 
#define _CMU_HFXOCTRL_LOWPOWER_SHIFT   8
 
#define _CMU_HFXOCTRL_MASK   0x37000731UL
 
#define _CMU_HFXOCTRL_MODE_DEFAULT   0x00000000UL
 
#define _CMU_HFXOCTRL_MODE_EXTCLK   0x00000001UL
 
#define _CMU_HFXOCTRL_MODE_MASK   0x1UL
 
#define _CMU_HFXOCTRL_MODE_SHIFT   0
 
#define _CMU_HFXOCTRL_MODE_XTAL   0x00000000UL
 
#define _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_AUTOCMD   0x00000000UL
 
#define _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_CMD   0x00000001UL
 
#define _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_DEFAULT   0x00000000UL
 
#define _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MANUAL   0x00000002UL
 
#define _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK   0x30UL
 
#define _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_SHIFT   4
 
#define _CMU_HFXOCTRL_RESETVALUE   0x00000000UL
 
#define _CMU_HFXOCTRL_XTI2GND_DEFAULT   0x00000000UL
 
#define _CMU_HFXOCTRL_XTI2GND_MASK   0x200UL
 
#define _CMU_HFXOCTRL_XTI2GND_SHIFT   9
 
#define _CMU_HFXOCTRL_XTO2GND_DEFAULT   0x00000000UL
 
#define _CMU_HFXOCTRL_XTO2GND_MASK   0x400UL
 
#define _CMU_HFXOCTRL_XTO2GND_SHIFT   10
 
#define _CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT   0x000000A0UL
 
#define _CMU_HFXOSTARTUPCTRL_CTUNE_MASK   0xFF800UL
 
#define _CMU_HFXOSTARTUPCTRL_CTUNE_SHIFT   11
 
#define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT   0x00000060UL
 
#define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_MASK   0x7FUL
 
#define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_SHIFT   0
 
#define _CMU_HFXOSTARTUPCTRL_MASK   0xFFEFF87FUL
 
#define _CMU_HFXOSTARTUPCTRL_RESERVED0_DEFAULT   0x00000009UL
 
#define _CMU_HFXOSTARTUPCTRL_RESERVED0_MASK   0xFE00000UL
 
#define _CMU_HFXOSTARTUPCTRL_RESERVED0_SHIFT   21
 
#define _CMU_HFXOSTARTUPCTRL_RESERVED1_DEFAULT   0x0000000AUL
 
#define _CMU_HFXOSTARTUPCTRL_RESERVED1_MASK   0xF0000000UL
 
#define _CMU_HFXOSTARTUPCTRL_RESERVED1_SHIFT   28
 
#define _CMU_HFXOSTARTUPCTRL_RESETVALUE   0xA1250060UL
 
#define _CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT   0x00000155UL
 
#define _CMU_HFXOSTEADYSTATECTRL_CTUNE_MASK   0xFF800UL
 
#define _CMU_HFXOSTEADYSTATECTRL_CTUNE_SHIFT   11
 
#define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT   0x00000009UL
 
#define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_MASK   0x7FUL
 
#define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_SHIFT   0
 
#define _CMU_HFXOSTEADYSTATECTRL_MASK   0xF70FFFFFUL
 
#define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT   0x00000000UL
 
#define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_MASK   0x4000000UL
 
#define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_SHIFT   26
 
#define _CMU_HFXOSTEADYSTATECTRL_REGISH_DEFAULT   0x0000000AUL
 
#define _CMU_HFXOSTEADYSTATECTRL_REGISH_MASK   0x780UL
 
#define _CMU_HFXOSTEADYSTATECTRL_REGISH_SHIFT   7
 
#define _CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_DEFAULT   0x0000000AUL
 
#define _CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_MASK   0xF0000000UL
 
#define _CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_SHIFT   28
 
#define _CMU_HFXOSTEADYSTATECTRL_REGSELILOW_DEFAULT   0x00000003UL
 
#define _CMU_HFXOSTEADYSTATECTRL_REGSELILOW_MASK   0x3000000UL
 
#define _CMU_HFXOSTEADYSTATECTRL_REGSELILOW_SHIFT   24
 
#define _CMU_HFXOSTEADYSTATECTRL_RESETVALUE   0xA30AAD09UL
 
#define _CMU_HFXOTIMEOUTCTRL_MASK   0x000FFFFFUL
 
#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES   0x00000002UL
 
#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES   0x00000009UL
 
#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES   0x00000005UL
 
#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES   0x00000004UL
 
#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES   0x00000000UL
 
#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES   0x00000006UL
 
#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES   0x00000003UL
 
#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES   0x0000000AUL
 
#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES   0x00000001UL
 
#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES   0x00000007UL
 
#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES   0x00000008UL
 
#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT   0x00000006UL
 
#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_MASK   0xF000UL
 
#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_SHIFT   12
 
#define _CMU_HFXOTIMEOUTCTRL_RESERVED2_DEFAULT   0x00000006UL
 
#define _CMU_HFXOTIMEOUTCTRL_RESERVED2_MASK   0xF00UL
 
#define _CMU_HFXOTIMEOUTCTRL_RESERVED2_SHIFT   8
 
#define _CMU_HFXOTIMEOUTCTRL_RESETVALUE   0x00026667UL
 
#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_16CYCLES   0x00000002UL
 
#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_16KCYCLES   0x00000009UL
 
#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_1KCYCLES   0x00000005UL
 
#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_256CYCLES   0x00000004UL
 
#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_2CYCLES   0x00000000UL
 
#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_2KCYCLES   0x00000006UL
 
#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_32CYCLES   0x00000003UL
 
#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_32KCYCLES   0x0000000AUL
 
#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_4CYCLES   0x00000001UL
 
#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_4KCYCLES   0x00000007UL
 
#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_8KCYCLES   0x00000008UL
 
#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_DEFAULT   0x00000002UL
 
#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_MASK   0xF0000UL
 
#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_SHIFT   16
 
#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES   0x00000002UL
 
#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES   0x00000009UL
 
#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES   0x00000005UL
 
#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES   0x00000004UL
 
#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES   0x00000000UL
 
#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES   0x00000006UL
 
#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES   0x00000003UL
 
#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES   0x0000000AUL
 
#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES   0x00000001UL
 
#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES   0x00000007UL
 
#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES   0x00000008UL
 
#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT   0x00000007UL
 
#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_MASK   0xFUL
 
#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_SHIFT   0
 
#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES   0x00000002UL
 
#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES   0x00000009UL
 
#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES   0x00000005UL
 
#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES   0x00000004UL
 
#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES   0x00000000UL
 
#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES   0x00000006UL
 
#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES   0x00000003UL
 
#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES   0x0000000AUL
 
#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES   0x00000001UL
 
#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES   0x00000007UL
 
#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES   0x00000008UL
 
#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT   0x00000006UL
 
#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_MASK   0xF0UL
 
#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_SHIFT   4
 
#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT   0x00000000UL
 
#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_MASK   0x7FUL
 
#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_SHIFT   0
 
#define _CMU_HFXOTRIMSTATUS_MASK   0x000007FFUL
 
#define _CMU_HFXOTRIMSTATUS_REGISH_DEFAULT   0x0000000AUL
 
#define _CMU_HFXOTRIMSTATUS_REGISH_MASK   0x780UL
 
#define _CMU_HFXOTRIMSTATUS_REGISH_SHIFT   7
 
#define _CMU_HFXOTRIMSTATUS_RESETVALUE   0x00000500UL
 
#define _CMU_IEN_AUXHFRCORDY_DEFAULT   0x00000000UL
 
#define _CMU_IEN_AUXHFRCORDY_MASK   0x10UL
 
#define _CMU_IEN_AUXHFRCORDY_SHIFT   4
 
#define _CMU_IEN_CALOF_DEFAULT   0x00000000UL
 
#define _CMU_IEN_CALOF_MASK   0x40UL
 
#define _CMU_IEN_CALOF_SHIFT   6
 
#define _CMU_IEN_CALRDY_DEFAULT   0x00000000UL
 
#define _CMU_IEN_CALRDY_MASK   0x20UL
 
#define _CMU_IEN_CALRDY_SHIFT   5
 
#define _CMU_IEN_CMUERR_DEFAULT   0x00000000UL
 
#define _CMU_IEN_CMUERR_MASK   0x80000000UL
 
#define _CMU_IEN_CMUERR_SHIFT   31
 
#define _CMU_IEN_HFRCODIS_DEFAULT   0x00000000UL
 
#define _CMU_IEN_HFRCODIS_MASK   0x2000UL
 
#define _CMU_IEN_HFRCODIS_SHIFT   13
 
#define _CMU_IEN_HFRCORDY_DEFAULT   0x00000000UL
 
#define _CMU_IEN_HFRCORDY_MASK   0x1UL
 
#define _CMU_IEN_HFRCORDY_SHIFT   0
 
#define _CMU_IEN_HFXOAUTOSW_DEFAULT   0x00000000UL
 
#define _CMU_IEN_HFXOAUTOSW_MASK   0x200UL
 
#define _CMU_IEN_HFXOAUTOSW_SHIFT   9
 
#define _CMU_IEN_HFXODISERR_DEFAULT   0x00000000UL
 
#define _CMU_IEN_HFXODISERR_MASK   0x100UL
 
#define _CMU_IEN_HFXODISERR_SHIFT   8
 
#define _CMU_IEN_HFXOPEAKDETERR_DEFAULT   0x00000000UL
 
#define _CMU_IEN_HFXOPEAKDETERR_MASK   0x400UL
 
#define _CMU_IEN_HFXOPEAKDETERR_SHIFT   10
 
#define _CMU_IEN_HFXOPEAKDETRDY_DEFAULT   0x00000000UL
 
#define _CMU_IEN_HFXOPEAKDETRDY_MASK   0x800UL
 
#define _CMU_IEN_HFXOPEAKDETRDY_SHIFT   11
 
#define _CMU_IEN_HFXORDY_DEFAULT   0x00000000UL
 
#define _CMU_IEN_HFXORDY_MASK   0x2UL
 
#define _CMU_IEN_HFXORDY_SHIFT   1
 
#define _CMU_IEN_HFXOSHUNTOPTRDY_DEFAULT   0x00000000UL
 
#define _CMU_IEN_HFXOSHUNTOPTRDY_MASK   0x1000UL
 
#define _CMU_IEN_HFXOSHUNTOPTRDY_SHIFT   12
 
#define _CMU_IEN_LFRCORDY_DEFAULT   0x00000000UL
 
#define _CMU_IEN_LFRCORDY_MASK   0x4UL
 
#define _CMU_IEN_LFRCORDY_SHIFT   2
 
#define _CMU_IEN_LFTIMEOUTERR_DEFAULT   0x00000000UL
 
#define _CMU_IEN_LFTIMEOUTERR_MASK   0x4000UL
 
#define _CMU_IEN_LFTIMEOUTERR_SHIFT   14
 
#define _CMU_IEN_LFXORDY_DEFAULT   0x00000000UL
 
#define _CMU_IEN_LFXORDY_MASK   0x8UL
 
#define _CMU_IEN_LFXORDY_SHIFT   3
 
#define _CMU_IEN_MASK   0x80007F7FUL
 
#define _CMU_IEN_RESETVALUE   0x00000000UL
 
#define _CMU_IF_AUXHFRCORDY_DEFAULT   0x00000000UL
 
#define _CMU_IF_AUXHFRCORDY_MASK   0x10UL
 
#define _CMU_IF_AUXHFRCORDY_SHIFT   4
 
#define _CMU_IF_CALOF_DEFAULT   0x00000000UL
 
#define _CMU_IF_CALOF_MASK   0x40UL
 
#define _CMU_IF_CALOF_SHIFT   6
 
#define _CMU_IF_CALRDY_DEFAULT   0x00000000UL
 
#define _CMU_IF_CALRDY_MASK   0x20UL
 
#define _CMU_IF_CALRDY_SHIFT   5
 
#define _CMU_IF_CMUERR_DEFAULT   0x00000000UL
 
#define _CMU_IF_CMUERR_MASK   0x80000000UL
 
#define _CMU_IF_CMUERR_SHIFT   31
 
#define _CMU_IF_HFRCODIS_DEFAULT   0x00000000UL
 
#define _CMU_IF_HFRCODIS_MASK   0x2000UL
 
#define _CMU_IF_HFRCODIS_SHIFT   13
 
#define _CMU_IF_HFRCORDY_DEFAULT   0x00000001UL
 
#define _CMU_IF_HFRCORDY_MASK   0x1UL
 
#define _CMU_IF_HFRCORDY_SHIFT   0
 
#define _CMU_IF_HFXOAUTOSW_DEFAULT   0x00000000UL
 
#define _CMU_IF_HFXOAUTOSW_MASK   0x200UL
 
#define _CMU_IF_HFXOAUTOSW_SHIFT   9
 
#define _CMU_IF_HFXODISERR_DEFAULT   0x00000000UL
 
#define _CMU_IF_HFXODISERR_MASK   0x100UL
 
#define _CMU_IF_HFXODISERR_SHIFT   8
 
#define _CMU_IF_HFXOPEAKDETERR_DEFAULT   0x00000000UL
 
#define _CMU_IF_HFXOPEAKDETERR_MASK   0x400UL
 
#define _CMU_IF_HFXOPEAKDETERR_SHIFT   10
 
#define _CMU_IF_HFXOPEAKDETRDY_DEFAULT   0x00000000UL
 
#define _CMU_IF_HFXOPEAKDETRDY_MASK   0x800UL
 
#define _CMU_IF_HFXOPEAKDETRDY_SHIFT   11
 
#define _CMU_IF_HFXORDY_DEFAULT   0x00000000UL
 
#define _CMU_IF_HFXORDY_MASK   0x2UL
 
#define _CMU_IF_HFXORDY_SHIFT   1
 
#define _CMU_IF_HFXOSHUNTOPTRDY_DEFAULT   0x00000000UL
 
#define _CMU_IF_HFXOSHUNTOPTRDY_MASK   0x1000UL
 
#define _CMU_IF_HFXOSHUNTOPTRDY_SHIFT   12
 
#define _CMU_IF_LFRCORDY_DEFAULT   0x00000000UL
 
#define _CMU_IF_LFRCORDY_MASK   0x4UL
 
#define _CMU_IF_LFRCORDY_SHIFT   2
 
#define _CMU_IF_LFTIMEOUTERR_DEFAULT   0x00000000UL
 
#define _CMU_IF_LFTIMEOUTERR_MASK   0x4000UL
 
#define _CMU_IF_LFTIMEOUTERR_SHIFT   14
 
#define _CMU_IF_LFXORDY_DEFAULT   0x00000000UL
 
#define _CMU_IF_LFXORDY_MASK   0x8UL
 
#define _CMU_IF_LFXORDY_SHIFT   3
 
#define _CMU_IF_MASK   0x80007F7FUL
 
#define _CMU_IF_RESETVALUE   0x00000001UL
 
#define _CMU_IFC_AUXHFRCORDY_DEFAULT   0x00000000UL
 
#define _CMU_IFC_AUXHFRCORDY_MASK   0x10UL
 
#define _CMU_IFC_AUXHFRCORDY_SHIFT   4
 
#define _CMU_IFC_CALOF_DEFAULT   0x00000000UL
 
#define _CMU_IFC_CALOF_MASK   0x40UL
 
#define _CMU_IFC_CALOF_SHIFT   6
 
#define _CMU_IFC_CALRDY_DEFAULT   0x00000000UL
 
#define _CMU_IFC_CALRDY_MASK   0x20UL
 
#define _CMU_IFC_CALRDY_SHIFT   5
 
#define _CMU_IFC_CMUERR_DEFAULT   0x00000000UL
 
#define _CMU_IFC_CMUERR_MASK   0x80000000UL
 
#define _CMU_IFC_CMUERR_SHIFT   31
 
#define _CMU_IFC_HFRCODIS_DEFAULT   0x00000000UL
 
#define _CMU_IFC_HFRCODIS_MASK   0x2000UL
 
#define _CMU_IFC_HFRCODIS_SHIFT   13
 
#define _CMU_IFC_HFRCORDY_DEFAULT   0x00000000UL
 
#define _CMU_IFC_HFRCORDY_MASK   0x1UL
 
#define _CMU_IFC_HFRCORDY_SHIFT   0
 
#define _CMU_IFC_HFXOAUTOSW_DEFAULT   0x00000000UL
 
#define _CMU_IFC_HFXOAUTOSW_MASK   0x200UL
 
#define _CMU_IFC_HFXOAUTOSW_SHIFT   9
 
#define _CMU_IFC_HFXODISERR_DEFAULT   0x00000000UL
 
#define _CMU_IFC_HFXODISERR_MASK   0x100UL
 
#define _CMU_IFC_HFXODISERR_SHIFT   8
 
#define _CMU_IFC_HFXOPEAKDETERR_DEFAULT   0x00000000UL
 
#define _CMU_IFC_HFXOPEAKDETERR_MASK   0x400UL
 
#define _CMU_IFC_HFXOPEAKDETERR_SHIFT   10
 
#define _CMU_IFC_HFXOPEAKDETRDY_DEFAULT   0x00000000UL
 
#define _CMU_IFC_HFXOPEAKDETRDY_MASK   0x800UL
 
#define _CMU_IFC_HFXOPEAKDETRDY_SHIFT   11
 
#define _CMU_IFC_HFXORDY_DEFAULT   0x00000000UL
 
#define _CMU_IFC_HFXORDY_MASK   0x2UL
 
#define _CMU_IFC_HFXORDY_SHIFT   1
 
#define _CMU_IFC_HFXOSHUNTOPTRDY_DEFAULT   0x00000000UL
 
#define _CMU_IFC_HFXOSHUNTOPTRDY_MASK   0x1000UL
 
#define _CMU_IFC_HFXOSHUNTOPTRDY_SHIFT   12
 
#define _CMU_IFC_LFRCORDY_DEFAULT   0x00000000UL
 
#define _CMU_IFC_LFRCORDY_MASK   0x4UL
 
#define _CMU_IFC_LFRCORDY_SHIFT   2
 
#define _CMU_IFC_LFTIMEOUTERR_DEFAULT   0x00000000UL
 
#define _CMU_IFC_LFTIMEOUTERR_MASK   0x4000UL
 
#define _CMU_IFC_LFTIMEOUTERR_SHIFT   14
 
#define _CMU_IFC_LFXORDY_DEFAULT   0x00000000UL
 
#define _CMU_IFC_LFXORDY_MASK   0x8UL
 
#define _CMU_IFC_LFXORDY_SHIFT   3
 
#define _CMU_IFC_MASK   0x80007F7FUL
 
#define _CMU_IFC_RESETVALUE   0x00000000UL
 
#define _CMU_IFS_AUXHFRCORDY_DEFAULT   0x00000000UL
 
#define _CMU_IFS_AUXHFRCORDY_MASK   0x10UL
 
#define _CMU_IFS_AUXHFRCORDY_SHIFT   4
 
#define _CMU_IFS_CALOF_DEFAULT   0x00000000UL
 
#define _CMU_IFS_CALOF_MASK   0x40UL
 
#define _CMU_IFS_CALOF_SHIFT   6
 
#define _CMU_IFS_CALRDY_DEFAULT   0x00000000UL
 
#define _CMU_IFS_CALRDY_MASK   0x20UL
 
#define _CMU_IFS_CALRDY_SHIFT   5
 
#define _CMU_IFS_CMUERR_DEFAULT   0x00000000UL
 
#define _CMU_IFS_CMUERR_MASK   0x80000000UL
 
#define _CMU_IFS_CMUERR_SHIFT   31
 
#define _CMU_IFS_HFRCODIS_DEFAULT   0x00000000UL
 
#define _CMU_IFS_HFRCODIS_MASK   0x2000UL
 
#define _CMU_IFS_HFRCODIS_SHIFT   13
 
#define _CMU_IFS_HFRCORDY_DEFAULT   0x00000000UL
 
#define _CMU_IFS_HFRCORDY_MASK   0x1UL
 
#define _CMU_IFS_HFRCORDY_SHIFT   0
 
#define _CMU_IFS_HFXOAUTOSW_DEFAULT   0x00000000UL
 
#define _CMU_IFS_HFXOAUTOSW_MASK   0x200UL
 
#define _CMU_IFS_HFXOAUTOSW_SHIFT   9
 
#define _CMU_IFS_HFXODISERR_DEFAULT   0x00000000UL
 
#define _CMU_IFS_HFXODISERR_MASK   0x100UL
 
#define _CMU_IFS_HFXODISERR_SHIFT   8
 
#define _CMU_IFS_HFXOPEAKDETERR_DEFAULT   0x00000000UL
 
#define _CMU_IFS_HFXOPEAKDETERR_MASK   0x400UL
 
#define _CMU_IFS_HFXOPEAKDETERR_SHIFT   10
 
#define _CMU_IFS_HFXOPEAKDETRDY_DEFAULT   0x00000000UL
 
#define _CMU_IFS_HFXOPEAKDETRDY_MASK   0x800UL
 
#define _CMU_IFS_HFXOPEAKDETRDY_SHIFT   11
 
#define _CMU_IFS_HFXORDY_DEFAULT   0x00000000UL
 
#define _CMU_IFS_HFXORDY_MASK   0x2UL
 
#define _CMU_IFS_HFXORDY_SHIFT   1
 
#define _CMU_IFS_HFXOSHUNTOPTRDY_DEFAULT   0x00000000UL
 
#define _CMU_IFS_HFXOSHUNTOPTRDY_MASK   0x1000UL
 
#define _CMU_IFS_HFXOSHUNTOPTRDY_SHIFT   12
 
#define _CMU_IFS_LFRCORDY_DEFAULT   0x00000000UL
 
#define _CMU_IFS_LFRCORDY_MASK   0x4UL
 
#define _CMU_IFS_LFRCORDY_SHIFT   2
 
#define _CMU_IFS_LFTIMEOUTERR_DEFAULT   0x00000000UL
 
#define _CMU_IFS_LFTIMEOUTERR_MASK   0x4000UL
 
#define _CMU_IFS_LFTIMEOUTERR_SHIFT   14
 
#define _CMU_IFS_LFXORDY_DEFAULT   0x00000000UL
 
#define _CMU_IFS_LFXORDY_MASK   0x8UL
 
#define _CMU_IFS_LFXORDY_SHIFT   3
 
#define _CMU_IFS_MASK   0x80007F7FUL
 
#define _CMU_IFS_RESETVALUE   0x00000000UL
 
#define _CMU_LFACLKEN0_LETIMER0_DEFAULT   0x00000000UL
 
#define _CMU_LFACLKEN0_LETIMER0_MASK   0x1UL
 
#define _CMU_LFACLKEN0_LETIMER0_SHIFT   0
 
#define _CMU_LFACLKEN0_MASK   0x00000001UL
 
#define _CMU_LFACLKEN0_RESETVALUE   0x00000000UL
 
#define _CMU_LFACLKSEL_LFA_DEFAULT   0x00000000UL
 
#define _CMU_LFACLKSEL_LFA_DISABLED   0x00000000UL
 
#define _CMU_LFACLKSEL_LFA_LFRCO   0x00000001UL
 
#define _CMU_LFACLKSEL_LFA_LFXO   0x00000002UL
 
#define _CMU_LFACLKSEL_LFA_MASK   0x7UL
 
#define _CMU_LFACLKSEL_LFA_SHIFT   0
 
#define _CMU_LFACLKSEL_LFA_ULFRCO   0x00000004UL
 
#define _CMU_LFACLKSEL_MASK   0x00000007UL
 
#define _CMU_LFACLKSEL_RESETVALUE   0x00000000UL
 
#define _CMU_LFAPRESC0_LETIMER0_DIV1   0x00000000UL
 
#define _CMU_LFAPRESC0_LETIMER0_DIV1024   0x0000000AUL
 
#define _CMU_LFAPRESC0_LETIMER0_DIV128   0x00000007UL
 
#define _CMU_LFAPRESC0_LETIMER0_DIV16   0x00000004UL
 
#define _CMU_LFAPRESC0_LETIMER0_DIV16384   0x0000000EUL
 
#define _CMU_LFAPRESC0_LETIMER0_DIV2   0x00000001UL
 
#define _CMU_LFAPRESC0_LETIMER0_DIV2048   0x0000000BUL
 
#define _CMU_LFAPRESC0_LETIMER0_DIV256   0x00000008UL
 
#define _CMU_LFAPRESC0_LETIMER0_DIV32   0x00000005UL
 
#define _CMU_LFAPRESC0_LETIMER0_DIV32768   0x0000000FUL
 
#define _CMU_LFAPRESC0_LETIMER0_DIV4   0x00000002UL
 
#define _CMU_LFAPRESC0_LETIMER0_DIV4096   0x0000000CUL
 
#define _CMU_LFAPRESC0_LETIMER0_DIV512   0x00000009UL
 
#define _CMU_LFAPRESC0_LETIMER0_DIV64   0x00000006UL
 
#define _CMU_LFAPRESC0_LETIMER0_DIV8   0x00000003UL
 
#define _CMU_LFAPRESC0_LETIMER0_DIV8192   0x0000000DUL
 
#define _CMU_LFAPRESC0_LETIMER0_MASK   0xFUL
 
#define _CMU_LFAPRESC0_LETIMER0_SHIFT   0
 
#define _CMU_LFAPRESC0_MASK   0x0000000FUL
 
#define _CMU_LFAPRESC0_RESETVALUE   0x00000000UL
 
#define _CMU_LFBCLKEN0_LEUART0_DEFAULT   0x00000000UL
 
#define _CMU_LFBCLKEN0_LEUART0_MASK   0x1UL
 
#define _CMU_LFBCLKEN0_LEUART0_SHIFT   0
 
#define _CMU_LFBCLKEN0_MASK   0x00000001UL
 
#define _CMU_LFBCLKEN0_RESETVALUE   0x00000000UL
 
#define _CMU_LFBCLKSEL_LFB_DEFAULT   0x00000000UL
 
#define _CMU_LFBCLKSEL_LFB_DISABLED   0x00000000UL
 
#define _CMU_LFBCLKSEL_LFB_HFCLKLE   0x00000003UL
 
#define _CMU_LFBCLKSEL_LFB_LFRCO   0x00000001UL
 
#define _CMU_LFBCLKSEL_LFB_LFXO   0x00000002UL
 
#define _CMU_LFBCLKSEL_LFB_MASK   0x7UL
 
#define _CMU_LFBCLKSEL_LFB_SHIFT   0
 
#define _CMU_LFBCLKSEL_LFB_ULFRCO   0x00000004UL
 
#define _CMU_LFBCLKSEL_MASK   0x00000007UL
 
#define _CMU_LFBCLKSEL_RESETVALUE   0x00000000UL
 
#define _CMU_LFBPRESC0_LEUART0_DIV1   0x00000000UL
 
#define _CMU_LFBPRESC0_LEUART0_DIV2   0x00000001UL
 
#define _CMU_LFBPRESC0_LEUART0_DIV4   0x00000002UL
 
#define _CMU_LFBPRESC0_LEUART0_DIV8   0x00000003UL
 
#define _CMU_LFBPRESC0_LEUART0_MASK   0x3UL
 
#define _CMU_LFBPRESC0_LEUART0_SHIFT   0
 
#define _CMU_LFBPRESC0_MASK   0x00000003UL
 
#define _CMU_LFBPRESC0_RESETVALUE   0x00000000UL
 
#define _CMU_LFECLKEN0_MASK   0x00000001UL
 
#define _CMU_LFECLKEN0_RESETVALUE   0x00000000UL
 
#define _CMU_LFECLKEN0_RTCC_DEFAULT   0x00000000UL
 
#define _CMU_LFECLKEN0_RTCC_MASK   0x1UL
 
#define _CMU_LFECLKEN0_RTCC_SHIFT   0
 
#define _CMU_LFECLKSEL_LFE_DEFAULT   0x00000000UL
 
#define _CMU_LFECLKSEL_LFE_DISABLED   0x00000000UL
 
#define _CMU_LFECLKSEL_LFE_LFRCO   0x00000001UL
 
#define _CMU_LFECLKSEL_LFE_LFXO   0x00000002UL
 
#define _CMU_LFECLKSEL_LFE_MASK   0x7UL
 
#define _CMU_LFECLKSEL_LFE_SHIFT   0
 
#define _CMU_LFECLKSEL_LFE_ULFRCO   0x00000004UL
 
#define _CMU_LFECLKSEL_MASK   0x00000007UL
 
#define _CMU_LFECLKSEL_RESETVALUE   0x00000000UL
 
#define _CMU_LFEPRESC0_MASK   0x0000000FUL
 
#define _CMU_LFEPRESC0_RESETVALUE   0x00000000UL
 
#define _CMU_LFEPRESC0_RTCC_DIV1   0x00000000UL
 
#define _CMU_LFEPRESC0_RTCC_MASK   0xFUL
 
#define _CMU_LFEPRESC0_RTCC_SHIFT   0
 
#define _CMU_LFRCOCTRL_ENCHOP_DEFAULT   0x00000001UL
 
#define _CMU_LFRCOCTRL_ENCHOP_MASK   0x20000UL
 
#define _CMU_LFRCOCTRL_ENCHOP_SHIFT   17
 
#define _CMU_LFRCOCTRL_ENDEM_DEFAULT   0x00000001UL
 
#define _CMU_LFRCOCTRL_ENDEM_MASK   0x40000UL
 
#define _CMU_LFRCOCTRL_ENDEM_SHIFT   18
 
#define _CMU_LFRCOCTRL_ENVREF_DEFAULT   0x00000000UL
 
#define _CMU_LFRCOCTRL_ENVREF_MASK   0x10000UL
 
#define _CMU_LFRCOCTRL_ENVREF_SHIFT   16
 
#define _CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT   0x00000008UL
 
#define _CMU_LFRCOCTRL_GMCCURTUNE_MASK   0xF0000000UL
 
#define _CMU_LFRCOCTRL_GMCCURTUNE_SHIFT   28
 
#define _CMU_LFRCOCTRL_MASK   0xF30701FFUL
 
#define _CMU_LFRCOCTRL_RESETVALUE   0x81060100UL
 
#define _CMU_LFRCOCTRL_TIMEOUT_16CYCLES   0x00000001UL
 
#define _CMU_LFRCOCTRL_TIMEOUT_2CYCLES   0x00000000UL
 
#define _CMU_LFRCOCTRL_TIMEOUT_32CYCLES   0x00000002UL
 
#define _CMU_LFRCOCTRL_TIMEOUT_DEFAULT   0x00000001UL
 
#define _CMU_LFRCOCTRL_TIMEOUT_MASK   0x3000000UL
 
#define _CMU_LFRCOCTRL_TIMEOUT_SHIFT   24
 
#define _CMU_LFRCOCTRL_TUNING_DEFAULT   0x00000100UL
 
#define _CMU_LFRCOCTRL_TUNING_MASK   0x1FFUL
 
#define _CMU_LFRCOCTRL_TUNING_SHIFT   0
 
#define _CMU_LFXOCTRL_AGC_DEFAULT   0x00000001UL
 
#define _CMU_LFXOCTRL_AGC_MASK   0x8000UL
 
#define _CMU_LFXOCTRL_AGC_SHIFT   15
 
#define _CMU_LFXOCTRL_BUFCUR_DEFAULT   0x00000000UL
 
#define _CMU_LFXOCTRL_BUFCUR_MASK   0x100000UL
 
#define _CMU_LFXOCTRL_BUFCUR_SHIFT   20
 
#define _CMU_LFXOCTRL_CUR_DEFAULT   0x00000000UL
 
#define _CMU_LFXOCTRL_CUR_MASK   0x30000UL
 
#define _CMU_LFXOCTRL_CUR_SHIFT   16
 
#define _CMU_LFXOCTRL_GAIN_DEFAULT   0x00000002UL
 
#define _CMU_LFXOCTRL_GAIN_MASK   0x1800UL
 
#define _CMU_LFXOCTRL_GAIN_SHIFT   11
 
#define _CMU_LFXOCTRL_HIGHAMPL_DEFAULT   0x00000000UL
 
#define _CMU_LFXOCTRL_HIGHAMPL_MASK   0x4000UL
 
#define _CMU_LFXOCTRL_HIGHAMPL_SHIFT   14
 
#define _CMU_LFXOCTRL_MASK   0x0713DB7FUL
 
#define _CMU_LFXOCTRL_MODE_BUFEXTCLK   0x00000001UL
 
#define _CMU_LFXOCTRL_MODE_DEFAULT   0x00000000UL
 
#define _CMU_LFXOCTRL_MODE_DIGEXTCLK   0x00000002UL
 
#define _CMU_LFXOCTRL_MODE_MASK   0x300UL
 
#define _CMU_LFXOCTRL_MODE_SHIFT   8
 
#define _CMU_LFXOCTRL_MODE_XTAL   0x00000000UL
 
#define _CMU_LFXOCTRL_RESETVALUE   0x07009000UL
 
#define _CMU_LFXOCTRL_TIMEOUT_16KCYCLES   0x00000006UL
 
#define _CMU_LFXOCTRL_TIMEOUT_1KCYCLES   0x00000002UL
 
#define _CMU_LFXOCTRL_TIMEOUT_256CYCLES   0x00000001UL
 
#define _CMU_LFXOCTRL_TIMEOUT_2CYCLES   0x00000000UL
 
#define _CMU_LFXOCTRL_TIMEOUT_2KCYCLES   0x00000003UL
 
#define _CMU_LFXOCTRL_TIMEOUT_32KCYCLES   0x00000007UL
 
#define _CMU_LFXOCTRL_TIMEOUT_4KCYCLES   0x00000004UL
 
#define _CMU_LFXOCTRL_TIMEOUT_8KCYCLES   0x00000005UL
 
#define _CMU_LFXOCTRL_TIMEOUT_DEFAULT   0x00000007UL
 
#define _CMU_LFXOCTRL_TIMEOUT_MASK   0x7000000UL
 
#define _CMU_LFXOCTRL_TIMEOUT_SHIFT   24
 
#define _CMU_LFXOCTRL_TUNING_DEFAULT   0x00000000UL
 
#define _CMU_LFXOCTRL_TUNING_MASK   0x7FUL
 
#define _CMU_LFXOCTRL_TUNING_SHIFT   0
 
#define _CMU_LOCK_LOCKKEY_DEFAULT   0x00000000UL
 
#define _CMU_LOCK_LOCKKEY_LOCK   0x00000000UL
 
#define _CMU_LOCK_LOCKKEY_LOCKED   0x00000001UL
 
#define _CMU_LOCK_LOCKKEY_MASK   0xFFFFUL
 
#define _CMU_LOCK_LOCKKEY_SHIFT   0
 
#define _CMU_LOCK_LOCKKEY_UNLOCK   0x0000580EUL
 
#define _CMU_LOCK_LOCKKEY_UNLOCKED   0x00000000UL
 
#define _CMU_LOCK_MASK   0x0000FFFFUL
 
#define _CMU_LOCK_RESETVALUE   0x00000000UL
 
#define _CMU_OSCENCMD_AUXHFRCODIS_DEFAULT   0x00000000UL
 
#define _CMU_OSCENCMD_AUXHFRCODIS_MASK   0x20UL
 
#define _CMU_OSCENCMD_AUXHFRCODIS_SHIFT   5
 
#define _CMU_OSCENCMD_AUXHFRCOEN_DEFAULT   0x00000000UL
 
#define _CMU_OSCENCMD_AUXHFRCOEN_MASK   0x10UL
 
#define _CMU_OSCENCMD_AUXHFRCOEN_SHIFT   4
 
#define _CMU_OSCENCMD_HFRCODIS_DEFAULT   0x00000000UL
 
#define _CMU_OSCENCMD_HFRCODIS_MASK   0x2UL
 
#define _CMU_OSCENCMD_HFRCODIS_SHIFT   1
 
#define _CMU_OSCENCMD_HFRCOEN_DEFAULT   0x00000000UL
 
#define _CMU_OSCENCMD_HFRCOEN_MASK   0x1UL
 
#define _CMU_OSCENCMD_HFRCOEN_SHIFT   0
 
#define _CMU_OSCENCMD_HFXODIS_DEFAULT   0x00000000UL
 
#define _CMU_OSCENCMD_HFXODIS_MASK   0x8UL
 
#define _CMU_OSCENCMD_HFXODIS_SHIFT   3
 
#define _CMU_OSCENCMD_HFXOEN_DEFAULT   0x00000000UL
 
#define _CMU_OSCENCMD_HFXOEN_MASK   0x4UL
 
#define _CMU_OSCENCMD_HFXOEN_SHIFT   2
 
#define _CMU_OSCENCMD_LFRCODIS_DEFAULT   0x00000000UL
 
#define _CMU_OSCENCMD_LFRCODIS_MASK   0x80UL
 
#define _CMU_OSCENCMD_LFRCODIS_SHIFT   7
 
#define _CMU_OSCENCMD_LFRCOEN_DEFAULT   0x00000000UL
 
#define _CMU_OSCENCMD_LFRCOEN_MASK   0x40UL
 
#define _CMU_OSCENCMD_LFRCOEN_SHIFT   6
 
#define _CMU_OSCENCMD_LFXODIS_DEFAULT   0x00000000UL
 
#define _CMU_OSCENCMD_LFXODIS_MASK   0x200UL
 
#define _CMU_OSCENCMD_LFXODIS_SHIFT   9
 
#define _CMU_OSCENCMD_LFXOEN_DEFAULT   0x00000000UL
 
#define _CMU_OSCENCMD_LFXOEN_MASK   0x100UL
 
#define _CMU_OSCENCMD_LFXOEN_SHIFT   8
 
#define _CMU_OSCENCMD_MASK   0x000003FFUL
 
#define _CMU_OSCENCMD_RESETVALUE   0x00000000UL
 
#define _CMU_PCNTCTRL_MASK   0x00000003UL
 
#define _CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT   0x00000000UL
 
#define _CMU_PCNTCTRL_PCNT0CLKEN_MASK   0x1UL
 
#define _CMU_PCNTCTRL_PCNT0CLKEN_SHIFT   0
 
#define _CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT   0x00000000UL
 
#define _CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK   0x00000000UL
 
#define _CMU_PCNTCTRL_PCNT0CLKSEL_MASK   0x2UL
 
#define _CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0   0x00000001UL
 
#define _CMU_PCNTCTRL_PCNT0CLKSEL_SHIFT   1
 
#define _CMU_PCNTCTRL_RESETVALUE   0x00000000UL
 
#define _CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT   0x00000000UL
 
#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC0   0x00000000UL
 
#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC1   0x00000001UL
 
#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC2   0x00000002UL
 
#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC3   0x00000003UL
 
#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC4   0x00000004UL
 
#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC5   0x00000005UL
 
#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC6   0x00000006UL
 
#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC7   0x00000007UL
 
#define _CMU_ROUTELOC0_CLKOUT0LOC_MASK   0x7UL
 
#define _CMU_ROUTELOC0_CLKOUT0LOC_SHIFT   0
 
#define _CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT   0x00000000UL
 
#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC0   0x00000000UL
 
#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC1   0x00000001UL
 
#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC2   0x00000002UL
 
#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC3   0x00000003UL
 
#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC4   0x00000004UL
 
#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC5   0x00000005UL
 
#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC6   0x00000006UL
 
#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC7   0x00000007UL
 
#define _CMU_ROUTELOC0_CLKOUT1LOC_MASK   0x700UL
 
#define _CMU_ROUTELOC0_CLKOUT1LOC_SHIFT   8
 
#define _CMU_ROUTELOC0_MASK   0x00000707UL
 
#define _CMU_ROUTELOC0_RESETVALUE   0x00000000UL
 
#define _CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT   0x00000000UL
 
#define _CMU_ROUTEPEN_CLKOUT0PEN_MASK   0x1UL
 
#define _CMU_ROUTEPEN_CLKOUT0PEN_SHIFT   0
 
#define _CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT   0x00000000UL
 
#define _CMU_ROUTEPEN_CLKOUT1PEN_MASK   0x2UL
 
#define _CMU_ROUTEPEN_CLKOUT1PEN_SHIFT   1
 
#define _CMU_ROUTEPEN_MASK   0x00000003UL
 
#define _CMU_ROUTEPEN_RESETVALUE   0x00000000UL
 
#define _CMU_STATUS_AUXHFRCOENS_DEFAULT   0x00000000UL
 
#define _CMU_STATUS_AUXHFRCOENS_MASK   0x10UL
 
#define _CMU_STATUS_AUXHFRCOENS_SHIFT   4
 
#define _CMU_STATUS_AUXHFRCORDY_DEFAULT   0x00000000UL
 
#define _CMU_STATUS_AUXHFRCORDY_MASK   0x20UL
 
#define _CMU_STATUS_AUXHFRCORDY_SHIFT   5
 
#define _CMU_STATUS_CALRDY_DEFAULT   0x00000001UL
 
#define _CMU_STATUS_CALRDY_MASK   0x10000UL
 
#define _CMU_STATUS_CALRDY_SHIFT   16
 
#define _CMU_STATUS_HFRCOENS_DEFAULT   0x00000001UL
 
#define _CMU_STATUS_HFRCOENS_MASK   0x1UL
 
#define _CMU_STATUS_HFRCOENS_SHIFT   0
 
#define _CMU_STATUS_HFRCORDY_DEFAULT   0x00000001UL
 
#define _CMU_STATUS_HFRCORDY_MASK   0x2UL
 
#define _CMU_STATUS_HFRCORDY_SHIFT   1
 
#define _CMU_STATUS_HFXOAMPHIGH_DEFAULT   0x00000000UL
 
#define _CMU_STATUS_HFXOAMPHIGH_MASK   0x1000000UL
 
#define _CMU_STATUS_HFXOAMPHIGH_SHIFT   24
 
#define _CMU_STATUS_HFXOAMPLOW_DEFAULT   0x00000000UL
 
#define _CMU_STATUS_HFXOAMPLOW_MASK   0x2000000UL
 
#define _CMU_STATUS_HFXOAMPLOW_SHIFT   25
 
#define _CMU_STATUS_HFXOENS_DEFAULT   0x00000000UL
 
#define _CMU_STATUS_HFXOENS_MASK   0x4UL
 
#define _CMU_STATUS_HFXOENS_SHIFT   2
 
#define _CMU_STATUS_HFXOPEAKDETRDY_DEFAULT   0x00000000UL
 
#define _CMU_STATUS_HFXOPEAKDETRDY_MASK   0x400000UL
 
#define _CMU_STATUS_HFXOPEAKDETRDY_SHIFT   22
 
#define _CMU_STATUS_HFXORDY_DEFAULT   0x00000000UL
 
#define _CMU_STATUS_HFXORDY_MASK   0x8UL
 
#define _CMU_STATUS_HFXORDY_SHIFT   3
 
#define _CMU_STATUS_HFXOREGILOW_DEFAULT   0x00000000UL
 
#define _CMU_STATUS_HFXOREGILOW_MASK   0x4000000UL
 
#define _CMU_STATUS_HFXOREGILOW_SHIFT   26
 
#define _CMU_STATUS_HFXOREQ_DEFAULT   0x00000000UL
 
#define _CMU_STATUS_HFXOREQ_MASK   0x200000UL
 
#define _CMU_STATUS_HFXOREQ_SHIFT   21
 
#define _CMU_STATUS_HFXOSHUNTOPTRDY_DEFAULT   0x00000000UL
 
#define _CMU_STATUS_HFXOSHUNTOPTRDY_MASK   0x800000UL
 
#define _CMU_STATUS_HFXOSHUNTOPTRDY_SHIFT   23
 
#define _CMU_STATUS_LFRCOENS_DEFAULT   0x00000000UL
 
#define _CMU_STATUS_LFRCOENS_MASK   0x40UL
 
#define _CMU_STATUS_LFRCOENS_SHIFT   6
 
#define _CMU_STATUS_LFRCORDY_DEFAULT   0x00000000UL
 
#define _CMU_STATUS_LFRCORDY_MASK   0x80UL
 
#define _CMU_STATUS_LFRCORDY_SHIFT   7
 
#define _CMU_STATUS_LFXOENS_DEFAULT   0x00000000UL
 
#define _CMU_STATUS_LFXOENS_MASK   0x100UL
 
#define _CMU_STATUS_LFXOENS_SHIFT   8
 
#define _CMU_STATUS_LFXORDY_DEFAULT   0x00000000UL
 
#define _CMU_STATUS_LFXORDY_MASK   0x200UL
 
#define _CMU_STATUS_LFXORDY_SHIFT   9
 
#define _CMU_STATUS_MASK   0x07E103FFUL
 
#define _CMU_STATUS_RESETVALUE   0x00010003UL
 
#define _CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT   0x00000000UL
 
#define _CMU_SYNCBUSY_AUXHFRCOBSY_MASK   0x2000000UL
 
#define _CMU_SYNCBUSY_AUXHFRCOBSY_SHIFT   25
 
#define _CMU_SYNCBUSY_HFRCOBSY_DEFAULT   0x00000000UL
 
#define _CMU_SYNCBUSY_HFRCOBSY_MASK   0x1000000UL
 
#define _CMU_SYNCBUSY_HFRCOBSY_SHIFT   24
 
#define _CMU_SYNCBUSY_HFXOBSY_DEFAULT   0x00000000UL
 
#define _CMU_SYNCBUSY_HFXOBSY_MASK   0x10000000UL
 
#define _CMU_SYNCBUSY_HFXOBSY_SHIFT   28
 
#define _CMU_SYNCBUSY_LFACLKEN0_DEFAULT   0x00000000UL
 
#define _CMU_SYNCBUSY_LFACLKEN0_MASK   0x1UL
 
#define _CMU_SYNCBUSY_LFACLKEN0_SHIFT   0
 
#define _CMU_SYNCBUSY_LFAPRESC0_DEFAULT   0x00000000UL
 
#define _CMU_SYNCBUSY_LFAPRESC0_MASK   0x4UL
 
#define _CMU_SYNCBUSY_LFAPRESC0_SHIFT   2
 
#define _CMU_SYNCBUSY_LFBCLKEN0_DEFAULT   0x00000000UL
 
#define _CMU_SYNCBUSY_LFBCLKEN0_MASK   0x10UL
 
#define _CMU_SYNCBUSY_LFBCLKEN0_SHIFT   4
 
#define _CMU_SYNCBUSY_LFBPRESC0_DEFAULT   0x00000000UL
 
#define _CMU_SYNCBUSY_LFBPRESC0_MASK   0x40UL
 
#define _CMU_SYNCBUSY_LFBPRESC0_SHIFT   6
 
#define _CMU_SYNCBUSY_LFECLKEN0_DEFAULT   0x00000000UL
 
#define _CMU_SYNCBUSY_LFECLKEN0_MASK   0x10000UL
 
#define _CMU_SYNCBUSY_LFECLKEN0_SHIFT   16
 
#define _CMU_SYNCBUSY_LFEPRESC0_DEFAULT   0x00000000UL
 
#define _CMU_SYNCBUSY_LFEPRESC0_MASK   0x40000UL
 
#define _CMU_SYNCBUSY_LFEPRESC0_SHIFT   18
 
#define _CMU_SYNCBUSY_LFRCOBSY_DEFAULT   0x00000000UL
 
#define _CMU_SYNCBUSY_LFRCOBSY_MASK   0x4000000UL
 
#define _CMU_SYNCBUSY_LFRCOBSY_SHIFT   26
 
#define _CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT   0x00000000UL
 
#define _CMU_SYNCBUSY_LFRCOVREFBSY_MASK   0x8000000UL
 
#define _CMU_SYNCBUSY_LFRCOVREFBSY_SHIFT   27
 
#define _CMU_SYNCBUSY_LFXOBSY_DEFAULT   0x00000000UL
 
#define _CMU_SYNCBUSY_LFXOBSY_MASK   0x20000000UL
 
#define _CMU_SYNCBUSY_LFXOBSY_SHIFT   29
 
#define _CMU_SYNCBUSY_MASK   0x3F050055UL
 
#define _CMU_SYNCBUSY_RESETVALUE   0x00000000UL
 
#define _CMU_ULFRCOCTRL_MASK   0x00030C3FUL
 
#define _CMU_ULFRCOCTRL_MODE_1KHZ   0x00000000UL
 
#define _CMU_ULFRCOCTRL_MODE_2KHZ   0x00000001UL
 
#define _CMU_ULFRCOCTRL_MODE_32KHZ   0x00000003UL
 
#define _CMU_ULFRCOCTRL_MODE_4KHZ   0x00000002UL
 
#define _CMU_ULFRCOCTRL_MODE_DEFAULT   0x00000000UL
 
#define _CMU_ULFRCOCTRL_MODE_MASK   0xC00UL
 
#define _CMU_ULFRCOCTRL_MODE_SHIFT   10
 
#define _CMU_ULFRCOCTRL_RESETVALUE   0x00020020UL
 
#define _CMU_ULFRCOCTRL_RESTRIM_DEFAULT   0x00000002UL
 
#define _CMU_ULFRCOCTRL_RESTRIM_MASK   0x30000UL
 
#define _CMU_ULFRCOCTRL_RESTRIM_SHIFT   16
 
#define _CMU_ULFRCOCTRL_TUNING_DEFAULT   0x00000020UL
 
#define _CMU_ULFRCOCTRL_TUNING_MASK   0x3FUL
 
#define _CMU_ULFRCOCTRL_TUNING_SHIFT   0
 
#define CMU_ADCCTRL_ADC0CLKINV   (0x1UL << 8)
 
#define CMU_ADCCTRL_ADC0CLKINV_DEFAULT   (_CMU_ADCCTRL_ADC0CLKINV_DEFAULT << 8)
 
#define CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO   (_CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO << 4)
 
#define CMU_ADCCTRL_ADC0CLKSEL_DEFAULT   (_CMU_ADCCTRL_ADC0CLKSEL_DEFAULT << 4)
 
#define CMU_ADCCTRL_ADC0CLKSEL_DISABLED   (_CMU_ADCCTRL_ADC0CLKSEL_DISABLED << 4)
 
#define CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK   (_CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK << 4)
 
#define CMU_ADCCTRL_ADC0CLKSEL_HFXO   (_CMU_ADCCTRL_ADC0CLKSEL_HFXO << 4)
 
#define CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT   (_CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT << 25)
 
#define CMU_AUXHFRCOCTRL_CLKDIV_DIV1   (_CMU_AUXHFRCOCTRL_CLKDIV_DIV1 << 25)
 
#define CMU_AUXHFRCOCTRL_CLKDIV_DIV2   (_CMU_AUXHFRCOCTRL_CLKDIV_DIV2 << 25)
 
#define CMU_AUXHFRCOCTRL_CLKDIV_DIV4   (_CMU_AUXHFRCOCTRL_CLKDIV_DIV4 << 25)
 
#define CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT   (_CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT << 21)
 
#define CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT   (_CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT << 8)
 
#define CMU_AUXHFRCOCTRL_FINETUNINGEN   (0x1UL << 27)
 
#define CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT   (_CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT << 27)
 
#define CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT   (_CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT << 16)
 
#define CMU_AUXHFRCOCTRL_LDOHP   (0x1UL << 24)
 
#define CMU_AUXHFRCOCTRL_LDOHP_DEFAULT   (_CMU_AUXHFRCOCTRL_LDOHP_DEFAULT << 24)
 
#define CMU_AUXHFRCOCTRL_TUNING_DEFAULT   (_CMU_AUXHFRCOCTRL_TUNING_DEFAULT << 0)
 
#define CMU_AUXHFRCOCTRL_VREFTC_DEFAULT   (_CMU_AUXHFRCOCTRL_VREFTC_DEFAULT << 28)
 
#define CMU_CALCNT_CALCNT_DEFAULT   (_CMU_CALCNT_CALCNT_DEFAULT << 0)
 
#define CMU_CALCTRL_CONT   (0x1UL << 8)
 
#define CMU_CALCTRL_CONT_DEFAULT   (_CMU_CALCTRL_CONT_DEFAULT << 8)
 
#define CMU_CALCTRL_DOWNSEL_AUXHFRCO   (_CMU_CALCTRL_DOWNSEL_AUXHFRCO << 4)
 
#define CMU_CALCTRL_DOWNSEL_DEFAULT   (_CMU_CALCTRL_DOWNSEL_DEFAULT << 4)
 
#define CMU_CALCTRL_DOWNSEL_HFCLK   (_CMU_CALCTRL_DOWNSEL_HFCLK << 4)
 
#define CMU_CALCTRL_DOWNSEL_HFRCO   (_CMU_CALCTRL_DOWNSEL_HFRCO << 4)
 
#define CMU_CALCTRL_DOWNSEL_HFXO   (_CMU_CALCTRL_DOWNSEL_HFXO << 4)
 
#define CMU_CALCTRL_DOWNSEL_LFRCO   (_CMU_CALCTRL_DOWNSEL_LFRCO << 4)
 
#define CMU_CALCTRL_DOWNSEL_LFXO   (_CMU_CALCTRL_DOWNSEL_LFXO << 4)
 
#define CMU_CALCTRL_DOWNSEL_PRS   (_CMU_CALCTRL_DOWNSEL_PRS << 4)
 
#define CMU_CALCTRL_PRSDOWNSEL_DEFAULT   (_CMU_CALCTRL_PRSDOWNSEL_DEFAULT << 24)
 
#define CMU_CALCTRL_PRSDOWNSEL_PRSCH0   (_CMU_CALCTRL_PRSDOWNSEL_PRSCH0 << 24)
 
#define CMU_CALCTRL_PRSDOWNSEL_PRSCH1   (_CMU_CALCTRL_PRSDOWNSEL_PRSCH1 << 24)
 
#define CMU_CALCTRL_PRSDOWNSEL_PRSCH10   (_CMU_CALCTRL_PRSDOWNSEL_PRSCH10 << 24)
 
#define CMU_CALCTRL_PRSDOWNSEL_PRSCH11   (_CMU_CALCTRL_PRSDOWNSEL_PRSCH11 << 24)
 
#define CMU_CALCTRL_PRSDOWNSEL_PRSCH2   (_CMU_CALCTRL_PRSDOWNSEL_PRSCH2 << 24)
 
#define CMU_CALCTRL_PRSDOWNSEL_PRSCH3   (_CMU_CALCTRL_PRSDOWNSEL_PRSCH3 << 24)
 
#define CMU_CALCTRL_PRSDOWNSEL_PRSCH4   (_CMU_CALCTRL_PRSDOWNSEL_PRSCH4 << 24)
 
#define CMU_CALCTRL_PRSDOWNSEL_PRSCH5   (_CMU_CALCTRL_PRSDOWNSEL_PRSCH5 << 24)
 
#define CMU_CALCTRL_PRSDOWNSEL_PRSCH6   (_CMU_CALCTRL_PRSDOWNSEL_PRSCH6 << 24)
 
#define CMU_CALCTRL_PRSDOWNSEL_PRSCH7   (_CMU_CALCTRL_PRSDOWNSEL_PRSCH7 << 24)
 
#define CMU_CALCTRL_PRSDOWNSEL_PRSCH8   (_CMU_CALCTRL_PRSDOWNSEL_PRSCH8 << 24)
 
#define CMU_CALCTRL_PRSDOWNSEL_PRSCH9   (_CMU_CALCTRL_PRSDOWNSEL_PRSCH9 << 24)
 
#define CMU_CALCTRL_PRSUPSEL_DEFAULT   (_CMU_CALCTRL_PRSUPSEL_DEFAULT << 16)
 
#define CMU_CALCTRL_PRSUPSEL_PRSCH0   (_CMU_CALCTRL_PRSUPSEL_PRSCH0 << 16)
 
#define CMU_CALCTRL_PRSUPSEL_PRSCH1   (_CMU_CALCTRL_PRSUPSEL_PRSCH1 << 16)
 
#define CMU_CALCTRL_PRSUPSEL_PRSCH10   (_CMU_CALCTRL_PRSUPSEL_PRSCH10 << 16)
 
#define CMU_CALCTRL_PRSUPSEL_PRSCH11   (_CMU_CALCTRL_PRSUPSEL_PRSCH11 << 16)
 
#define CMU_CALCTRL_PRSUPSEL_PRSCH2   (_CMU_CALCTRL_PRSUPSEL_PRSCH2 << 16)
 
#define CMU_CALCTRL_PRSUPSEL_PRSCH3   (_CMU_CALCTRL_PRSUPSEL_PRSCH3 << 16)
 
#define CMU_CALCTRL_PRSUPSEL_PRSCH4   (_CMU_CALCTRL_PRSUPSEL_PRSCH4 << 16)
 
#define CMU_CALCTRL_PRSUPSEL_PRSCH5   (_CMU_CALCTRL_PRSUPSEL_PRSCH5 << 16)
 
#define CMU_CALCTRL_PRSUPSEL_PRSCH6   (_CMU_CALCTRL_PRSUPSEL_PRSCH6 << 16)
 
#define CMU_CALCTRL_PRSUPSEL_PRSCH7   (_CMU_CALCTRL_PRSUPSEL_PRSCH7 << 16)
 
#define CMU_CALCTRL_PRSUPSEL_PRSCH8   (_CMU_CALCTRL_PRSUPSEL_PRSCH8 << 16)
 
#define CMU_CALCTRL_PRSUPSEL_PRSCH9   (_CMU_CALCTRL_PRSUPSEL_PRSCH9 << 16)
 
#define CMU_CALCTRL_UPSEL_AUXHFRCO   (_CMU_CALCTRL_UPSEL_AUXHFRCO << 0)
 
#define CMU_CALCTRL_UPSEL_DEFAULT   (_CMU_CALCTRL_UPSEL_DEFAULT << 0)
 
#define CMU_CALCTRL_UPSEL_HFRCO   (_CMU_CALCTRL_UPSEL_HFRCO << 0)
 
#define CMU_CALCTRL_UPSEL_HFXO   (_CMU_CALCTRL_UPSEL_HFXO << 0)
 
#define CMU_CALCTRL_UPSEL_LFRCO   (_CMU_CALCTRL_UPSEL_LFRCO << 0)
 
#define CMU_CALCTRL_UPSEL_LFXO   (_CMU_CALCTRL_UPSEL_LFXO << 0)
 
#define CMU_CALCTRL_UPSEL_PRS   (_CMU_CALCTRL_UPSEL_PRS << 0)
 
#define CMU_CMD_CALSTART   (0x1UL << 0)
 
#define CMU_CMD_CALSTART_DEFAULT   (_CMU_CMD_CALSTART_DEFAULT << 0)
 
#define CMU_CMD_CALSTOP   (0x1UL << 1)
 
#define CMU_CMD_CALSTOP_DEFAULT   (_CMU_CMD_CALSTOP_DEFAULT << 1)
 
#define CMU_CMD_HFXOPEAKDETSTART   (0x1UL << 4)
 
#define CMU_CMD_HFXOPEAKDETSTART_DEFAULT   (_CMU_CMD_HFXOPEAKDETSTART_DEFAULT << 4)
 
#define CMU_CMD_HFXOSHUNTOPTSTART   (0x1UL << 5)
 
#define CMU_CMD_HFXOSHUNTOPTSTART_DEFAULT   (_CMU_CMD_HFXOSHUNTOPTSTART_DEFAULT << 5)
 
#define CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ   (_CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ << 0)
 
#define CMU_CTRL_CLKOUTSEL0_DEFAULT   (_CMU_CTRL_CLKOUTSEL0_DEFAULT << 0)
 
#define CMU_CTRL_CLKOUTSEL0_DISABLED   (_CMU_CTRL_CLKOUTSEL0_DISABLED << 0)
 
#define CMU_CTRL_CLKOUTSEL0_HFEXPCLK   (_CMU_CTRL_CLKOUTSEL0_HFEXPCLK << 0)
 
#define CMU_CTRL_CLKOUTSEL0_HFRCOQ   (_CMU_CTRL_CLKOUTSEL0_HFRCOQ << 0)
 
#define CMU_CTRL_CLKOUTSEL0_HFSRCCLK   (_CMU_CTRL_CLKOUTSEL0_HFSRCCLK << 0)
 
#define CMU_CTRL_CLKOUTSEL0_HFXO   (_CMU_CTRL_CLKOUTSEL0_HFXO << 0)
 
#define CMU_CTRL_CLKOUTSEL0_HFXOQ   (_CMU_CTRL_CLKOUTSEL0_HFXOQ << 0)
 
#define CMU_CTRL_CLKOUTSEL0_LFRCO   (_CMU_CTRL_CLKOUTSEL0_LFRCO << 0)
 
#define CMU_CTRL_CLKOUTSEL0_LFRCOQ   (_CMU_CTRL_CLKOUTSEL0_LFRCOQ << 0)
 
#define CMU_CTRL_CLKOUTSEL0_LFXO   (_CMU_CTRL_CLKOUTSEL0_LFXO << 0)
 
#define CMU_CTRL_CLKOUTSEL0_LFXOQ   (_CMU_CTRL_CLKOUTSEL0_LFXOQ << 0)
 
#define CMU_CTRL_CLKOUTSEL0_ULFRCO   (_CMU_CTRL_CLKOUTSEL0_ULFRCO << 0)
 
#define CMU_CTRL_CLKOUTSEL0_ULFRCOQ   (_CMU_CTRL_CLKOUTSEL0_ULFRCOQ << 0)
 
#define CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ   (_CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ << 5)
 
#define CMU_CTRL_CLKOUTSEL1_DEFAULT   (_CMU_CTRL_CLKOUTSEL1_DEFAULT << 5)
 
#define CMU_CTRL_CLKOUTSEL1_DISABLED   (_CMU_CTRL_CLKOUTSEL1_DISABLED << 5)
 
#define CMU_CTRL_CLKOUTSEL1_HFEXPCLK   (_CMU_CTRL_CLKOUTSEL1_HFEXPCLK << 5)
 
#define CMU_CTRL_CLKOUTSEL1_HFRCOQ   (_CMU_CTRL_CLKOUTSEL1_HFRCOQ << 5)
 
#define CMU_CTRL_CLKOUTSEL1_HFSRCCLK   (_CMU_CTRL_CLKOUTSEL1_HFSRCCLK << 5)
 
#define CMU_CTRL_CLKOUTSEL1_HFXO   (_CMU_CTRL_CLKOUTSEL1_HFXO << 5)
 
#define CMU_CTRL_CLKOUTSEL1_HFXOQ   (_CMU_CTRL_CLKOUTSEL1_HFXOQ << 5)
 
#define CMU_CTRL_CLKOUTSEL1_LFRCO   (_CMU_CTRL_CLKOUTSEL1_LFRCO << 5)
 
#define CMU_CTRL_CLKOUTSEL1_LFRCOQ   (_CMU_CTRL_CLKOUTSEL1_LFRCOQ << 5)
 
#define CMU_CTRL_CLKOUTSEL1_LFXO   (_CMU_CTRL_CLKOUTSEL1_LFXO << 5)
 
#define CMU_CTRL_CLKOUTSEL1_LFXOQ   (_CMU_CTRL_CLKOUTSEL1_LFXOQ << 5)
 
#define CMU_CTRL_CLKOUTSEL1_ULFRCO   (_CMU_CTRL_CLKOUTSEL1_ULFRCO << 5)
 
#define CMU_CTRL_CLKOUTSEL1_ULFRCOQ   (_CMU_CTRL_CLKOUTSEL1_ULFRCOQ << 5)
 
#define CMU_CTRL_HFPERCLKEN   (0x1UL << 20)
 
#define CMU_CTRL_HFPERCLKEN_DEFAULT   (_CMU_CTRL_HFPERCLKEN_DEFAULT << 20)
 
#define CMU_CTRL_WSHFLE   (0x1UL << 16)
 
#define CMU_CTRL_WSHFLE_DEFAULT   (_CMU_CTRL_WSHFLE_DEFAULT << 16)
 
#define CMU_DBGCLKSEL_DBG_AUXHFRCO   (_CMU_DBGCLKSEL_DBG_AUXHFRCO << 0)
 
#define CMU_DBGCLKSEL_DBG_DEFAULT   (_CMU_DBGCLKSEL_DBG_DEFAULT << 0)
 
#define CMU_DBGCLKSEL_DBG_HFCLK   (_CMU_DBGCLKSEL_DBG_HFCLK << 0)
 
#define CMU_FREEZE_REGFREEZE   (0x1UL << 0)
 
#define CMU_FREEZE_REGFREEZE_DEFAULT   (_CMU_FREEZE_REGFREEZE_DEFAULT << 0)
 
#define CMU_FREEZE_REGFREEZE_FREEZE   (_CMU_FREEZE_REGFREEZE_FREEZE << 0)
 
#define CMU_FREEZE_REGFREEZE_UPDATE   (_CMU_FREEZE_REGFREEZE_UPDATE << 0)
 
#define CMU_HFBUSCLKEN0_CRYPTO   (0x1UL << 1)
 
#define CMU_HFBUSCLKEN0_CRYPTO_DEFAULT   (_CMU_HFBUSCLKEN0_CRYPTO_DEFAULT << 1)
 
#define CMU_HFBUSCLKEN0_GPCRC   (0x1UL << 5)
 
#define CMU_HFBUSCLKEN0_GPCRC_DEFAULT   (_CMU_HFBUSCLKEN0_GPCRC_DEFAULT << 5)
 
#define CMU_HFBUSCLKEN0_GPIO   (0x1UL << 2)
 
#define CMU_HFBUSCLKEN0_GPIO_DEFAULT   (_CMU_HFBUSCLKEN0_GPIO_DEFAULT << 2)
 
#define CMU_HFBUSCLKEN0_LDMA   (0x1UL << 4)
 
#define CMU_HFBUSCLKEN0_LDMA_DEFAULT   (_CMU_HFBUSCLKEN0_LDMA_DEFAULT << 4)
 
#define CMU_HFBUSCLKEN0_LE   (0x1UL << 0)
 
#define CMU_HFBUSCLKEN0_LE_DEFAULT   (_CMU_HFBUSCLKEN0_LE_DEFAULT << 0)
 
#define CMU_HFBUSCLKEN0_PRS   (0x1UL << 3)
 
#define CMU_HFBUSCLKEN0_PRS_DEFAULT   (_CMU_HFBUSCLKEN0_PRS_DEFAULT << 3)
 
#define CMU_HFCLKSEL_HF_DEFAULT   (_CMU_HFCLKSEL_HF_DEFAULT << 0)
 
#define CMU_HFCLKSEL_HF_HFRCO   (_CMU_HFCLKSEL_HF_HFRCO << 0)
 
#define CMU_HFCLKSEL_HF_HFXO   (_CMU_HFCLKSEL_HF_HFXO << 0)
 
#define CMU_HFCLKSEL_HF_LFRCO   (_CMU_HFCLKSEL_HF_LFRCO << 0)
 
#define CMU_HFCLKSEL_HF_LFXO   (_CMU_HFCLKSEL_HF_LFXO << 0)
 
#define CMU_HFCLKSTATUS_SELECTED_DEFAULT   (_CMU_HFCLKSTATUS_SELECTED_DEFAULT << 0)
 
#define CMU_HFCLKSTATUS_SELECTED_HFRCO   (_CMU_HFCLKSTATUS_SELECTED_HFRCO << 0)
 
#define CMU_HFCLKSTATUS_SELECTED_HFXO   (_CMU_HFCLKSTATUS_SELECTED_HFXO << 0)
 
#define CMU_HFCLKSTATUS_SELECTED_LFRCO   (_CMU_HFCLKSTATUS_SELECTED_LFRCO << 0)
 
#define CMU_HFCLKSTATUS_SELECTED_LFXO   (_CMU_HFCLKSTATUS_SELECTED_LFXO << 0)
 
#define CMU_HFCOREPRESC_PRESC_DEFAULT   (_CMU_HFCOREPRESC_PRESC_DEFAULT << 8)
 
#define CMU_HFCOREPRESC_PRESC_NODIVISION   (_CMU_HFCOREPRESC_PRESC_NODIVISION << 8)
 
#define CMU_HFEXPPRESC_PRESC_DEFAULT   (_CMU_HFEXPPRESC_PRESC_DEFAULT << 8)
 
#define CMU_HFEXPPRESC_PRESC_NODIVISION   (_CMU_HFEXPPRESC_PRESC_NODIVISION << 8)
 
#define CMU_HFPERCLKEN0_ACMP0   (0x1UL << 4)
 
#define CMU_HFPERCLKEN0_ACMP0_DEFAULT   (_CMU_HFPERCLKEN0_ACMP0_DEFAULT << 4)
 
#define CMU_HFPERCLKEN0_ACMP1   (0x1UL << 5)
 
#define CMU_HFPERCLKEN0_ACMP1_DEFAULT   (_CMU_HFPERCLKEN0_ACMP1_DEFAULT << 5)
 
#define CMU_HFPERCLKEN0_ADC0   (0x1UL << 8)
 
#define CMU_HFPERCLKEN0_ADC0_DEFAULT   (_CMU_HFPERCLKEN0_ADC0_DEFAULT << 8)
 
#define CMU_HFPERCLKEN0_CRYOTIMER   (0x1UL << 6)
 
#define CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT   (_CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT << 6)
 
#define CMU_HFPERCLKEN0_I2C0   (0x1UL << 7)
 
#define CMU_HFPERCLKEN0_I2C0_DEFAULT   (_CMU_HFPERCLKEN0_I2C0_DEFAULT << 7)
 
#define CMU_HFPERCLKEN0_IDAC0   (0x1UL << 9)
 
#define CMU_HFPERCLKEN0_IDAC0_DEFAULT   (_CMU_HFPERCLKEN0_IDAC0_DEFAULT << 9)
 
#define CMU_HFPERCLKEN0_TIMER0   (0x1UL << 0)
 
#define CMU_HFPERCLKEN0_TIMER0_DEFAULT   (_CMU_HFPERCLKEN0_TIMER0_DEFAULT << 0)
 
#define CMU_HFPERCLKEN0_TIMER1   (0x1UL << 1)
 
#define CMU_HFPERCLKEN0_TIMER1_DEFAULT   (_CMU_HFPERCLKEN0_TIMER1_DEFAULT << 1)
 
#define CMU_HFPERCLKEN0_USART0   (0x1UL << 2)
 
#define CMU_HFPERCLKEN0_USART0_DEFAULT   (_CMU_HFPERCLKEN0_USART0_DEFAULT << 2)
 
#define CMU_HFPERCLKEN0_USART1   (0x1UL << 3)
 
#define CMU_HFPERCLKEN0_USART1_DEFAULT   (_CMU_HFPERCLKEN0_USART1_DEFAULT << 3)
 
#define CMU_HFPERPRESC_PRESC_DEFAULT   (_CMU_HFPERPRESC_PRESC_DEFAULT << 8)
 
#define CMU_HFPERPRESC_PRESC_NODIVISION   (_CMU_HFPERPRESC_PRESC_NODIVISION << 8)
 
#define CMU_HFPRESC_HFCLKLEPRESC_DEFAULT   (_CMU_HFPRESC_HFCLKLEPRESC_DEFAULT << 24)
 
#define CMU_HFPRESC_HFCLKLEPRESC_DIV2   (_CMU_HFPRESC_HFCLKLEPRESC_DIV2 << 24)
 
#define CMU_HFPRESC_HFCLKLEPRESC_DIV4   (_CMU_HFPRESC_HFCLKLEPRESC_DIV4 << 24)
 
#define CMU_HFPRESC_PRESC_DEFAULT   (_CMU_HFPRESC_PRESC_DEFAULT << 8)
 
#define CMU_HFPRESC_PRESC_NODIVISION   (_CMU_HFPRESC_PRESC_NODIVISION << 8)
 
#define CMU_HFRCOCTRL_CLKDIV_DEFAULT   (_CMU_HFRCOCTRL_CLKDIV_DEFAULT << 25)
 
#define CMU_HFRCOCTRL_CLKDIV_DIV1   (_CMU_HFRCOCTRL_CLKDIV_DIV1 << 25)
 
#define CMU_HFRCOCTRL_CLKDIV_DIV2   (_CMU_HFRCOCTRL_CLKDIV_DIV2 << 25)
 
#define CMU_HFRCOCTRL_CLKDIV_DIV4   (_CMU_HFRCOCTRL_CLKDIV_DIV4 << 25)
 
#define CMU_HFRCOCTRL_CMPBIAS_DEFAULT   (_CMU_HFRCOCTRL_CMPBIAS_DEFAULT << 21)
 
#define CMU_HFRCOCTRL_FINETUNING_DEFAULT   (_CMU_HFRCOCTRL_FINETUNING_DEFAULT << 8)
 
#define CMU_HFRCOCTRL_FINETUNINGEN   (0x1UL << 27)
 
#define CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT   (_CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT << 27)
 
#define CMU_HFRCOCTRL_FREQRANGE_DEFAULT   (_CMU_HFRCOCTRL_FREQRANGE_DEFAULT << 16)
 
#define CMU_HFRCOCTRL_LDOHP   (0x1UL << 24)
 
#define CMU_HFRCOCTRL_LDOHP_DEFAULT   (_CMU_HFRCOCTRL_LDOHP_DEFAULT << 24)
 
#define CMU_HFRCOCTRL_TUNING_DEFAULT   (_CMU_HFRCOCTRL_TUNING_DEFAULT << 0)
 
#define CMU_HFRCOCTRL_VREFTC_DEFAULT   (_CMU_HFRCOCTRL_VREFTC_DEFAULT << 28)
 
#define CMU_HFXOCTRL1_PEAKDETTHR_DEFAULT   (_CMU_HFXOCTRL1_PEAKDETTHR_DEFAULT << 0)
 
#define CMU_HFXOCTRL1_REGLVL_DEFAULT   (_CMU_HFXOCTRL1_REGLVL_DEFAULT << 4)
 
#define CMU_HFXOCTRL1_XTIBIASEN   (0x1UL << 9)
 
#define CMU_HFXOCTRL1_XTIBIASEN_DEFAULT   (_CMU_HFXOCTRL1_XTIBIASEN_DEFAULT << 9)
 
#define CMU_HFXOCTRL_AUTOSTARTEM0EM1   (0x1UL << 28)
 
#define CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT   (_CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT << 28)
 
#define CMU_HFXOCTRL_AUTOSTARTSELEM0EM1   (0x1UL << 29)
 
#define CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT   (_CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT << 29)
 
#define CMU_HFXOCTRL_LFTIMEOUT_0CYCLES   (_CMU_HFXOCTRL_LFTIMEOUT_0CYCLES << 24)
 
#define CMU_HFXOCTRL_LFTIMEOUT_16CYCLES   (_CMU_HFXOCTRL_LFTIMEOUT_16CYCLES << 24)
 
#define CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES   (_CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES << 24)
 
#define CMU_HFXOCTRL_LFTIMEOUT_2CYCLES   (_CMU_HFXOCTRL_LFTIMEOUT_2CYCLES << 24)
 
#define CMU_HFXOCTRL_LFTIMEOUT_32CYCLES   (_CMU_HFXOCTRL_LFTIMEOUT_32CYCLES << 24)
 
#define CMU_HFXOCTRL_LFTIMEOUT_4CYCLES   (_CMU_HFXOCTRL_LFTIMEOUT_4CYCLES << 24)
 
#define CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES   (_CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES << 24)
 
#define CMU_HFXOCTRL_LFTIMEOUT_64CYCLES   (_CMU_HFXOCTRL_LFTIMEOUT_64CYCLES << 24)
 
#define CMU_HFXOCTRL_LFTIMEOUT_DEFAULT   (_CMU_HFXOCTRL_LFTIMEOUT_DEFAULT << 24)
 
#define CMU_HFXOCTRL_LOWPOWER   (0x1UL << 8)
 
#define CMU_HFXOCTRL_LOWPOWER_DEFAULT   (_CMU_HFXOCTRL_LOWPOWER_DEFAULT << 8)
 
#define CMU_HFXOCTRL_MODE   (0x1UL << 0)
 
#define CMU_HFXOCTRL_MODE_DEFAULT   (_CMU_HFXOCTRL_MODE_DEFAULT << 0)
 
#define CMU_HFXOCTRL_MODE_EXTCLK   (_CMU_HFXOCTRL_MODE_EXTCLK << 0)
 
#define CMU_HFXOCTRL_MODE_XTAL   (_CMU_HFXOCTRL_MODE_XTAL << 0)
 
#define CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_AUTOCMD   (_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_AUTOCMD << 4)
 
#define CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_CMD   (_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_CMD << 4)
 
#define CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_DEFAULT   (_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_DEFAULT << 4)
 
#define CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MANUAL   (_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MANUAL << 4)
 
#define CMU_HFXOCTRL_XTI2GND   (0x1UL << 9)
 
#define CMU_HFXOCTRL_XTI2GND_DEFAULT   (_CMU_HFXOCTRL_XTI2GND_DEFAULT << 9)
 
#define CMU_HFXOCTRL_XTO2GND   (0x1UL << 10)
 
#define CMU_HFXOCTRL_XTO2GND_DEFAULT   (_CMU_HFXOCTRL_XTO2GND_DEFAULT << 10)
 
#define CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT   (_CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT << 11)
 
#define CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT   (_CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT << 0)
 
#define CMU_HFXOSTARTUPCTRL_RESERVED0_DEFAULT   (_CMU_HFXOSTARTUPCTRL_RESERVED0_DEFAULT << 21)
 
#define CMU_HFXOSTARTUPCTRL_RESERVED1_DEFAULT   (_CMU_HFXOSTARTUPCTRL_RESERVED1_DEFAULT << 28)
 
#define CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT   (_CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT << 11)
 
#define CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT   (_CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT << 0)
 
#define CMU_HFXOSTEADYSTATECTRL_PEAKDETEN   (0x1UL << 26)
 
#define CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT   (_CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT << 26)
 
#define CMU_HFXOSTEADYSTATECTRL_REGISH_DEFAULT   (_CMU_HFXOSTEADYSTATECTRL_REGISH_DEFAULT << 7)
 
#define CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_DEFAULT   (_CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_DEFAULT << 28)
 
#define CMU_HFXOSTEADYSTATECTRL_REGSELILOW_DEFAULT   (_CMU_HFXOSTEADYSTATECTRL_REGSELILOW_DEFAULT << 24)
 
#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES   (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES << 12)
 
#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES   (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES << 12)
 
#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES   (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES << 12)
 
#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES   (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES << 12)
 
#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES   (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES << 12)
 
#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES   (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES << 12)
 
#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES   (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES << 12)
 
#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES   (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES << 12)
 
#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES   (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES << 12)
 
#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES   (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES << 12)
 
#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES   (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES << 12)
 
#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT   (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT << 12)
 
#define CMU_HFXOTIMEOUTCTRL_RESERVED2_DEFAULT   (_CMU_HFXOTIMEOUTCTRL_RESERVED2_DEFAULT << 8)
 
#define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_16CYCLES   (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_16CYCLES << 16)
 
#define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_16KCYCLES   (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_16KCYCLES << 16)
 
#define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_1KCYCLES   (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_1KCYCLES << 16)
 
#define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_256CYCLES   (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_256CYCLES << 16)
 
#define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_2CYCLES   (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_2CYCLES << 16)
 
#define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_2KCYCLES   (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_2KCYCLES << 16)
 
#define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_32CYCLES   (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_32CYCLES << 16)
 
#define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_32KCYCLES   (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_32KCYCLES << 16)
 
#define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_4CYCLES   (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_4CYCLES << 16)
 
#define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_4KCYCLES   (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_4KCYCLES << 16)
 
#define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_8KCYCLES   (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_8KCYCLES << 16)
 
#define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_DEFAULT   (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_DEFAULT << 16)
 
#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES   (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES << 0)
 
#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES   (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES << 0)
 
#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES   (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES << 0)
 
#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES   (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES << 0)
 
#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES   (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES << 0)
 
#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES   (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES << 0)
 
#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES   (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES << 0)
 
#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES   (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES << 0)
 
#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES   (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES << 0)
 
#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES   (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES << 0)
 
#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES   (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES << 0)
 
#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT   (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT << 0)
 
#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES   (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES << 4)
 
#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES   (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES << 4)
 
#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES   (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES << 4)
 
#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES   (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES << 4)
 
#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES   (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES << 4)
 
#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES   (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES << 4)
 
#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES   (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES << 4)
 
#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES   (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES << 4)
 
#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES   (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES << 4)
 
#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES   (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES << 4)
 
#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES   (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES << 4)
 
#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT   (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT << 4)
 
#define CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT   (_CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT << 0)
 
#define CMU_HFXOTRIMSTATUS_REGISH_DEFAULT   (_CMU_HFXOTRIMSTATUS_REGISH_DEFAULT << 7)
 
#define CMU_IEN_AUXHFRCORDY   (0x1UL << 4)
 
#define CMU_IEN_AUXHFRCORDY_DEFAULT   (_CMU_IEN_AUXHFRCORDY_DEFAULT << 4)
 
#define CMU_IEN_CALOF   (0x1UL << 6)
 
#define CMU_IEN_CALOF_DEFAULT   (_CMU_IEN_CALOF_DEFAULT << 6)
 
#define CMU_IEN_CALRDY   (0x1UL << 5)
 
#define CMU_IEN_CALRDY_DEFAULT   (_CMU_IEN_CALRDY_DEFAULT << 5)
 
#define CMU_IEN_CMUERR   (0x1UL << 31)
 
#define CMU_IEN_CMUERR_DEFAULT   (_CMU_IEN_CMUERR_DEFAULT << 31)
 
#define CMU_IEN_HFRCODIS   (0x1UL << 13)
 
#define CMU_IEN_HFRCODIS_DEFAULT   (_CMU_IEN_HFRCODIS_DEFAULT << 13)
 
#define CMU_IEN_HFRCORDY   (0x1UL << 0)
 
#define CMU_IEN_HFRCORDY_DEFAULT   (_CMU_IEN_HFRCORDY_DEFAULT << 0)
 
#define CMU_IEN_HFXOAUTOSW   (0x1UL << 9)
 
#define CMU_IEN_HFXOAUTOSW_DEFAULT   (_CMU_IEN_HFXOAUTOSW_DEFAULT << 9)
 
#define CMU_IEN_HFXODISERR   (0x1UL << 8)
 
#define CMU_IEN_HFXODISERR_DEFAULT   (_CMU_IEN_HFXODISERR_DEFAULT << 8)
 
#define CMU_IEN_HFXOPEAKDETERR   (0x1UL << 10)
 
#define CMU_IEN_HFXOPEAKDETERR_DEFAULT   (_CMU_IEN_HFXOPEAKDETERR_DEFAULT << 10)
 
#define CMU_IEN_HFXOPEAKDETRDY   (0x1UL << 11)
 
#define CMU_IEN_HFXOPEAKDETRDY_DEFAULT   (_CMU_IEN_HFXOPEAKDETRDY_DEFAULT << 11)
 
#define CMU_IEN_HFXORDY   (0x1UL << 1)
 
#define CMU_IEN_HFXORDY_DEFAULT   (_CMU_IEN_HFXORDY_DEFAULT << 1)
 
#define CMU_IEN_HFXOSHUNTOPTRDY   (0x1UL << 12)
 
#define CMU_IEN_HFXOSHUNTOPTRDY_DEFAULT   (_CMU_IEN_HFXOSHUNTOPTRDY_DEFAULT << 12)
 
#define CMU_IEN_LFRCORDY   (0x1UL << 2)
 
#define CMU_IEN_LFRCORDY_DEFAULT   (_CMU_IEN_LFRCORDY_DEFAULT << 2)
 
#define CMU_IEN_LFTIMEOUTERR   (0x1UL << 14)
 
#define CMU_IEN_LFTIMEOUTERR_DEFAULT   (_CMU_IEN_LFTIMEOUTERR_DEFAULT << 14)
 
#define CMU_IEN_LFXORDY   (0x1UL << 3)
 
#define CMU_IEN_LFXORDY_DEFAULT   (_CMU_IEN_LFXORDY_DEFAULT << 3)
 
#define CMU_IF_AUXHFRCORDY   (0x1UL << 4)
 
#define CMU_IF_AUXHFRCORDY_DEFAULT   (_CMU_IF_AUXHFRCORDY_DEFAULT << 4)
 
#define CMU_IF_CALOF   (0x1UL << 6)
 
#define CMU_IF_CALOF_DEFAULT   (_CMU_IF_CALOF_DEFAULT << 6)
 
#define CMU_IF_CALRDY   (0x1UL << 5)
 
#define CMU_IF_CALRDY_DEFAULT   (_CMU_IF_CALRDY_DEFAULT << 5)
 
#define CMU_IF_CMUERR   (0x1UL << 31)
 
#define CMU_IF_CMUERR_DEFAULT   (_CMU_IF_CMUERR_DEFAULT << 31)
 
#define CMU_IF_HFRCODIS   (0x1UL << 13)
 
#define CMU_IF_HFRCODIS_DEFAULT   (_CMU_IF_HFRCODIS_DEFAULT << 13)
 
#define CMU_IF_HFRCORDY   (0x1UL << 0)
 
#define CMU_IF_HFRCORDY_DEFAULT   (_CMU_IF_HFRCORDY_DEFAULT << 0)
 
#define CMU_IF_HFXOAUTOSW   (0x1UL << 9)
 
#define CMU_IF_HFXOAUTOSW_DEFAULT   (_CMU_IF_HFXOAUTOSW_DEFAULT << 9)
 
#define CMU_IF_HFXODISERR   (0x1UL << 8)
 
#define CMU_IF_HFXODISERR_DEFAULT   (_CMU_IF_HFXODISERR_DEFAULT << 8)
 
#define CMU_IF_HFXOPEAKDETERR   (0x1UL << 10)
 
#define CMU_IF_HFXOPEAKDETERR_DEFAULT   (_CMU_IF_HFXOPEAKDETERR_DEFAULT << 10)
 
#define CMU_IF_HFXOPEAKDETRDY   (0x1UL << 11)
 
#define CMU_IF_HFXOPEAKDETRDY_DEFAULT   (_CMU_IF_HFXOPEAKDETRDY_DEFAULT << 11)
 
#define CMU_IF_HFXORDY   (0x1UL << 1)
 
#define CMU_IF_HFXORDY_DEFAULT   (_CMU_IF_HFXORDY_DEFAULT << 1)
 
#define CMU_IF_HFXOSHUNTOPTRDY   (0x1UL << 12)
 
#define CMU_IF_HFXOSHUNTOPTRDY_DEFAULT   (_CMU_IF_HFXOSHUNTOPTRDY_DEFAULT << 12)
 
#define CMU_IF_LFRCORDY   (0x1UL << 2)
 
#define CMU_IF_LFRCORDY_DEFAULT   (_CMU_IF_LFRCORDY_DEFAULT << 2)
 
#define CMU_IF_LFTIMEOUTERR   (0x1UL << 14)
 
#define CMU_IF_LFTIMEOUTERR_DEFAULT   (_CMU_IF_LFTIMEOUTERR_DEFAULT << 14)
 
#define CMU_IF_LFXORDY   (0x1UL << 3)
 
#define CMU_IF_LFXORDY_DEFAULT   (_CMU_IF_LFXORDY_DEFAULT << 3)
 
#define CMU_IFC_AUXHFRCORDY   (0x1UL << 4)
 
#define CMU_IFC_AUXHFRCORDY_DEFAULT   (_CMU_IFC_AUXHFRCORDY_DEFAULT << 4)
 
#define CMU_IFC_CALOF   (0x1UL << 6)
 
#define CMU_IFC_CALOF_DEFAULT   (_CMU_IFC_CALOF_DEFAULT << 6)
 
#define CMU_IFC_CALRDY   (0x1UL << 5)
 
#define CMU_IFC_CALRDY_DEFAULT   (_CMU_IFC_CALRDY_DEFAULT << 5)
 
#define CMU_IFC_CMUERR   (0x1UL << 31)
 
#define CMU_IFC_CMUERR_DEFAULT   (_CMU_IFC_CMUERR_DEFAULT << 31)
 
#define CMU_IFC_HFRCODIS   (0x1UL << 13)
 
#define CMU_IFC_HFRCODIS_DEFAULT   (_CMU_IFC_HFRCODIS_DEFAULT << 13)
 
#define CMU_IFC_HFRCORDY   (0x1UL << 0)
 
#define CMU_IFC_HFRCORDY_DEFAULT   (_CMU_IFC_HFRCORDY_DEFAULT << 0)
 
#define CMU_IFC_HFXOAUTOSW   (0x1UL << 9)
 
#define CMU_IFC_HFXOAUTOSW_DEFAULT   (_CMU_IFC_HFXOAUTOSW_DEFAULT << 9)
 
#define CMU_IFC_HFXODISERR   (0x1UL << 8)
 
#define CMU_IFC_HFXODISERR_DEFAULT   (_CMU_IFC_HFXODISERR_DEFAULT << 8)
 
#define CMU_IFC_HFXOPEAKDETERR   (0x1UL << 10)
 
#define CMU_IFC_HFXOPEAKDETERR_DEFAULT   (_CMU_IFC_HFXOPEAKDETERR_DEFAULT << 10)
 
#define CMU_IFC_HFXOPEAKDETRDY   (0x1UL << 11)
 
#define CMU_IFC_HFXOPEAKDETRDY_DEFAULT   (_CMU_IFC_HFXOPEAKDETRDY_DEFAULT << 11)
 
#define CMU_IFC_HFXORDY   (0x1UL << 1)
 
#define CMU_IFC_HFXORDY_DEFAULT   (_CMU_IFC_HFXORDY_DEFAULT << 1)
 
#define CMU_IFC_HFXOSHUNTOPTRDY   (0x1UL << 12)
 
#define CMU_IFC_HFXOSHUNTOPTRDY_DEFAULT   (_CMU_IFC_HFXOSHUNTOPTRDY_DEFAULT << 12)
 
#define CMU_IFC_LFRCORDY   (0x1UL << 2)
 
#define CMU_IFC_LFRCORDY_DEFAULT   (_CMU_IFC_LFRCORDY_DEFAULT << 2)
 
#define CMU_IFC_LFTIMEOUTERR   (0x1UL << 14)
 
#define CMU_IFC_LFTIMEOUTERR_DEFAULT   (_CMU_IFC_LFTIMEOUTERR_DEFAULT << 14)
 
#define CMU_IFC_LFXORDY   (0x1UL << 3)
 
#define CMU_IFC_LFXORDY_DEFAULT   (_CMU_IFC_LFXORDY_DEFAULT << 3)
 
#define CMU_IFS_AUXHFRCORDY   (0x1UL << 4)
 
#define CMU_IFS_AUXHFRCORDY_DEFAULT   (_CMU_IFS_AUXHFRCORDY_DEFAULT << 4)
 
#define CMU_IFS_CALOF   (0x1UL << 6)
 
#define CMU_IFS_CALOF_DEFAULT   (_CMU_IFS_CALOF_DEFAULT << 6)
 
#define CMU_IFS_CALRDY   (0x1UL << 5)
 
#define CMU_IFS_CALRDY_DEFAULT   (_CMU_IFS_CALRDY_DEFAULT << 5)
 
#define CMU_IFS_CMUERR   (0x1UL << 31)
 
#define CMU_IFS_CMUERR_DEFAULT   (_CMU_IFS_CMUERR_DEFAULT << 31)
 
#define CMU_IFS_HFRCODIS   (0x1UL << 13)
 
#define CMU_IFS_HFRCODIS_DEFAULT   (_CMU_IFS_HFRCODIS_DEFAULT << 13)
 
#define CMU_IFS_HFRCORDY   (0x1UL << 0)
 
#define CMU_IFS_HFRCORDY_DEFAULT   (_CMU_IFS_HFRCORDY_DEFAULT << 0)
 
#define CMU_IFS_HFXOAUTOSW   (0x1UL << 9)
 
#define CMU_IFS_HFXOAUTOSW_DEFAULT   (_CMU_IFS_HFXOAUTOSW_DEFAULT << 9)
 
#define CMU_IFS_HFXODISERR   (0x1UL << 8)
 
#define CMU_IFS_HFXODISERR_DEFAULT   (_CMU_IFS_HFXODISERR_DEFAULT << 8)
 
#define CMU_IFS_HFXOPEAKDETERR   (0x1UL << 10)
 
#define CMU_IFS_HFXOPEAKDETERR_DEFAULT   (_CMU_IFS_HFXOPEAKDETERR_DEFAULT << 10)
 
#define CMU_IFS_HFXOPEAKDETRDY   (0x1UL << 11)
 
#define CMU_IFS_HFXOPEAKDETRDY_DEFAULT   (_CMU_IFS_HFXOPEAKDETRDY_DEFAULT << 11)
 
#define CMU_IFS_HFXORDY   (0x1UL << 1)
 
#define CMU_IFS_HFXORDY_DEFAULT   (_CMU_IFS_HFXORDY_DEFAULT << 1)
 
#define CMU_IFS_HFXOSHUNTOPTRDY   (0x1UL << 12)
 
#define CMU_IFS_HFXOSHUNTOPTRDY_DEFAULT   (_CMU_IFS_HFXOSHUNTOPTRDY_DEFAULT << 12)
 
#define CMU_IFS_LFRCORDY   (0x1UL << 2)
 
#define CMU_IFS_LFRCORDY_DEFAULT   (_CMU_IFS_LFRCORDY_DEFAULT << 2)
 
#define CMU_IFS_LFTIMEOUTERR   (0x1UL << 14)
 
#define CMU_IFS_LFTIMEOUTERR_DEFAULT   (_CMU_IFS_LFTIMEOUTERR_DEFAULT << 14)
 
#define CMU_IFS_LFXORDY   (0x1UL << 3)
 
#define CMU_IFS_LFXORDY_DEFAULT   (_CMU_IFS_LFXORDY_DEFAULT << 3)
 
#define CMU_LFACLKEN0_LETIMER0   (0x1UL << 0)
 
#define CMU_LFACLKEN0_LETIMER0_DEFAULT   (_CMU_LFACLKEN0_LETIMER0_DEFAULT << 0)
 
#define CMU_LFACLKSEL_LFA_DEFAULT   (_CMU_LFACLKSEL_LFA_DEFAULT << 0)
 
#define CMU_LFACLKSEL_LFA_DISABLED   (_CMU_LFACLKSEL_LFA_DISABLED << 0)
 
#define CMU_LFACLKSEL_LFA_LFRCO   (_CMU_LFACLKSEL_LFA_LFRCO << 0)
 
#define CMU_LFACLKSEL_LFA_LFXO   (_CMU_LFACLKSEL_LFA_LFXO << 0)
 
#define CMU_LFACLKSEL_LFA_ULFRCO   (_CMU_LFACLKSEL_LFA_ULFRCO << 0)
 
#define CMU_LFAPRESC0_LETIMER0_DIV1   (_CMU_LFAPRESC0_LETIMER0_DIV1 << 0)
 
#define CMU_LFAPRESC0_LETIMER0_DIV1024   (_CMU_LFAPRESC0_LETIMER0_DIV1024 << 0)
 
#define CMU_LFAPRESC0_LETIMER0_DIV128   (_CMU_LFAPRESC0_LETIMER0_DIV128 << 0)
 
#define CMU_LFAPRESC0_LETIMER0_DIV16   (_CMU_LFAPRESC0_LETIMER0_DIV16 << 0)
 
#define CMU_LFAPRESC0_LETIMER0_DIV16384   (_CMU_LFAPRESC0_LETIMER0_DIV16384 << 0)
 
#define CMU_LFAPRESC0_LETIMER0_DIV2   (_CMU_LFAPRESC0_LETIMER0_DIV2 << 0)
 
#define CMU_LFAPRESC0_LETIMER0_DIV2048   (_CMU_LFAPRESC0_LETIMER0_DIV2048 << 0)
 
#define CMU_LFAPRESC0_LETIMER0_DIV256   (_CMU_LFAPRESC0_LETIMER0_DIV256 << 0)
 
#define CMU_LFAPRESC0_LETIMER0_DIV32   (_CMU_LFAPRESC0_LETIMER0_DIV32 << 0)
 
#define CMU_LFAPRESC0_LETIMER0_DIV32768   (_CMU_LFAPRESC0_LETIMER0_DIV32768 << 0)
 
#define CMU_LFAPRESC0_LETIMER0_DIV4   (_CMU_LFAPRESC0_LETIMER0_DIV4 << 0)
 
#define CMU_LFAPRESC0_LETIMER0_DIV4096   (_CMU_LFAPRESC0_LETIMER0_DIV4096 << 0)
 
#define CMU_LFAPRESC0_LETIMER0_DIV512   (_CMU_LFAPRESC0_LETIMER0_DIV512 << 0)
 
#define CMU_LFAPRESC0_LETIMER0_DIV64   (_CMU_LFAPRESC0_LETIMER0_DIV64 << 0)
 
#define CMU_LFAPRESC0_LETIMER0_DIV8   (_CMU_LFAPRESC0_LETIMER0_DIV8 << 0)
 
#define CMU_LFAPRESC0_LETIMER0_DIV8192   (_CMU_LFAPRESC0_LETIMER0_DIV8192 << 0)
 
#define CMU_LFBCLKEN0_LEUART0   (0x1UL << 0)
 
#define CMU_LFBCLKEN0_LEUART0_DEFAULT   (_CMU_LFBCLKEN0_LEUART0_DEFAULT << 0)
 
#define CMU_LFBCLKSEL_LFB_DEFAULT   (_CMU_LFBCLKSEL_LFB_DEFAULT << 0)
 
#define CMU_LFBCLKSEL_LFB_DISABLED   (_CMU_LFBCLKSEL_LFB_DISABLED << 0)
 
#define CMU_LFBCLKSEL_LFB_HFCLKLE   (_CMU_LFBCLKSEL_LFB_HFCLKLE << 0)
 
#define CMU_LFBCLKSEL_LFB_LFRCO   (_CMU_LFBCLKSEL_LFB_LFRCO << 0)
 
#define CMU_LFBCLKSEL_LFB_LFXO   (_CMU_LFBCLKSEL_LFB_LFXO << 0)
 
#define CMU_LFBCLKSEL_LFB_ULFRCO   (_CMU_LFBCLKSEL_LFB_ULFRCO << 0)
 
#define CMU_LFBPRESC0_LEUART0_DIV1   (_CMU_LFBPRESC0_LEUART0_DIV1 << 0)
 
#define CMU_LFBPRESC0_LEUART0_DIV2   (_CMU_LFBPRESC0_LEUART0_DIV2 << 0)
 
#define CMU_LFBPRESC0_LEUART0_DIV4   (_CMU_LFBPRESC0_LEUART0_DIV4 << 0)
 
#define CMU_LFBPRESC0_LEUART0_DIV8   (_CMU_LFBPRESC0_LEUART0_DIV8 << 0)
 
#define CMU_LFECLKEN0_RTCC   (0x1UL << 0)
 
#define CMU_LFECLKEN0_RTCC_DEFAULT   (_CMU_LFECLKEN0_RTCC_DEFAULT << 0)
 
#define CMU_LFECLKSEL_LFE_DEFAULT   (_CMU_LFECLKSEL_LFE_DEFAULT << 0)
 
#define CMU_LFECLKSEL_LFE_DISABLED   (_CMU_LFECLKSEL_LFE_DISABLED << 0)
 
#define CMU_LFECLKSEL_LFE_LFRCO   (_CMU_LFECLKSEL_LFE_LFRCO << 0)
 
#define CMU_LFECLKSEL_LFE_LFXO   (_CMU_LFECLKSEL_LFE_LFXO << 0)
 
#define CMU_LFECLKSEL_LFE_ULFRCO   (_CMU_LFECLKSEL_LFE_ULFRCO << 0)
 
#define CMU_LFEPRESC0_RTCC_DIV1   (_CMU_LFEPRESC0_RTCC_DIV1 << 0)
 
#define CMU_LFRCOCTRL_ENCHOP   (0x1UL << 17)
 
#define CMU_LFRCOCTRL_ENCHOP_DEFAULT   (_CMU_LFRCOCTRL_ENCHOP_DEFAULT << 17)
 
#define CMU_LFRCOCTRL_ENDEM   (0x1UL << 18)
 
#define CMU_LFRCOCTRL_ENDEM_DEFAULT   (_CMU_LFRCOCTRL_ENDEM_DEFAULT << 18)
 
#define CMU_LFRCOCTRL_ENVREF   (0x1UL << 16)
 
#define CMU_LFRCOCTRL_ENVREF_DEFAULT   (_CMU_LFRCOCTRL_ENVREF_DEFAULT << 16)
 
#define CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT   (_CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT << 28)
 
#define CMU_LFRCOCTRL_TIMEOUT_16CYCLES   (_CMU_LFRCOCTRL_TIMEOUT_16CYCLES << 24)
 
#define CMU_LFRCOCTRL_TIMEOUT_2CYCLES   (_CMU_LFRCOCTRL_TIMEOUT_2CYCLES << 24)
 
#define CMU_LFRCOCTRL_TIMEOUT_32CYCLES   (_CMU_LFRCOCTRL_TIMEOUT_32CYCLES << 24)
 
#define CMU_LFRCOCTRL_TIMEOUT_DEFAULT   (_CMU_LFRCOCTRL_TIMEOUT_DEFAULT << 24)
 
#define CMU_LFRCOCTRL_TUNING_DEFAULT   (_CMU_LFRCOCTRL_TUNING_DEFAULT << 0)
 
#define CMU_LFXOCTRL_AGC   (0x1UL << 15)
 
#define CMU_LFXOCTRL_AGC_DEFAULT   (_CMU_LFXOCTRL_AGC_DEFAULT << 15)
 
#define CMU_LFXOCTRL_BUFCUR   (0x1UL << 20)
 
#define CMU_LFXOCTRL_BUFCUR_DEFAULT   (_CMU_LFXOCTRL_BUFCUR_DEFAULT << 20)
 
#define CMU_LFXOCTRL_CUR_DEFAULT   (_CMU_LFXOCTRL_CUR_DEFAULT << 16)
 
#define CMU_LFXOCTRL_GAIN_DEFAULT   (_CMU_LFXOCTRL_GAIN_DEFAULT << 11)
 
#define CMU_LFXOCTRL_HIGHAMPL   (0x1UL << 14)
 
#define CMU_LFXOCTRL_HIGHAMPL_DEFAULT   (_CMU_LFXOCTRL_HIGHAMPL_DEFAULT << 14)
 
#define CMU_LFXOCTRL_MODE_BUFEXTCLK   (_CMU_LFXOCTRL_MODE_BUFEXTCLK << 8)
 
#define CMU_LFXOCTRL_MODE_DEFAULT   (_CMU_LFXOCTRL_MODE_DEFAULT << 8)
 
#define CMU_LFXOCTRL_MODE_DIGEXTCLK   (_CMU_LFXOCTRL_MODE_DIGEXTCLK << 8)
 
#define CMU_LFXOCTRL_MODE_XTAL   (_CMU_LFXOCTRL_MODE_XTAL << 8)
 
#define CMU_LFXOCTRL_TIMEOUT_16KCYCLES   (_CMU_LFXOCTRL_TIMEOUT_16KCYCLES << 24)
 
#define CMU_LFXOCTRL_TIMEOUT_1KCYCLES   (_CMU_LFXOCTRL_TIMEOUT_1KCYCLES << 24)
 
#define CMU_LFXOCTRL_TIMEOUT_256CYCLES   (_CMU_LFXOCTRL_TIMEOUT_256CYCLES << 24)
 
#define CMU_LFXOCTRL_TIMEOUT_2CYCLES   (_CMU_LFXOCTRL_TIMEOUT_2CYCLES << 24)
 
#define CMU_LFXOCTRL_TIMEOUT_2KCYCLES   (_CMU_LFXOCTRL_TIMEOUT_2KCYCLES << 24)
 
#define CMU_LFXOCTRL_TIMEOUT_32KCYCLES   (_CMU_LFXOCTRL_TIMEOUT_32KCYCLES << 24)
 
#define CMU_LFXOCTRL_TIMEOUT_4KCYCLES   (_CMU_LFXOCTRL_TIMEOUT_4KCYCLES << 24)
 
#define CMU_LFXOCTRL_TIMEOUT_8KCYCLES   (_CMU_LFXOCTRL_TIMEOUT_8KCYCLES << 24)
 
#define CMU_LFXOCTRL_TIMEOUT_DEFAULT   (_CMU_LFXOCTRL_TIMEOUT_DEFAULT << 24)
 
#define CMU_LFXOCTRL_TUNING_DEFAULT   (_CMU_LFXOCTRL_TUNING_DEFAULT << 0)
 
#define CMU_LOCK_LOCKKEY_DEFAULT   (_CMU_LOCK_LOCKKEY_DEFAULT << 0)
 
#define CMU_LOCK_LOCKKEY_LOCK   (_CMU_LOCK_LOCKKEY_LOCK << 0)
 
#define CMU_LOCK_LOCKKEY_LOCKED   (_CMU_LOCK_LOCKKEY_LOCKED << 0)
 
#define CMU_LOCK_LOCKKEY_UNLOCK   (_CMU_LOCK_LOCKKEY_UNLOCK << 0)
 
#define CMU_LOCK_LOCKKEY_UNLOCKED   (_CMU_LOCK_LOCKKEY_UNLOCKED << 0)
 
#define CMU_OSCENCMD_AUXHFRCODIS   (0x1UL << 5)
 
#define CMU_OSCENCMD_AUXHFRCODIS_DEFAULT   (_CMU_OSCENCMD_AUXHFRCODIS_DEFAULT << 5)
 
#define CMU_OSCENCMD_AUXHFRCOEN   (0x1UL << 4)
 
#define CMU_OSCENCMD_AUXHFRCOEN_DEFAULT   (_CMU_OSCENCMD_AUXHFRCOEN_DEFAULT << 4)
 
#define CMU_OSCENCMD_HFRCODIS   (0x1UL << 1)
 
#define CMU_OSCENCMD_HFRCODIS_DEFAULT   (_CMU_OSCENCMD_HFRCODIS_DEFAULT << 1)
 
#define CMU_OSCENCMD_HFRCOEN   (0x1UL << 0)
 
#define CMU_OSCENCMD_HFRCOEN_DEFAULT   (_CMU_OSCENCMD_HFRCOEN_DEFAULT << 0)
 
#define CMU_OSCENCMD_HFXODIS   (0x1UL << 3)
 
#define CMU_OSCENCMD_HFXODIS_DEFAULT   (_CMU_OSCENCMD_HFXODIS_DEFAULT << 3)
 
#define CMU_OSCENCMD_HFXOEN   (0x1UL << 2)
 
#define CMU_OSCENCMD_HFXOEN_DEFAULT   (_CMU_OSCENCMD_HFXOEN_DEFAULT << 2)
 
#define CMU_OSCENCMD_LFRCODIS   (0x1UL << 7)
 
#define CMU_OSCENCMD_LFRCODIS_DEFAULT   (_CMU_OSCENCMD_LFRCODIS_DEFAULT << 7)
 
#define CMU_OSCENCMD_LFRCOEN   (0x1UL << 6)
 
#define CMU_OSCENCMD_LFRCOEN_DEFAULT   (_CMU_OSCENCMD_LFRCOEN_DEFAULT << 6)
 
#define CMU_OSCENCMD_LFXODIS   (0x1UL << 9)
 
#define CMU_OSCENCMD_LFXODIS_DEFAULT   (_CMU_OSCENCMD_LFXODIS_DEFAULT << 9)
 
#define CMU_OSCENCMD_LFXOEN   (0x1UL << 8)
 
#define CMU_OSCENCMD_LFXOEN_DEFAULT   (_CMU_OSCENCMD_LFXOEN_DEFAULT << 8)
 
#define CMU_PCNTCTRL_PCNT0CLKEN   (0x1UL << 0)
 
#define CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT   (_CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT << 0)
 
#define CMU_PCNTCTRL_PCNT0CLKSEL   (0x1UL << 1)
 
#define CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT   (_CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT << 1)
 
#define CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK   (_CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK << 1)
 
#define CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0   (_CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 << 1)
 
#define CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT   (_CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT << 0)
 
#define CMU_ROUTELOC0_CLKOUT0LOC_LOC0   (_CMU_ROUTELOC0_CLKOUT0LOC_LOC0 << 0)
 
#define CMU_ROUTELOC0_CLKOUT0LOC_LOC1   (_CMU_ROUTELOC0_CLKOUT0LOC_LOC1 << 0)
 
#define CMU_ROUTELOC0_CLKOUT0LOC_LOC2   (_CMU_ROUTELOC0_CLKOUT0LOC_LOC2 << 0)
 
#define CMU_ROUTELOC0_CLKOUT0LOC_LOC3   (_CMU_ROUTELOC0_CLKOUT0LOC_LOC3 << 0)
 
#define CMU_ROUTELOC0_CLKOUT0LOC_LOC4   (_CMU_ROUTELOC0_CLKOUT0LOC_LOC4 << 0)
 
#define CMU_ROUTELOC0_CLKOUT0LOC_LOC5   (_CMU_ROUTELOC0_CLKOUT0LOC_LOC5 << 0)
 
#define CMU_ROUTELOC0_CLKOUT0LOC_LOC6   (_CMU_ROUTELOC0_CLKOUT0LOC_LOC6 << 0)
 
#define CMU_ROUTELOC0_CLKOUT0LOC_LOC7   (_CMU_ROUTELOC0_CLKOUT0LOC_LOC7 << 0)
 
#define CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT   (_CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT << 8)
 
#define CMU_ROUTELOC0_CLKOUT1LOC_LOC0   (_CMU_ROUTELOC0_CLKOUT1LOC_LOC0 << 8)
 
#define CMU_ROUTELOC0_CLKOUT1LOC_LOC1   (_CMU_ROUTELOC0_CLKOUT1LOC_LOC1 << 8)
 
#define CMU_ROUTELOC0_CLKOUT1LOC_LOC2   (_CMU_ROUTELOC0_CLKOUT1LOC_LOC2 << 8)
 
#define CMU_ROUTELOC0_CLKOUT1LOC_LOC3   (_CMU_ROUTELOC0_CLKOUT1LOC_LOC3 << 8)
 
#define CMU_ROUTELOC0_CLKOUT1LOC_LOC4   (_CMU_ROUTELOC0_CLKOUT1LOC_LOC4 << 8)
 
#define CMU_ROUTELOC0_CLKOUT1LOC_LOC5   (_CMU_ROUTELOC0_CLKOUT1LOC_LOC5 << 8)
 
#define CMU_ROUTELOC0_CLKOUT1LOC_LOC6   (_CMU_ROUTELOC0_CLKOUT1LOC_LOC6 << 8)
 
#define CMU_ROUTELOC0_CLKOUT1LOC_LOC7   (_CMU_ROUTELOC0_CLKOUT1LOC_LOC7 << 8)
 
#define CMU_ROUTEPEN_CLKOUT0PEN   (0x1UL << 0)
 
#define CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT   (_CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT << 0)
 
#define CMU_ROUTEPEN_CLKOUT1PEN   (0x1UL << 1)
 
#define CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT   (_CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT << 1)
 
#define CMU_STATUS_AUXHFRCOENS   (0x1UL << 4)
 
#define CMU_STATUS_AUXHFRCOENS_DEFAULT   (_CMU_STATUS_AUXHFRCOENS_DEFAULT << 4)
 
#define CMU_STATUS_AUXHFRCORDY   (0x1UL << 5)
 
#define CMU_STATUS_AUXHFRCORDY_DEFAULT   (_CMU_STATUS_AUXHFRCORDY_DEFAULT << 5)
 
#define CMU_STATUS_CALRDY   (0x1UL << 16)
 
#define CMU_STATUS_CALRDY_DEFAULT   (_CMU_STATUS_CALRDY_DEFAULT << 16)
 
#define CMU_STATUS_HFRCOENS   (0x1UL << 0)
 
#define CMU_STATUS_HFRCOENS_DEFAULT   (_CMU_STATUS_HFRCOENS_DEFAULT << 0)
 
#define CMU_STATUS_HFRCORDY   (0x1UL << 1)
 
#define CMU_STATUS_HFRCORDY_DEFAULT   (_CMU_STATUS_HFRCORDY_DEFAULT << 1)
 
#define CMU_STATUS_HFXOAMPHIGH   (0x1UL << 24)
 
#define CMU_STATUS_HFXOAMPHIGH_DEFAULT   (_CMU_STATUS_HFXOAMPHIGH_DEFAULT << 24)
 
#define CMU_STATUS_HFXOAMPLOW   (0x1UL << 25)
 
#define CMU_STATUS_HFXOAMPLOW_DEFAULT   (_CMU_STATUS_HFXOAMPLOW_DEFAULT << 25)
 
#define CMU_STATUS_HFXOENS   (0x1UL << 2)
 
#define CMU_STATUS_HFXOENS_DEFAULT   (_CMU_STATUS_HFXOENS_DEFAULT << 2)
 
#define CMU_STATUS_HFXOPEAKDETRDY   (0x1UL << 22)
 
#define CMU_STATUS_HFXOPEAKDETRDY_DEFAULT   (_CMU_STATUS_HFXOPEAKDETRDY_DEFAULT << 22)
 
#define CMU_STATUS_HFXORDY   (0x1UL << 3)
 
#define CMU_STATUS_HFXORDY_DEFAULT   (_CMU_STATUS_HFXORDY_DEFAULT << 3)
 
#define CMU_STATUS_HFXOREGILOW   (0x1UL << 26)
 
#define CMU_STATUS_HFXOREGILOW_DEFAULT   (_CMU_STATUS_HFXOREGILOW_DEFAULT << 26)
 
#define CMU_STATUS_HFXOREQ   (0x1UL << 21)
 
#define CMU_STATUS_HFXOREQ_DEFAULT   (_CMU_STATUS_HFXOREQ_DEFAULT << 21)
 
#define CMU_STATUS_HFXOSHUNTOPTRDY   (0x1UL << 23)
 
#define CMU_STATUS_HFXOSHUNTOPTRDY_DEFAULT   (_CMU_STATUS_HFXOSHUNTOPTRDY_DEFAULT << 23)
 
#define CMU_STATUS_LFRCOENS   (0x1UL << 6)
 
#define CMU_STATUS_LFRCOENS_DEFAULT   (_CMU_STATUS_LFRCOENS_DEFAULT << 6)
 
#define CMU_STATUS_LFRCORDY   (0x1UL << 7)
 
#define CMU_STATUS_LFRCORDY_DEFAULT   (_CMU_STATUS_LFRCORDY_DEFAULT << 7)
 
#define CMU_STATUS_LFXOENS   (0x1UL << 8)
 
#define CMU_STATUS_LFXOENS_DEFAULT   (_CMU_STATUS_LFXOENS_DEFAULT << 8)
 
#define CMU_STATUS_LFXORDY   (0x1UL << 9)
 
#define CMU_STATUS_LFXORDY_DEFAULT   (_CMU_STATUS_LFXORDY_DEFAULT << 9)
 
#define CMU_SYNCBUSY_AUXHFRCOBSY   (0x1UL << 25)
 
#define CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT   (_CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT << 25)
 
#define CMU_SYNCBUSY_HFRCOBSY   (0x1UL << 24)
 
#define CMU_SYNCBUSY_HFRCOBSY_DEFAULT   (_CMU_SYNCBUSY_HFRCOBSY_DEFAULT << 24)
 
#define CMU_SYNCBUSY_HFXOBSY   (0x1UL << 28)
 
#define CMU_SYNCBUSY_HFXOBSY_DEFAULT   (_CMU_SYNCBUSY_HFXOBSY_DEFAULT << 28)
 
#define CMU_SYNCBUSY_LFACLKEN0   (0x1UL << 0)
 
#define CMU_SYNCBUSY_LFACLKEN0_DEFAULT   (_CMU_SYNCBUSY_LFACLKEN0_DEFAULT << 0)
 
#define CMU_SYNCBUSY_LFAPRESC0   (0x1UL << 2)
 
#define CMU_SYNCBUSY_LFAPRESC0_DEFAULT   (_CMU_SYNCBUSY_LFAPRESC0_DEFAULT << 2)
 
#define CMU_SYNCBUSY_LFBCLKEN0   (0x1UL << 4)
 
#define CMU_SYNCBUSY_LFBCLKEN0_DEFAULT   (_CMU_SYNCBUSY_LFBCLKEN0_DEFAULT << 4)
 
#define CMU_SYNCBUSY_LFBPRESC0   (0x1UL << 6)
 
#define CMU_SYNCBUSY_LFBPRESC0_DEFAULT   (_CMU_SYNCBUSY_LFBPRESC0_DEFAULT << 6)
 
#define CMU_SYNCBUSY_LFECLKEN0   (0x1UL << 16)
 
#define CMU_SYNCBUSY_LFECLKEN0_DEFAULT   (_CMU_SYNCBUSY_LFECLKEN0_DEFAULT << 16)
 
#define CMU_SYNCBUSY_LFEPRESC0   (0x1UL << 18)
 
#define CMU_SYNCBUSY_LFEPRESC0_DEFAULT   (_CMU_SYNCBUSY_LFEPRESC0_DEFAULT << 18)
 
#define CMU_SYNCBUSY_LFRCOBSY   (0x1UL << 26)
 
#define CMU_SYNCBUSY_LFRCOBSY_DEFAULT   (_CMU_SYNCBUSY_LFRCOBSY_DEFAULT << 26)
 
#define CMU_SYNCBUSY_LFRCOVREFBSY   (0x1UL << 27)
 
#define CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT   (_CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT << 27)
 
#define CMU_SYNCBUSY_LFXOBSY   (0x1UL << 29)
 
#define CMU_SYNCBUSY_LFXOBSY_DEFAULT   (_CMU_SYNCBUSY_LFXOBSY_DEFAULT << 29)
 
#define CMU_ULFRCOCTRL_MODE_1KHZ   (_CMU_ULFRCOCTRL_MODE_1KHZ << 10)
 
#define CMU_ULFRCOCTRL_MODE_2KHZ   (_CMU_ULFRCOCTRL_MODE_2KHZ << 10)
 
#define CMU_ULFRCOCTRL_MODE_32KHZ   (_CMU_ULFRCOCTRL_MODE_32KHZ << 10)
 
#define CMU_ULFRCOCTRL_MODE_4KHZ   (_CMU_ULFRCOCTRL_MODE_4KHZ << 10)
 
#define CMU_ULFRCOCTRL_MODE_DEFAULT   (_CMU_ULFRCOCTRL_MODE_DEFAULT << 10)
 
#define CMU_ULFRCOCTRL_RESTRIM_DEFAULT   (_CMU_ULFRCOCTRL_RESTRIM_DEFAULT << 16)
 
#define CMU_ULFRCOCTRL_TUNING_DEFAULT   (_CMU_ULFRCOCTRL_TUNING_DEFAULT << 0)
 

Macro Definition Documentation

#define _CMU_ADCCTRL_ADC0CLKINV_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_ADCCTRL

Definition at line 1706 of file efr32fg1p_cmu.h.

#define _CMU_ADCCTRL_ADC0CLKINV_MASK   0x100UL

Bit mask for CMU_ADC0CLKINV

Definition at line 1705 of file efr32fg1p_cmu.h.

#define _CMU_ADCCTRL_ADC0CLKINV_SHIFT   8

Shift value for CMU_ADC0CLKINV

Definition at line 1704 of file efr32fg1p_cmu.h.

#define _CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO   0x00000001UL

Mode AUXHFRCO for CMU_ADCCTRL

Definition at line 1695 of file efr32fg1p_cmu.h.

Referenced by CMU_ClockSelectSet().

#define _CMU_ADCCTRL_ADC0CLKSEL_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_ADCCTRL

Definition at line 1693 of file efr32fg1p_cmu.h.

#define _CMU_ADCCTRL_ADC0CLKSEL_DISABLED   0x00000000UL

Mode DISABLED for CMU_ADCCTRL

Definition at line 1694 of file efr32fg1p_cmu.h.

Referenced by CMU_ClockSelectSet().

#define _CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK   0x00000003UL

Mode HFSRCCLK for CMU_ADCCTRL

Definition at line 1697 of file efr32fg1p_cmu.h.

Referenced by CMU_ClockSelectSet().

#define _CMU_ADCCTRL_ADC0CLKSEL_HFXO   0x00000002UL

Mode HFXO for CMU_ADCCTRL

Definition at line 1696 of file efr32fg1p_cmu.h.

Referenced by CMU_ClockSelectSet().

#define _CMU_ADCCTRL_ADC0CLKSEL_MASK   0x30UL

Bit mask for CMU_ADC0CLKSEL

Definition at line 1692 of file efr32fg1p_cmu.h.

Referenced by CMU_ClockSelectGet(), and CMU_ClockSelectSet().

#define _CMU_ADCCTRL_ADC0CLKSEL_SHIFT   4

Shift value for CMU_ADC0CLKSEL

Definition at line 1691 of file efr32fg1p_cmu.h.

Referenced by CMU_ClockSelectSet().

#define _CMU_ADCCTRL_MASK   0x00000130UL

Mask for CMU_ADCCTRL

Definition at line 1690 of file efr32fg1p_cmu.h.

#define _CMU_ADCCTRL_RESETVALUE   0x00000000UL

Default value for CMU_ADCCTRL

Definition at line 1689 of file efr32fg1p_cmu.h.

#define _CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_AUXHFRCOCTRL

Definition at line 288 of file efr32fg1p_cmu.h.

#define _CMU_AUXHFRCOCTRL_CLKDIV_DIV1   0x00000000UL

Mode DIV1 for CMU_AUXHFRCOCTRL

Definition at line 289 of file efr32fg1p_cmu.h.

#define _CMU_AUXHFRCOCTRL_CLKDIV_DIV2   0x00000001UL

Mode DIV2 for CMU_AUXHFRCOCTRL

Definition at line 290 of file efr32fg1p_cmu.h.

#define _CMU_AUXHFRCOCTRL_CLKDIV_DIV4   0x00000002UL

Mode DIV4 for CMU_AUXHFRCOCTRL

Definition at line 291 of file efr32fg1p_cmu.h.

#define _CMU_AUXHFRCOCTRL_CLKDIV_MASK   0x6000000UL

Bit mask for CMU_CLKDIV

Definition at line 287 of file efr32fg1p_cmu.h.

Referenced by CMU_AUXHFRCOBandSet().

#define _CMU_AUXHFRCOCTRL_CLKDIV_SHIFT   25

Shift value for CMU_CLKDIV

Definition at line 286 of file efr32fg1p_cmu.h.

#define _CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT   0x00000002UL

Mode DEFAULT for CMU_AUXHFRCOCTRL

Definition at line 279 of file efr32fg1p_cmu.h.

#define _CMU_AUXHFRCOCTRL_CMPBIAS_MASK   0xE00000UL

Bit mask for CMU_CMPBIAS

Definition at line 278 of file efr32fg1p_cmu.h.

#define _CMU_AUXHFRCOCTRL_CMPBIAS_SHIFT   21

Shift value for CMU_CMPBIAS

Definition at line 277 of file efr32fg1p_cmu.h.

#define _CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT   0x0000001FUL

Mode DEFAULT for CMU_AUXHFRCOCTRL

Definition at line 271 of file efr32fg1p_cmu.h.

#define _CMU_AUXHFRCOCTRL_FINETUNING_MASK   0x3F00UL

Bit mask for CMU_FINETUNING

Definition at line 270 of file efr32fg1p_cmu.h.

#define _CMU_AUXHFRCOCTRL_FINETUNING_SHIFT   8

Shift value for CMU_FINETUNING

Definition at line 269 of file efr32fg1p_cmu.h.

#define _CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_AUXHFRCOCTRL

Definition at line 299 of file efr32fg1p_cmu.h.

#define _CMU_AUXHFRCOCTRL_FINETUNINGEN_MASK   0x8000000UL

Bit mask for CMU_FINETUNINGEN

Definition at line 298 of file efr32fg1p_cmu.h.

#define _CMU_AUXHFRCOCTRL_FINETUNINGEN_SHIFT   27

Shift value for CMU_FINETUNINGEN

Definition at line 297 of file efr32fg1p_cmu.h.

#define _CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT   0x00000008UL

Mode DEFAULT for CMU_AUXHFRCOCTRL

Definition at line 275 of file efr32fg1p_cmu.h.

#define _CMU_AUXHFRCOCTRL_FREQRANGE_MASK   0x1F0000UL

Bit mask for CMU_FREQRANGE

Definition at line 274 of file efr32fg1p_cmu.h.

#define _CMU_AUXHFRCOCTRL_FREQRANGE_SHIFT   16

Shift value for CMU_FREQRANGE

Definition at line 273 of file efr32fg1p_cmu.h.

#define _CMU_AUXHFRCOCTRL_LDOHP_DEFAULT   0x00000001UL

Mode DEFAULT for CMU_AUXHFRCOCTRL

Definition at line 284 of file efr32fg1p_cmu.h.

#define _CMU_AUXHFRCOCTRL_LDOHP_MASK   0x1000000UL

Bit mask for CMU_LDOHP

Definition at line 283 of file efr32fg1p_cmu.h.

#define _CMU_AUXHFRCOCTRL_LDOHP_SHIFT   24

Shift value for CMU_LDOHP

Definition at line 282 of file efr32fg1p_cmu.h.

#define _CMU_AUXHFRCOCTRL_MASK   0xFFFF3F7FUL

Mask for CMU_AUXHFRCOCTRL

Definition at line 264 of file efr32fg1p_cmu.h.

#define _CMU_AUXHFRCOCTRL_RESETVALUE   0xB1481F3CUL

Default value for CMU_AUXHFRCOCTRL

Definition at line 263 of file efr32fg1p_cmu.h.

#define _CMU_AUXHFRCOCTRL_TUNING_DEFAULT   0x0000003CUL

Mode DEFAULT for CMU_AUXHFRCOCTRL

Definition at line 267 of file efr32fg1p_cmu.h.

#define _CMU_AUXHFRCOCTRL_TUNING_MASK   0x7FUL

Bit mask for CMU_TUNING

Definition at line 266 of file efr32fg1p_cmu.h.

Referenced by CMU_OscillatorTuningGet(), and CMU_OscillatorTuningSet().

#define _CMU_AUXHFRCOCTRL_TUNING_SHIFT   0

Shift value for CMU_TUNING

Definition at line 265 of file efr32fg1p_cmu.h.

Referenced by CMU_OscillatorTuningGet(), and CMU_OscillatorTuningSet().

#define _CMU_AUXHFRCOCTRL_VREFTC_DEFAULT   0x0000000BUL

Mode DEFAULT for CMU_AUXHFRCOCTRL

Definition at line 303 of file efr32fg1p_cmu.h.

#define _CMU_AUXHFRCOCTRL_VREFTC_MASK   0xF0000000UL

Bit mask for CMU_VREFTC

Definition at line 302 of file efr32fg1p_cmu.h.

#define _CMU_AUXHFRCOCTRL_VREFTC_SHIFT   28

Shift value for CMU_VREFTC

Definition at line 301 of file efr32fg1p_cmu.h.

#define _CMU_CALCNT_CALCNT_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_CALCNT

Definition at line 778 of file efr32fg1p_cmu.h.

#define _CMU_CALCNT_CALCNT_MASK   0xFFFFFUL

Bit mask for CMU_CALCNT

Definition at line 777 of file efr32fg1p_cmu.h.

Referenced by CMU_Calibrate(), and CMU_CalibrateConfig().

#define _CMU_CALCNT_CALCNT_SHIFT   0

Shift value for CMU_CALCNT

Definition at line 776 of file efr32fg1p_cmu.h.

Referenced by CMU_Calibrate(), and CMU_CalibrateConfig().

#define _CMU_CALCNT_MASK   0x000FFFFFUL

Mask for CMU_CALCNT

Definition at line 775 of file efr32fg1p_cmu.h.

#define _CMU_CALCNT_RESETVALUE   0x00000000UL

Default value for CMU_CALCNT

Definition at line 774 of file efr32fg1p_cmu.h.

#define _CMU_CALCTRL_CONT_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_CALCTRL

Definition at line 714 of file efr32fg1p_cmu.h.

#define _CMU_CALCTRL_CONT_MASK   0x100UL

Bit mask for CMU_CONT

Definition at line 713 of file efr32fg1p_cmu.h.

#define _CMU_CALCTRL_CONT_SHIFT   8

Shift value for CMU_CONT

Definition at line 712 of file efr32fg1p_cmu.h.

Referenced by CMU_CalibrateCont(), and CMU_CalibrateCountGet().

#define _CMU_CALCTRL_DOWNSEL_AUXHFRCO   0x00000005UL

Mode AUXHFRCO for CMU_CALCTRL

Definition at line 701 of file efr32fg1p_cmu.h.

#define _CMU_CALCTRL_DOWNSEL_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_CALCTRL

Definition at line 695 of file efr32fg1p_cmu.h.

#define _CMU_CALCTRL_DOWNSEL_HFCLK   0x00000000UL

Mode HFCLK for CMU_CALCTRL

Definition at line 696 of file efr32fg1p_cmu.h.

#define _CMU_CALCTRL_DOWNSEL_HFRCO   0x00000003UL

Mode HFRCO for CMU_CALCTRL

Definition at line 699 of file efr32fg1p_cmu.h.

#define _CMU_CALCTRL_DOWNSEL_HFXO   0x00000001UL

Mode HFXO for CMU_CALCTRL

Definition at line 697 of file efr32fg1p_cmu.h.

#define _CMU_CALCTRL_DOWNSEL_LFRCO   0x00000004UL

Mode LFRCO for CMU_CALCTRL

Definition at line 700 of file efr32fg1p_cmu.h.

#define _CMU_CALCTRL_DOWNSEL_LFXO   0x00000002UL

Mode LFXO for CMU_CALCTRL

Definition at line 698 of file efr32fg1p_cmu.h.

#define _CMU_CALCTRL_DOWNSEL_MASK   0x70UL

Bit mask for CMU_DOWNSEL

Definition at line 694 of file efr32fg1p_cmu.h.

Referenced by CMU_CalibrateConfig().

#define _CMU_CALCTRL_DOWNSEL_PRS   0x00000006UL

Mode PRS for CMU_CALCTRL

Definition at line 702 of file efr32fg1p_cmu.h.

#define _CMU_CALCTRL_DOWNSEL_SHIFT   4

Shift value for CMU_DOWNSEL

Definition at line 693 of file efr32fg1p_cmu.h.

#define _CMU_CALCTRL_MASK   0x0F0F0177UL

Mask for CMU_CALCTRL

Definition at line 676 of file efr32fg1p_cmu.h.

#define _CMU_CALCTRL_PRSDOWNSEL_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_CALCTRL

Definition at line 746 of file efr32fg1p_cmu.h.

#define _CMU_CALCTRL_PRSDOWNSEL_MASK   0xF000000UL

Bit mask for CMU_PRSDOWNSEL

Definition at line 745 of file efr32fg1p_cmu.h.

#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH0   0x00000000UL

Mode PRSCH0 for CMU_CALCTRL

Definition at line 747 of file efr32fg1p_cmu.h.

#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH1   0x00000001UL

Mode PRSCH1 for CMU_CALCTRL

Definition at line 748 of file efr32fg1p_cmu.h.

#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH10   0x0000000AUL

Mode PRSCH10 for CMU_CALCTRL

Definition at line 757 of file efr32fg1p_cmu.h.

#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH11   0x0000000BUL

Mode PRSCH11 for CMU_CALCTRL

Definition at line 758 of file efr32fg1p_cmu.h.

#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH2   0x00000002UL

Mode PRSCH2 for CMU_CALCTRL

Definition at line 749 of file efr32fg1p_cmu.h.

#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH3   0x00000003UL

Mode PRSCH3 for CMU_CALCTRL

Definition at line 750 of file efr32fg1p_cmu.h.

#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH4   0x00000004UL

Mode PRSCH4 for CMU_CALCTRL

Definition at line 751 of file efr32fg1p_cmu.h.

#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH5   0x00000005UL

Mode PRSCH5 for CMU_CALCTRL

Definition at line 752 of file efr32fg1p_cmu.h.

#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH6   0x00000006UL

Mode PRSCH6 for CMU_CALCTRL

Definition at line 753 of file efr32fg1p_cmu.h.

#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH7   0x00000007UL

Mode PRSCH7 for CMU_CALCTRL

Definition at line 754 of file efr32fg1p_cmu.h.

#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH8   0x00000008UL

Mode PRSCH8 for CMU_CALCTRL

Definition at line 755 of file efr32fg1p_cmu.h.

#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH9   0x00000009UL

Mode PRSCH9 for CMU_CALCTRL

Definition at line 756 of file efr32fg1p_cmu.h.

#define _CMU_CALCTRL_PRSDOWNSEL_SHIFT   24

Shift value for CMU_PRSDOWNSEL

Definition at line 744 of file efr32fg1p_cmu.h.

#define _CMU_CALCTRL_PRSUPSEL_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_CALCTRL

Definition at line 718 of file efr32fg1p_cmu.h.

#define _CMU_CALCTRL_PRSUPSEL_MASK   0xF0000UL

Bit mask for CMU_PRSUPSEL

Definition at line 717 of file efr32fg1p_cmu.h.

#define _CMU_CALCTRL_PRSUPSEL_PRSCH0   0x00000000UL

Mode PRSCH0 for CMU_CALCTRL

Definition at line 719 of file efr32fg1p_cmu.h.

#define _CMU_CALCTRL_PRSUPSEL_PRSCH1   0x00000001UL

Mode PRSCH1 for CMU_CALCTRL

Definition at line 720 of file efr32fg1p_cmu.h.

#define _CMU_CALCTRL_PRSUPSEL_PRSCH10   0x0000000AUL

Mode PRSCH10 for CMU_CALCTRL

Definition at line 729 of file efr32fg1p_cmu.h.

#define _CMU_CALCTRL_PRSUPSEL_PRSCH11   0x0000000BUL

Mode PRSCH11 for CMU_CALCTRL

Definition at line 730 of file efr32fg1p_cmu.h.

#define _CMU_CALCTRL_PRSUPSEL_PRSCH2   0x00000002UL

Mode PRSCH2 for CMU_CALCTRL

Definition at line 721 of file efr32fg1p_cmu.h.

#define _CMU_CALCTRL_PRSUPSEL_PRSCH3   0x00000003UL

Mode PRSCH3 for CMU_CALCTRL

Definition at line 722 of file efr32fg1p_cmu.h.

#define _CMU_CALCTRL_PRSUPSEL_PRSCH4   0x00000004UL

Mode PRSCH4 for CMU_CALCTRL

Definition at line 723 of file efr32fg1p_cmu.h.

#define _CMU_CALCTRL_PRSUPSEL_PRSCH5   0x00000005UL

Mode PRSCH5 for CMU_CALCTRL

Definition at line 724 of file efr32fg1p_cmu.h.

#define _CMU_CALCTRL_PRSUPSEL_PRSCH6   0x00000006UL

Mode PRSCH6 for CMU_CALCTRL

Definition at line 725 of file efr32fg1p_cmu.h.

#define _CMU_CALCTRL_PRSUPSEL_PRSCH7   0x00000007UL

Mode PRSCH7 for CMU_CALCTRL

Definition at line 726 of file efr32fg1p_cmu.h.

#define _CMU_CALCTRL_PRSUPSEL_PRSCH8   0x00000008UL

Mode PRSCH8 for CMU_CALCTRL

Definition at line 727 of file efr32fg1p_cmu.h.

#define _CMU_CALCTRL_PRSUPSEL_PRSCH9   0x00000009UL

Mode PRSCH9 for CMU_CALCTRL

Definition at line 728 of file efr32fg1p_cmu.h.

#define _CMU_CALCTRL_PRSUPSEL_SHIFT   16

Shift value for CMU_PRSUPSEL

Definition at line 716 of file efr32fg1p_cmu.h.

#define _CMU_CALCTRL_RESETVALUE   0x00000000UL

Default value for CMU_CALCTRL

Definition at line 675 of file efr32fg1p_cmu.h.

#define _CMU_CALCTRL_UPSEL_AUXHFRCO   0x00000004UL

Mode AUXHFRCO for CMU_CALCTRL

Definition at line 684 of file efr32fg1p_cmu.h.

#define _CMU_CALCTRL_UPSEL_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_CALCTRL

Definition at line 679 of file efr32fg1p_cmu.h.

#define _CMU_CALCTRL_UPSEL_HFRCO   0x00000002UL

Mode HFRCO for CMU_CALCTRL

Definition at line 682 of file efr32fg1p_cmu.h.

#define _CMU_CALCTRL_UPSEL_HFXO   0x00000000UL

Mode HFXO for CMU_CALCTRL

Definition at line 680 of file efr32fg1p_cmu.h.

#define _CMU_CALCTRL_UPSEL_LFRCO   0x00000003UL

Mode LFRCO for CMU_CALCTRL

Definition at line 683 of file efr32fg1p_cmu.h.

#define _CMU_CALCTRL_UPSEL_LFXO   0x00000001UL

Mode LFXO for CMU_CALCTRL

Definition at line 681 of file efr32fg1p_cmu.h.

#define _CMU_CALCTRL_UPSEL_MASK   0x7UL

Bit mask for CMU_UPSEL

Definition at line 678 of file efr32fg1p_cmu.h.

Referenced by CMU_CalibrateConfig().

#define _CMU_CALCTRL_UPSEL_PRS   0x00000005UL

Mode PRS for CMU_CALCTRL

Definition at line 685 of file efr32fg1p_cmu.h.

#define _CMU_CALCTRL_UPSEL_SHIFT   0

Shift value for CMU_UPSEL

Definition at line 677 of file efr32fg1p_cmu.h.

#define _CMU_CMD_CALSTART_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_CMD

Definition at line 841 of file efr32fg1p_cmu.h.

#define _CMU_CMD_CALSTART_MASK   0x1UL

Bit mask for CMU_CALSTART

Definition at line 840 of file efr32fg1p_cmu.h.

#define _CMU_CMD_CALSTART_SHIFT   0

Shift value for CMU_CALSTART

Definition at line 839 of file efr32fg1p_cmu.h.

#define _CMU_CMD_CALSTOP_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_CMD

Definition at line 846 of file efr32fg1p_cmu.h.

#define _CMU_CMD_CALSTOP_MASK   0x2UL

Bit mask for CMU_CALSTOP

Definition at line 845 of file efr32fg1p_cmu.h.

#define _CMU_CMD_CALSTOP_SHIFT   1

Shift value for CMU_CALSTOP

Definition at line 844 of file efr32fg1p_cmu.h.

#define _CMU_CMD_HFXOPEAKDETSTART_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_CMD

Definition at line 851 of file efr32fg1p_cmu.h.

#define _CMU_CMD_HFXOPEAKDETSTART_MASK   0x10UL

Bit mask for CMU_HFXOPEAKDETSTART

Definition at line 850 of file efr32fg1p_cmu.h.

#define _CMU_CMD_HFXOPEAKDETSTART_SHIFT   4

Shift value for CMU_HFXOPEAKDETSTART

Definition at line 849 of file efr32fg1p_cmu.h.

#define _CMU_CMD_HFXOSHUNTOPTSTART_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_CMD

Definition at line 856 of file efr32fg1p_cmu.h.

#define _CMU_CMD_HFXOSHUNTOPTSTART_MASK   0x20UL

Bit mask for CMU_HFXOSHUNTOPTSTART

Definition at line 855 of file efr32fg1p_cmu.h.

#define _CMU_CMD_HFXOSHUNTOPTSTART_SHIFT   5

Shift value for CMU_HFXOSHUNTOPTSTART

Definition at line 854 of file efr32fg1p_cmu.h.

#define _CMU_CMD_MASK   0x00000033UL

Mask for CMU_CMD

Definition at line 837 of file efr32fg1p_cmu.h.

#define _CMU_CMD_RESETVALUE   0x00000000UL

Default value for CMU_CMD

Definition at line 836 of file efr32fg1p_cmu.h.

#define _CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ   0x0000000DUL

Mode AUXHFRCOQ for CMU_CTRL

Definition at line 160 of file efr32fg1p_cmu.h.

#define _CMU_CTRL_CLKOUTSEL0_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_CTRL

Definition at line 149 of file efr32fg1p_cmu.h.

#define _CMU_CTRL_CLKOUTSEL0_DISABLED   0x00000000UL

Mode DISABLED for CMU_CTRL

Definition at line 150 of file efr32fg1p_cmu.h.

#define _CMU_CTRL_CLKOUTSEL0_HFEXPCLK   0x00000007UL

Mode HFEXPCLK for CMU_CTRL

Definition at line 155 of file efr32fg1p_cmu.h.

#define _CMU_CTRL_CLKOUTSEL0_HFRCOQ   0x0000000CUL

Mode HFRCOQ for CMU_CTRL

Definition at line 159 of file efr32fg1p_cmu.h.

#define _CMU_CTRL_CLKOUTSEL0_HFSRCCLK   0x0000000FUL

Mode HFSRCCLK for CMU_CTRL

Definition at line 162 of file efr32fg1p_cmu.h.

#define _CMU_CTRL_CLKOUTSEL0_HFXO   0x00000006UL

Mode HFXO for CMU_CTRL

Definition at line 154 of file efr32fg1p_cmu.h.

#define _CMU_CTRL_CLKOUTSEL0_HFXOQ   0x0000000EUL

Mode HFXOQ for CMU_CTRL

Definition at line 161 of file efr32fg1p_cmu.h.

#define _CMU_CTRL_CLKOUTSEL0_LFRCO   0x00000002UL

Mode LFRCO for CMU_CTRL

Definition at line 152 of file efr32fg1p_cmu.h.

#define _CMU_CTRL_CLKOUTSEL0_LFRCOQ   0x0000000AUL

Mode LFRCOQ for CMU_CTRL

Definition at line 157 of file efr32fg1p_cmu.h.

#define _CMU_CTRL_CLKOUTSEL0_LFXO   0x00000003UL

Mode LFXO for CMU_CTRL

Definition at line 153 of file efr32fg1p_cmu.h.

#define _CMU_CTRL_CLKOUTSEL0_LFXOQ   0x0000000BUL

Mode LFXOQ for CMU_CTRL

Definition at line 158 of file efr32fg1p_cmu.h.

#define _CMU_CTRL_CLKOUTSEL0_MASK   0xFUL

Bit mask for CMU_CLKOUTSEL0

Definition at line 148 of file efr32fg1p_cmu.h.

#define _CMU_CTRL_CLKOUTSEL0_SHIFT   0

Shift value for CMU_CLKOUTSEL0

Definition at line 147 of file efr32fg1p_cmu.h.

#define _CMU_CTRL_CLKOUTSEL0_ULFRCO   0x00000001UL

Mode ULFRCO for CMU_CTRL

Definition at line 151 of file efr32fg1p_cmu.h.

#define _CMU_CTRL_CLKOUTSEL0_ULFRCOQ   0x00000009UL

Mode ULFRCOQ for CMU_CTRL

Definition at line 156 of file efr32fg1p_cmu.h.

#define _CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ   0x0000000DUL

Mode AUXHFRCOQ for CMU_CTRL

Definition at line 190 of file efr32fg1p_cmu.h.

#define _CMU_CTRL_CLKOUTSEL1_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_CTRL

Definition at line 179 of file efr32fg1p_cmu.h.

#define _CMU_CTRL_CLKOUTSEL1_DISABLED   0x00000000UL

Mode DISABLED for CMU_CTRL

Definition at line 180 of file efr32fg1p_cmu.h.

#define _CMU_CTRL_CLKOUTSEL1_HFEXPCLK   0x00000007UL

Mode HFEXPCLK for CMU_CTRL

Definition at line 185 of file efr32fg1p_cmu.h.

#define _CMU_CTRL_CLKOUTSEL1_HFRCOQ   0x0000000CUL

Mode HFRCOQ for CMU_CTRL

Definition at line 189 of file efr32fg1p_cmu.h.

#define _CMU_CTRL_CLKOUTSEL1_HFSRCCLK   0x0000000FUL

Mode HFSRCCLK for CMU_CTRL

Definition at line 192 of file efr32fg1p_cmu.h.

#define _CMU_CTRL_CLKOUTSEL1_HFXO   0x00000006UL

Mode HFXO for CMU_CTRL

Definition at line 184 of file efr32fg1p_cmu.h.

#define _CMU_CTRL_CLKOUTSEL1_HFXOQ   0x0000000EUL

Mode HFXOQ for CMU_CTRL

Definition at line 191 of file efr32fg1p_cmu.h.

#define _CMU_CTRL_CLKOUTSEL1_LFRCO   0x00000002UL

Mode LFRCO for CMU_CTRL

Definition at line 182 of file efr32fg1p_cmu.h.

#define _CMU_CTRL_CLKOUTSEL1_LFRCOQ   0x0000000AUL

Mode LFRCOQ for CMU_CTRL

Definition at line 187 of file efr32fg1p_cmu.h.

#define _CMU_CTRL_CLKOUTSEL1_LFXO   0x00000003UL

Mode LFXO for CMU_CTRL

Definition at line 183 of file efr32fg1p_cmu.h.

#define _CMU_CTRL_CLKOUTSEL1_LFXOQ   0x0000000BUL

Mode LFXOQ for CMU_CTRL

Definition at line 188 of file efr32fg1p_cmu.h.

#define _CMU_CTRL_CLKOUTSEL1_MASK   0x1E0UL

Bit mask for CMU_CLKOUTSEL1

Definition at line 178 of file efr32fg1p_cmu.h.

Referenced by adcDeInit().

#define _CMU_CTRL_CLKOUTSEL1_SHIFT   5

Shift value for CMU_CLKOUTSEL1

Definition at line 177 of file efr32fg1p_cmu.h.

#define _CMU_CTRL_CLKOUTSEL1_ULFRCO   0x00000001UL

Mode ULFRCO for CMU_CTRL

Definition at line 181 of file efr32fg1p_cmu.h.

#define _CMU_CTRL_CLKOUTSEL1_ULFRCOQ   0x00000009UL

Mode ULFRCOQ for CMU_CTRL

Definition at line 186 of file efr32fg1p_cmu.h.

#define _CMU_CTRL_HFPERCLKEN_DEFAULT   0x00000001UL

Mode DEFAULT for CMU_CTRL

Definition at line 215 of file efr32fg1p_cmu.h.

#define _CMU_CTRL_HFPERCLKEN_MASK   0x100000UL

Bit mask for CMU_HFPERCLKEN

Definition at line 214 of file efr32fg1p_cmu.h.

#define _CMU_CTRL_HFPERCLKEN_SHIFT   20

Shift value for CMU_HFPERCLKEN

Definition at line 213 of file efr32fg1p_cmu.h.

#define _CMU_CTRL_MASK   0x001101EFUL

Mask for CMU_CTRL

Definition at line 146 of file efr32fg1p_cmu.h.

#define _CMU_CTRL_RESETVALUE   0x00300000UL

Default value for CMU_CTRL

Definition at line 145 of file efr32fg1p_cmu.h.

#define _CMU_CTRL_WSHFLE_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_CTRL

Definition at line 210 of file efr32fg1p_cmu.h.

#define _CMU_CTRL_WSHFLE_MASK   0x10000UL

Bit mask for CMU_WSHFLE

Definition at line 209 of file efr32fg1p_cmu.h.

#define _CMU_CTRL_WSHFLE_SHIFT   16

Shift value for CMU_WSHFLE

Definition at line 208 of file efr32fg1p_cmu.h.

#define _CMU_DBGCLKSEL_DBG_AUXHFRCO   0x00000000UL

Mode AUXHFRCO for CMU_DBGCLKSEL

Definition at line 865 of file efr32fg1p_cmu.h.

#define _CMU_DBGCLKSEL_DBG_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_DBGCLKSEL

Definition at line 864 of file efr32fg1p_cmu.h.

#define _CMU_DBGCLKSEL_DBG_HFCLK   0x00000001UL

Mode HFCLK for CMU_DBGCLKSEL

Definition at line 866 of file efr32fg1p_cmu.h.

#define _CMU_DBGCLKSEL_DBG_MASK   0x1UL

Bit mask for CMU_DBG

Definition at line 863 of file efr32fg1p_cmu.h.

Referenced by CMU_ClockSelectGet().

#define _CMU_DBGCLKSEL_DBG_SHIFT   0

Shift value for CMU_DBG

Definition at line 862 of file efr32fg1p_cmu.h.

#define _CMU_DBGCLKSEL_MASK   0x00000001UL

Mask for CMU_DBGCLKSEL

Definition at line 861 of file efr32fg1p_cmu.h.

#define _CMU_DBGCLKSEL_RESETVALUE   0x00000000UL

Default value for CMU_DBGCLKSEL

Definition at line 860 of file efr32fg1p_cmu.h.

#define _CMU_FREEZE_MASK   0x00000001UL

Mask for CMU_FREEZE

Definition at line 1659 of file efr32fg1p_cmu.h.

#define _CMU_FREEZE_REGFREEZE_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_FREEZE

Definition at line 1663 of file efr32fg1p_cmu.h.

#define _CMU_FREEZE_REGFREEZE_FREEZE   0x00000001UL

Mode FREEZE for CMU_FREEZE

Definition at line 1665 of file efr32fg1p_cmu.h.

#define _CMU_FREEZE_REGFREEZE_MASK   0x1UL

Bit mask for CMU_REGFREEZE

Definition at line 1662 of file efr32fg1p_cmu.h.

#define _CMU_FREEZE_REGFREEZE_SHIFT   0

Shift value for CMU_REGFREEZE

Definition at line 1661 of file efr32fg1p_cmu.h.

#define _CMU_FREEZE_REGFREEZE_UPDATE   0x00000000UL

Mode UPDATE for CMU_FREEZE

Definition at line 1664 of file efr32fg1p_cmu.h.

#define _CMU_FREEZE_RESETVALUE   0x00000000UL

Default value for CMU_FREEZE

Definition at line 1658 of file efr32fg1p_cmu.h.

#define _CMU_HFBUSCLKEN0_CRYPTO_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_HFBUSCLKEN0

Definition at line 1381 of file efr32fg1p_cmu.h.

#define _CMU_HFBUSCLKEN0_CRYPTO_MASK   0x2UL

Bit mask for CMU_CRYPTO

Definition at line 1380 of file efr32fg1p_cmu.h.

#define _CMU_HFBUSCLKEN0_CRYPTO_SHIFT   1

Shift value for CMU_CRYPTO

Definition at line 1379 of file efr32fg1p_cmu.h.

#define _CMU_HFBUSCLKEN0_GPCRC_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_HFBUSCLKEN0

Definition at line 1401 of file efr32fg1p_cmu.h.

#define _CMU_HFBUSCLKEN0_GPCRC_MASK   0x20UL

Bit mask for CMU_GPCRC

Definition at line 1400 of file efr32fg1p_cmu.h.

#define _CMU_HFBUSCLKEN0_GPCRC_SHIFT   5

Shift value for CMU_GPCRC

Definition at line 1399 of file efr32fg1p_cmu.h.

#define _CMU_HFBUSCLKEN0_GPIO_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_HFBUSCLKEN0

Definition at line 1386 of file efr32fg1p_cmu.h.

#define _CMU_HFBUSCLKEN0_GPIO_MASK   0x4UL

Bit mask for CMU_GPIO

Definition at line 1385 of file efr32fg1p_cmu.h.

#define _CMU_HFBUSCLKEN0_GPIO_SHIFT   2

Shift value for CMU_GPIO

Definition at line 1384 of file efr32fg1p_cmu.h.

#define _CMU_HFBUSCLKEN0_LDMA_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_HFBUSCLKEN0

Definition at line 1396 of file efr32fg1p_cmu.h.

#define _CMU_HFBUSCLKEN0_LDMA_MASK   0x10UL

Bit mask for CMU_LDMA

Definition at line 1395 of file efr32fg1p_cmu.h.

#define _CMU_HFBUSCLKEN0_LDMA_SHIFT   4

Shift value for CMU_LDMA

Definition at line 1394 of file efr32fg1p_cmu.h.

#define _CMU_HFBUSCLKEN0_LE_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_HFBUSCLKEN0

Definition at line 1376 of file efr32fg1p_cmu.h.

#define _CMU_HFBUSCLKEN0_LE_MASK   0x1UL

Bit mask for CMU_LE

Definition at line 1375 of file efr32fg1p_cmu.h.

#define _CMU_HFBUSCLKEN0_LE_SHIFT   0

Shift value for CMU_LE

Definition at line 1374 of file efr32fg1p_cmu.h.

Referenced by CMU_ClockSelectSet().

#define _CMU_HFBUSCLKEN0_MASK   0x0000003FUL

Mask for CMU_HFBUSCLKEN0

Definition at line 1372 of file efr32fg1p_cmu.h.

#define _CMU_HFBUSCLKEN0_PRS_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_HFBUSCLKEN0

Definition at line 1391 of file efr32fg1p_cmu.h.

#define _CMU_HFBUSCLKEN0_PRS_MASK   0x8UL

Bit mask for CMU_PRS

Definition at line 1390 of file efr32fg1p_cmu.h.

#define _CMU_HFBUSCLKEN0_PRS_SHIFT   3

Shift value for CMU_PRS

Definition at line 1389 of file efr32fg1p_cmu.h.

#define _CMU_HFBUSCLKEN0_RESETVALUE   0x00000000UL

Default value for CMU_HFBUSCLKEN0

Definition at line 1371 of file efr32fg1p_cmu.h.

#define _CMU_HFCLKSEL_HF_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_HFCLKSEL

Definition at line 876 of file efr32fg1p_cmu.h.

#define _CMU_HFCLKSEL_HF_HFRCO   0x00000001UL

Mode HFRCO for CMU_HFCLKSEL

Definition at line 877 of file efr32fg1p_cmu.h.

#define _CMU_HFCLKSEL_HF_HFXO   0x00000002UL

Mode HFXO for CMU_HFCLKSEL

Definition at line 878 of file efr32fg1p_cmu.h.

#define _CMU_HFCLKSEL_HF_LFRCO   0x00000003UL

Mode LFRCO for CMU_HFCLKSEL

Definition at line 879 of file efr32fg1p_cmu.h.

#define _CMU_HFCLKSEL_HF_LFXO   0x00000004UL

Mode LFXO for CMU_HFCLKSEL

Definition at line 880 of file efr32fg1p_cmu.h.

#define _CMU_HFCLKSEL_HF_MASK   0x7UL

Bit mask for CMU_HF

Definition at line 875 of file efr32fg1p_cmu.h.

#define _CMU_HFCLKSEL_HF_SHIFT   0

Shift value for CMU_HF

Definition at line 874 of file efr32fg1p_cmu.h.

#define _CMU_HFCLKSEL_MASK   0x00000007UL

Mask for CMU_HFCLKSEL

Definition at line 873 of file efr32fg1p_cmu.h.

#define _CMU_HFCLKSEL_RESETVALUE   0x00000000UL

Default value for CMU_HFCLKSEL

Definition at line 872 of file efr32fg1p_cmu.h.

#define _CMU_HFCLKSTATUS_MASK   0x00000007UL

Mask for CMU_HFCLKSTATUS

Definition at line 1028 of file efr32fg1p_cmu.h.

#define _CMU_HFCLKSTATUS_RESETVALUE   0x00000001UL

Default value for CMU_HFCLKSTATUS

Definition at line 1027 of file efr32fg1p_cmu.h.

#define _CMU_HFCLKSTATUS_SELECTED_DEFAULT   0x00000001UL

Mode DEFAULT for CMU_HFCLKSTATUS

Definition at line 1031 of file efr32fg1p_cmu.h.

#define _CMU_HFCLKSTATUS_SELECTED_HFRCO   0x00000001UL

Mode HFRCO for CMU_HFCLKSTATUS

Definition at line 1032 of file efr32fg1p_cmu.h.

#define _CMU_HFCLKSTATUS_SELECTED_HFXO   0x00000002UL

Mode HFXO for CMU_HFCLKSTATUS

Definition at line 1033 of file efr32fg1p_cmu.h.

#define _CMU_HFCLKSTATUS_SELECTED_LFRCO   0x00000003UL

Mode LFRCO for CMU_HFCLKSTATUS

Definition at line 1034 of file efr32fg1p_cmu.h.

#define _CMU_HFCLKSTATUS_SELECTED_LFXO   0x00000004UL

Mode LFXO for CMU_HFCLKSTATUS

Definition at line 1035 of file efr32fg1p_cmu.h.

#define _CMU_HFCLKSTATUS_SELECTED_MASK   0x7UL

Bit mask for CMU_SELECTED

Definition at line 1030 of file efr32fg1p_cmu.h.

Referenced by CMU_ClockSelectGet(), SystemHFClockGet(), SystemHFXOClockSet(), and SystemLFXOClockSet().

#define _CMU_HFCLKSTATUS_SELECTED_SHIFT   0

Shift value for CMU_SELECTED

Definition at line 1029 of file efr32fg1p_cmu.h.

#define _CMU_HFCOREPRESC_MASK   0x0001FF00UL

Mask for CMU_HFCOREPRESC

Definition at line 1505 of file efr32fg1p_cmu.h.

#define _CMU_HFCOREPRESC_PRESC_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_HFCOREPRESC

Definition at line 1508 of file efr32fg1p_cmu.h.

#define _CMU_HFCOREPRESC_PRESC_MASK   0x1FF00UL

Bit mask for CMU_PRESC

Definition at line 1507 of file efr32fg1p_cmu.h.

Referenced by CMU_ClockFreqGet(), CMU_ClockPrescGet(), CMU_ClockPrescSet(), and SystemCoreClockGet().

#define _CMU_HFCOREPRESC_PRESC_NODIVISION   0x00000000UL

Mode NODIVISION for CMU_HFCOREPRESC

Definition at line 1509 of file efr32fg1p_cmu.h.

#define _CMU_HFCOREPRESC_PRESC_SHIFT   8

Shift value for CMU_PRESC

Definition at line 1506 of file efr32fg1p_cmu.h.

Referenced by CMU_ClockFreqGet(), CMU_ClockPrescGet(), CMU_ClockPrescSet(), and SystemCoreClockGet().

#define _CMU_HFCOREPRESC_RESETVALUE   0x00000000UL

Default value for CMU_HFCOREPRESC

Definition at line 1504 of file efr32fg1p_cmu.h.

#define _CMU_HFEXPPRESC_MASK   0x00001F00UL

Mask for CMU_HFEXPPRESC

Definition at line 1525 of file efr32fg1p_cmu.h.

#define _CMU_HFEXPPRESC_PRESC_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_HFEXPPRESC

Definition at line 1528 of file efr32fg1p_cmu.h.

#define _CMU_HFEXPPRESC_PRESC_MASK   0x1F00UL

Bit mask for CMU_PRESC

Definition at line 1527 of file efr32fg1p_cmu.h.

Referenced by CMU_ClockFreqGet(), CMU_ClockPrescGet(), and CMU_ClockPrescSet().

#define _CMU_HFEXPPRESC_PRESC_NODIVISION   0x00000000UL

Mode NODIVISION for CMU_HFEXPPRESC

Definition at line 1529 of file efr32fg1p_cmu.h.

#define _CMU_HFEXPPRESC_PRESC_SHIFT   8

Shift value for CMU_PRESC

Definition at line 1526 of file efr32fg1p_cmu.h.

Referenced by CMU_ClockFreqGet(), CMU_ClockPrescGet(), and CMU_ClockPrescSet().

#define _CMU_HFEXPPRESC_RESETVALUE   0x00000000UL

Default value for CMU_HFEXPPRESC

Definition at line 1524 of file efr32fg1p_cmu.h.

#define _CMU_HFPERCLKEN0_ACMP0_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_HFPERCLKEN0

Definition at line 1430 of file efr32fg1p_cmu.h.

#define _CMU_HFPERCLKEN0_ACMP0_MASK   0x10UL

Bit mask for CMU_ACMP0

Definition at line 1429 of file efr32fg1p_cmu.h.

#define _CMU_HFPERCLKEN0_ACMP0_SHIFT   4

Shift value for CMU_ACMP0

Definition at line 1428 of file efr32fg1p_cmu.h.

#define _CMU_HFPERCLKEN0_ACMP1_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_HFPERCLKEN0

Definition at line 1435 of file efr32fg1p_cmu.h.

#define _CMU_HFPERCLKEN0_ACMP1_MASK   0x20UL

Bit mask for CMU_ACMP1

Definition at line 1434 of file efr32fg1p_cmu.h.

#define _CMU_HFPERCLKEN0_ACMP1_SHIFT   5

Shift value for CMU_ACMP1

Definition at line 1433 of file efr32fg1p_cmu.h.

#define _CMU_HFPERCLKEN0_ADC0_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_HFPERCLKEN0

Definition at line 1450 of file efr32fg1p_cmu.h.

#define _CMU_HFPERCLKEN0_ADC0_MASK   0x100UL

Bit mask for CMU_ADC0

Definition at line 1449 of file efr32fg1p_cmu.h.

#define _CMU_HFPERCLKEN0_ADC0_SHIFT   8

Shift value for CMU_ADC0

Definition at line 1448 of file efr32fg1p_cmu.h.

#define _CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_HFPERCLKEN0

Definition at line 1440 of file efr32fg1p_cmu.h.

#define _CMU_HFPERCLKEN0_CRYOTIMER_MASK   0x40UL

Bit mask for CMU_CRYOTIMER

Definition at line 1439 of file efr32fg1p_cmu.h.

#define _CMU_HFPERCLKEN0_CRYOTIMER_SHIFT   6

Shift value for CMU_CRYOTIMER

Definition at line 1438 of file efr32fg1p_cmu.h.

#define _CMU_HFPERCLKEN0_I2C0_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_HFPERCLKEN0

Definition at line 1445 of file efr32fg1p_cmu.h.

#define _CMU_HFPERCLKEN0_I2C0_MASK   0x80UL

Bit mask for CMU_I2C0

Definition at line 1444 of file efr32fg1p_cmu.h.

#define _CMU_HFPERCLKEN0_I2C0_SHIFT   7

Shift value for CMU_I2C0

Definition at line 1443 of file efr32fg1p_cmu.h.

#define _CMU_HFPERCLKEN0_IDAC0_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_HFPERCLKEN0

Definition at line 1455 of file efr32fg1p_cmu.h.

#define _CMU_HFPERCLKEN0_IDAC0_MASK   0x200UL

Bit mask for CMU_IDAC0

Definition at line 1454 of file efr32fg1p_cmu.h.

#define _CMU_HFPERCLKEN0_IDAC0_SHIFT   9

Shift value for CMU_IDAC0

Definition at line 1453 of file efr32fg1p_cmu.h.

#define _CMU_HFPERCLKEN0_MASK   0x000003FFUL

Mask for CMU_HFPERCLKEN0

Definition at line 1406 of file efr32fg1p_cmu.h.

#define _CMU_HFPERCLKEN0_RESETVALUE   0x00000000UL

Default value for CMU_HFPERCLKEN0

Definition at line 1405 of file efr32fg1p_cmu.h.

#define _CMU_HFPERCLKEN0_TIMER0_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_HFPERCLKEN0

Definition at line 1410 of file efr32fg1p_cmu.h.

#define _CMU_HFPERCLKEN0_TIMER0_MASK   0x1UL

Bit mask for CMU_TIMER0

Definition at line 1409 of file efr32fg1p_cmu.h.

#define _CMU_HFPERCLKEN0_TIMER0_SHIFT   0

Shift value for CMU_TIMER0

Definition at line 1408 of file efr32fg1p_cmu.h.

#define _CMU_HFPERCLKEN0_TIMER1_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_HFPERCLKEN0

Definition at line 1415 of file efr32fg1p_cmu.h.

#define _CMU_HFPERCLKEN0_TIMER1_MASK   0x2UL

Bit mask for CMU_TIMER1

Definition at line 1414 of file efr32fg1p_cmu.h.

#define _CMU_HFPERCLKEN0_TIMER1_SHIFT   1

Shift value for CMU_TIMER1

Definition at line 1413 of file efr32fg1p_cmu.h.

#define _CMU_HFPERCLKEN0_USART0_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_HFPERCLKEN0

Definition at line 1420 of file efr32fg1p_cmu.h.

#define _CMU_HFPERCLKEN0_USART0_MASK   0x4UL

Bit mask for CMU_USART0

Definition at line 1419 of file efr32fg1p_cmu.h.

#define _CMU_HFPERCLKEN0_USART0_SHIFT   2

Shift value for CMU_USART0

Definition at line 1418 of file efr32fg1p_cmu.h.

#define _CMU_HFPERCLKEN0_USART1_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_HFPERCLKEN0

Definition at line 1425 of file efr32fg1p_cmu.h.

#define _CMU_HFPERCLKEN0_USART1_MASK   0x8UL

Bit mask for CMU_USART1

Definition at line 1424 of file efr32fg1p_cmu.h.

#define _CMU_HFPERCLKEN0_USART1_SHIFT   3

Shift value for CMU_USART1

Definition at line 1423 of file efr32fg1p_cmu.h.

#define _CMU_HFPERPRESC_MASK   0x0001FF00UL

Mask for CMU_HFPERPRESC

Definition at line 1515 of file efr32fg1p_cmu.h.

#define _CMU_HFPERPRESC_PRESC_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_HFPERPRESC

Definition at line 1518 of file efr32fg1p_cmu.h.

#define _CMU_HFPERPRESC_PRESC_MASK   0x1FF00UL

Bit mask for CMU_PRESC

Definition at line 1517 of file efr32fg1p_cmu.h.

Referenced by CMU_ClockFreqGet(), CMU_ClockPrescGet(), and CMU_ClockPrescSet().

#define _CMU_HFPERPRESC_PRESC_NODIVISION   0x00000000UL

Mode NODIVISION for CMU_HFPERPRESC

Definition at line 1519 of file efr32fg1p_cmu.h.

#define _CMU_HFPERPRESC_PRESC_SHIFT   8

Shift value for CMU_PRESC

Definition at line 1516 of file efr32fg1p_cmu.h.

Referenced by CMU_ClockFreqGet(), CMU_ClockPrescGet(), and CMU_ClockPrescSet().

#define _CMU_HFPERPRESC_RESETVALUE   0x00000000UL

Default value for CMU_HFPERPRESC

Definition at line 1514 of file efr32fg1p_cmu.h.

#define _CMU_HFPRESC_HFCLKLEPRESC_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_HFPRESC

Definition at line 1496 of file efr32fg1p_cmu.h.

#define _CMU_HFPRESC_HFCLKLEPRESC_DIV2   0x00000000UL

Mode DIV2 for CMU_HFPRESC

Definition at line 1497 of file efr32fg1p_cmu.h.

#define _CMU_HFPRESC_HFCLKLEPRESC_DIV4   0x00000001UL

Mode DIV4 for CMU_HFPRESC

Definition at line 1498 of file efr32fg1p_cmu.h.

#define _CMU_HFPRESC_HFCLKLEPRESC_MASK   0x1000000UL

Bit mask for CMU_HFCLKLEPRESC

Definition at line 1495 of file efr32fg1p_cmu.h.

Referenced by CMU_ClockPrescGet(), and CMU_ClockPrescSet().

#define _CMU_HFPRESC_HFCLKLEPRESC_SHIFT   24

Shift value for CMU_HFCLKLEPRESC

Definition at line 1494 of file efr32fg1p_cmu.h.

Referenced by CMU_ClockPrescGet(), and CMU_ClockPrescSet().

#define _CMU_HFPRESC_MASK   0x01001F00UL

Mask for CMU_HFPRESC

Definition at line 1487 of file efr32fg1p_cmu.h.

#define _CMU_HFPRESC_PRESC_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_HFPRESC

Definition at line 1490 of file efr32fg1p_cmu.h.

#define _CMU_HFPRESC_PRESC_MASK   0x1F00UL

Bit mask for CMU_PRESC

Definition at line 1489 of file efr32fg1p_cmu.h.

Referenced by CMU_ClockPrescGet(), CMU_ClockPrescSet(), and SystemHFClockGet().

#define _CMU_HFPRESC_PRESC_NODIVISION   0x00000000UL

Mode NODIVISION for CMU_HFPRESC

Definition at line 1491 of file efr32fg1p_cmu.h.

#define _CMU_HFPRESC_PRESC_SHIFT   8

Shift value for CMU_PRESC

Definition at line 1488 of file efr32fg1p_cmu.h.

Referenced by CMU_ClockPrescGet(), CMU_ClockPrescSet(), and SystemHFClockGet().

#define _CMU_HFPRESC_RESETVALUE   0x00000000UL

Default value for CMU_HFPRESC

Definition at line 1486 of file efr32fg1p_cmu.h.

#define _CMU_HFRCOCTRL_CLKDIV_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_HFRCOCTRL

Definition at line 244 of file efr32fg1p_cmu.h.

#define _CMU_HFRCOCTRL_CLKDIV_DIV1   0x00000000UL

Mode DIV1 for CMU_HFRCOCTRL

Definition at line 245 of file efr32fg1p_cmu.h.

#define _CMU_HFRCOCTRL_CLKDIV_DIV2   0x00000001UL

Mode DIV2 for CMU_HFRCOCTRL

Definition at line 246 of file efr32fg1p_cmu.h.

#define _CMU_HFRCOCTRL_CLKDIV_DIV4   0x00000002UL

Mode DIV4 for CMU_HFRCOCTRL

Definition at line 247 of file efr32fg1p_cmu.h.

#define _CMU_HFRCOCTRL_CLKDIV_MASK   0x6000000UL

Bit mask for CMU_CLKDIV

Definition at line 243 of file efr32fg1p_cmu.h.

Referenced by CMU_HFRCOBandSet(), and EMU_EnterEM4().

#define _CMU_HFRCOCTRL_CLKDIV_SHIFT   25

Shift value for CMU_CLKDIV

Definition at line 242 of file efr32fg1p_cmu.h.

#define _CMU_HFRCOCTRL_CMPBIAS_DEFAULT   0x00000002UL

Mode DEFAULT for CMU_HFRCOCTRL

Definition at line 235 of file efr32fg1p_cmu.h.

#define _CMU_HFRCOCTRL_CMPBIAS_MASK   0xE00000UL

Bit mask for CMU_CMPBIAS

Definition at line 234 of file efr32fg1p_cmu.h.

#define _CMU_HFRCOCTRL_CMPBIAS_SHIFT   21

Shift value for CMU_CMPBIAS

Definition at line 233 of file efr32fg1p_cmu.h.

#define _CMU_HFRCOCTRL_FINETUNING_DEFAULT   0x0000001FUL

Mode DEFAULT for CMU_HFRCOCTRL

Definition at line 227 of file efr32fg1p_cmu.h.

#define _CMU_HFRCOCTRL_FINETUNING_MASK   0x3F00UL

Bit mask for CMU_FINETUNING

Definition at line 226 of file efr32fg1p_cmu.h.

#define _CMU_HFRCOCTRL_FINETUNING_SHIFT   8

Shift value for CMU_FINETUNING

Definition at line 225 of file efr32fg1p_cmu.h.

#define _CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_HFRCOCTRL

Definition at line 255 of file efr32fg1p_cmu.h.

#define _CMU_HFRCOCTRL_FINETUNINGEN_MASK   0x8000000UL

Bit mask for CMU_FINETUNINGEN

Definition at line 254 of file efr32fg1p_cmu.h.

#define _CMU_HFRCOCTRL_FINETUNINGEN_SHIFT   27

Shift value for CMU_FINETUNINGEN

Definition at line 253 of file efr32fg1p_cmu.h.

#define _CMU_HFRCOCTRL_FREQRANGE_DEFAULT   0x00000008UL

Mode DEFAULT for CMU_HFRCOCTRL

Definition at line 231 of file efr32fg1p_cmu.h.

#define _CMU_HFRCOCTRL_FREQRANGE_MASK   0x1F0000UL

Bit mask for CMU_FREQRANGE

Definition at line 230 of file efr32fg1p_cmu.h.

#define _CMU_HFRCOCTRL_FREQRANGE_SHIFT   16

Shift value for CMU_FREQRANGE

Definition at line 229 of file efr32fg1p_cmu.h.

#define _CMU_HFRCOCTRL_LDOHP_DEFAULT   0x00000001UL

Mode DEFAULT for CMU_HFRCOCTRL

Definition at line 240 of file efr32fg1p_cmu.h.

#define _CMU_HFRCOCTRL_LDOHP_MASK   0x1000000UL

Bit mask for CMU_LDOHP

Definition at line 239 of file efr32fg1p_cmu.h.

#define _CMU_HFRCOCTRL_LDOHP_SHIFT   24

Shift value for CMU_LDOHP

Definition at line 238 of file efr32fg1p_cmu.h.

#define _CMU_HFRCOCTRL_MASK   0xFFFF3F7FUL

Mask for CMU_HFRCOCTRL

Definition at line 220 of file efr32fg1p_cmu.h.

#define _CMU_HFRCOCTRL_RESETVALUE   0xB1481F3CUL

Default value for CMU_HFRCOCTRL

Definition at line 219 of file efr32fg1p_cmu.h.

#define _CMU_HFRCOCTRL_TUNING_DEFAULT   0x0000003CUL

Mode DEFAULT for CMU_HFRCOCTRL

Definition at line 223 of file efr32fg1p_cmu.h.

#define _CMU_HFRCOCTRL_TUNING_MASK   0x7FUL

Bit mask for CMU_TUNING

Definition at line 222 of file efr32fg1p_cmu.h.

Referenced by CMU_OscillatorTuningGet(), and CMU_OscillatorTuningSet().

#define _CMU_HFRCOCTRL_TUNING_SHIFT   0

Shift value for CMU_TUNING

Definition at line 221 of file efr32fg1p_cmu.h.

Referenced by CMU_OscillatorTuningGet(), and CMU_OscillatorTuningSet().

#define _CMU_HFRCOCTRL_VREFTC_DEFAULT   0x0000000BUL

Mode DEFAULT for CMU_HFRCOCTRL

Definition at line 259 of file efr32fg1p_cmu.h.

#define _CMU_HFRCOCTRL_VREFTC_MASK   0xF0000000UL

Bit mask for CMU_VREFTC

Definition at line 258 of file efr32fg1p_cmu.h.

#define _CMU_HFRCOCTRL_VREFTC_SHIFT   28

Shift value for CMU_VREFTC

Definition at line 257 of file efr32fg1p_cmu.h.

#define _CMU_HFXOCTRL1_MASK   0x00000277UL

Mask for CMU_HFXOCTRL1

Definition at line 413 of file efr32fg1p_cmu.h.

#define _CMU_HFXOCTRL1_PEAKDETTHR_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_HFXOCTRL1

Definition at line 416 of file efr32fg1p_cmu.h.

#define _CMU_HFXOCTRL1_PEAKDETTHR_MASK   0x7UL

Bit mask for CMU_PEAKDETTHR

Definition at line 415 of file efr32fg1p_cmu.h.

Referenced by CMU_HFXOInit().

#define _CMU_HFXOCTRL1_PEAKDETTHR_SHIFT   0

Shift value for CMU_PEAKDETTHR

Definition at line 414 of file efr32fg1p_cmu.h.

Referenced by CMU_HFXOInit().

#define _CMU_HFXOCTRL1_REGLVL_DEFAULT   0x00000004UL

Mode DEFAULT for CMU_HFXOCTRL1

Definition at line 420 of file efr32fg1p_cmu.h.

#define _CMU_HFXOCTRL1_REGLVL_MASK   0x70UL

Bit mask for CMU_REGLVL

Definition at line 419 of file efr32fg1p_cmu.h.

#define _CMU_HFXOCTRL1_REGLVL_SHIFT   4

Shift value for CMU_REGLVL

Definition at line 418 of file efr32fg1p_cmu.h.

#define _CMU_HFXOCTRL1_RESETVALUE   0x00000240UL

Default value for CMU_HFXOCTRL1

Definition at line 412 of file efr32fg1p_cmu.h.

#define _CMU_HFXOCTRL1_XTIBIASEN_DEFAULT   0x00000001UL

Mode DEFAULT for CMU_HFXOCTRL1

Definition at line 425 of file efr32fg1p_cmu.h.

#define _CMU_HFXOCTRL1_XTIBIASEN_MASK   0x200UL

Bit mask for CMU_XTIBIASEN

Definition at line 424 of file efr32fg1p_cmu.h.

#define _CMU_HFXOCTRL1_XTIBIASEN_SHIFT   9

Shift value for CMU_XTIBIASEN

Definition at line 423 of file efr32fg1p_cmu.h.

#define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_HFXOCTRL

Definition at line 403 of file efr32fg1p_cmu.h.

#define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_MASK   0x10000000UL

Bit mask for CMU_AUTOSTARTEM0EM1

Definition at line 402 of file efr32fg1p_cmu.h.

Referenced by CMU_HFXOAutostartEnable().

#define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_SHIFT   28

Shift value for CMU_AUTOSTARTEM0EM1

Definition at line 401 of file efr32fg1p_cmu.h.

#define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_HFXOCTRL

Definition at line 408 of file efr32fg1p_cmu.h.

#define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_MASK   0x20000000UL

Bit mask for CMU_AUTOSTARTSELEM0EM1

Definition at line 407 of file efr32fg1p_cmu.h.

Referenced by CMU_HFXOAutostartEnable().

#define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_SHIFT   29

Shift value for CMU_AUTOSTARTSELEM0EM1

Definition at line 406 of file efr32fg1p_cmu.h.

#define _CMU_HFXOCTRL_LFTIMEOUT_0CYCLES   0x00000000UL

Mode 0CYCLES for CMU_HFXOCTRL

Definition at line 383 of file efr32fg1p_cmu.h.

#define _CMU_HFXOCTRL_LFTIMEOUT_16CYCLES   0x00000003UL

Mode 16CYCLES for CMU_HFXOCTRL

Definition at line 386 of file efr32fg1p_cmu.h.

#define _CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES   0x00000006UL

Mode 1KCYCLES for CMU_HFXOCTRL

Definition at line 389 of file efr32fg1p_cmu.h.

#define _CMU_HFXOCTRL_LFTIMEOUT_2CYCLES   0x00000001UL

Mode 2CYCLES for CMU_HFXOCTRL

Definition at line 384 of file efr32fg1p_cmu.h.

#define _CMU_HFXOCTRL_LFTIMEOUT_32CYCLES   0x00000004UL

Mode 32CYCLES for CMU_HFXOCTRL

Definition at line 387 of file efr32fg1p_cmu.h.

#define _CMU_HFXOCTRL_LFTIMEOUT_4CYCLES   0x00000002UL

Mode 4CYCLES for CMU_HFXOCTRL

Definition at line 385 of file efr32fg1p_cmu.h.

#define _CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES   0x00000007UL

Mode 4KCYCLES for CMU_HFXOCTRL

Definition at line 390 of file efr32fg1p_cmu.h.

#define _CMU_HFXOCTRL_LFTIMEOUT_64CYCLES   0x00000005UL

Mode 64CYCLES for CMU_HFXOCTRL

Definition at line 388 of file efr32fg1p_cmu.h.

#define _CMU_HFXOCTRL_LFTIMEOUT_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_HFXOCTRL

Definition at line 382 of file efr32fg1p_cmu.h.

#define _CMU_HFXOCTRL_LFTIMEOUT_MASK   0x7000000UL

Bit mask for CMU_LFTIMEOUT

Definition at line 381 of file efr32fg1p_cmu.h.

#define _CMU_HFXOCTRL_LFTIMEOUT_SHIFT   24

Shift value for CMU_LFTIMEOUT

Definition at line 380 of file efr32fg1p_cmu.h.

#define _CMU_HFXOCTRL_LOWPOWER_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_HFXOCTRL

Definition at line 368 of file efr32fg1p_cmu.h.

#define _CMU_HFXOCTRL_LOWPOWER_MASK   0x100UL

Bit mask for CMU_LOWPOWER

Definition at line 367 of file efr32fg1p_cmu.h.

#define _CMU_HFXOCTRL_LOWPOWER_SHIFT   8

Shift value for CMU_LOWPOWER

Definition at line 366 of file efr32fg1p_cmu.h.

Referenced by CMU_HFXOInit().

#define _CMU_HFXOCTRL_MASK   0x37000731UL

Mask for CMU_HFXOCTRL

Definition at line 345 of file efr32fg1p_cmu.h.

#define _CMU_HFXOCTRL_MODE_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_HFXOCTRL

Definition at line 349 of file efr32fg1p_cmu.h.

#define _CMU_HFXOCTRL_MODE_EXTCLK   0x00000001UL

Mode EXTCLK for CMU_HFXOCTRL

Definition at line 351 of file efr32fg1p_cmu.h.

#define _CMU_HFXOCTRL_MODE_MASK   0x1UL

Bit mask for CMU_MODE

Definition at line 348 of file efr32fg1p_cmu.h.

Referenced by CMU_HFXOInit(), and CMU_OscillatorEnable().

#define _CMU_HFXOCTRL_MODE_SHIFT   0

Shift value for CMU_MODE

Definition at line 347 of file efr32fg1p_cmu.h.

#define _CMU_HFXOCTRL_MODE_XTAL   0x00000000UL

Mode XTAL for CMU_HFXOCTRL

Definition at line 350 of file efr32fg1p_cmu.h.

#define _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_AUTOCMD   0x00000000UL

Mode AUTOCMD for CMU_HFXOCTRL

Definition at line 358 of file efr32fg1p_cmu.h.

#define _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_CMD   0x00000001UL

Mode CMD for CMU_HFXOCTRL

Definition at line 359 of file efr32fg1p_cmu.h.

#define _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_HFXOCTRL

Definition at line 357 of file efr32fg1p_cmu.h.

#define _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MANUAL   0x00000002UL

Mode MANUAL for CMU_HFXOCTRL

Definition at line 360 of file efr32fg1p_cmu.h.

#define _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK   0x30UL

Bit mask for CMU_PEAKDETSHUNTOPTMODE

Definition at line 356 of file efr32fg1p_cmu.h.

Referenced by CMU_OscillatorTuningSet().

#define _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_SHIFT   4

Shift value for CMU_PEAKDETSHUNTOPTMODE

Definition at line 355 of file efr32fg1p_cmu.h.

#define _CMU_HFXOCTRL_RESETVALUE   0x00000000UL

Default value for CMU_HFXOCTRL

Definition at line 344 of file efr32fg1p_cmu.h.

#define _CMU_HFXOCTRL_XTI2GND_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_HFXOCTRL

Definition at line 373 of file efr32fg1p_cmu.h.

#define _CMU_HFXOCTRL_XTI2GND_MASK   0x200UL

Bit mask for CMU_XTI2GND

Definition at line 372 of file efr32fg1p_cmu.h.

#define _CMU_HFXOCTRL_XTI2GND_SHIFT   9

Shift value for CMU_XTI2GND

Definition at line 371 of file efr32fg1p_cmu.h.

#define _CMU_HFXOCTRL_XTO2GND_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_HFXOCTRL

Definition at line 378 of file efr32fg1p_cmu.h.

#define _CMU_HFXOCTRL_XTO2GND_MASK   0x400UL

Bit mask for CMU_XTO2GND

Definition at line 377 of file efr32fg1p_cmu.h.

#define _CMU_HFXOCTRL_XTO2GND_SHIFT   10

Shift value for CMU_XTO2GND

Definition at line 376 of file efr32fg1p_cmu.h.

#define _CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT   0x000000A0UL

Mode DEFAULT for CMU_HFXOSTARTUPCTRL

Definition at line 437 of file efr32fg1p_cmu.h.

#define _CMU_HFXOSTARTUPCTRL_CTUNE_MASK   0xFF800UL

Bit mask for CMU_CTUNE

Definition at line 436 of file efr32fg1p_cmu.h.

#define _CMU_HFXOSTARTUPCTRL_CTUNE_SHIFT   11

Shift value for CMU_CTUNE

Definition at line 435 of file efr32fg1p_cmu.h.

Referenced by CMU_HFXOInit().

#define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT   0x00000060UL

Mode DEFAULT for CMU_HFXOSTARTUPCTRL

Definition at line 433 of file efr32fg1p_cmu.h.

#define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_MASK   0x7FUL

Bit mask for CMU_IBTRIMXOCORE

Definition at line 432 of file efr32fg1p_cmu.h.

Referenced by CHIP_Init().

#define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_SHIFT   0

Shift value for CMU_IBTRIMXOCORE

Definition at line 431 of file efr32fg1p_cmu.h.

Referenced by CHIP_Init(), and CMU_HFXOInit().

#define _CMU_HFXOSTARTUPCTRL_MASK   0xFFEFF87FUL

Mask for CMU_HFXOSTARTUPCTRL

Definition at line 430 of file efr32fg1p_cmu.h.

#define _CMU_HFXOSTARTUPCTRL_RESERVED0_DEFAULT   0x00000009UL

Mode DEFAULT for CMU_HFXOSTARTUPCTRL

Definition at line 441 of file efr32fg1p_cmu.h.

#define _CMU_HFXOSTARTUPCTRL_RESERVED0_MASK   0xFE00000UL

Bit mask for CMU_RESERVED0

Definition at line 440 of file efr32fg1p_cmu.h.

#define _CMU_HFXOSTARTUPCTRL_RESERVED0_SHIFT   21

Shift value for CMU_RESERVED0

Definition at line 439 of file efr32fg1p_cmu.h.

#define _CMU_HFXOSTARTUPCTRL_RESERVED1_DEFAULT   0x0000000AUL

Mode DEFAULT for CMU_HFXOSTARTUPCTRL

Definition at line 445 of file efr32fg1p_cmu.h.

#define _CMU_HFXOSTARTUPCTRL_RESERVED1_MASK   0xF0000000UL

Bit mask for CMU_RESERVED1

Definition at line 444 of file efr32fg1p_cmu.h.

#define _CMU_HFXOSTARTUPCTRL_RESERVED1_SHIFT   28

Shift value for CMU_RESERVED1

Definition at line 443 of file efr32fg1p_cmu.h.

#define _CMU_HFXOSTARTUPCTRL_RESETVALUE   0xA1250060UL

Default value for CMU_HFXOSTARTUPCTRL

Definition at line 429 of file efr32fg1p_cmu.h.

#define _CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT   0x00000155UL

Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL

Definition at line 461 of file efr32fg1p_cmu.h.

#define _CMU_HFXOSTEADYSTATECTRL_CTUNE_MASK   0xFF800UL

Bit mask for CMU_CTUNE

Definition at line 460 of file efr32fg1p_cmu.h.

Referenced by CMU_HFXOInit().

#define _CMU_HFXOSTEADYSTATECTRL_CTUNE_SHIFT   11

Shift value for CMU_CTUNE

Definition at line 459 of file efr32fg1p_cmu.h.

Referenced by CMU_HFXOInit().

#define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT   0x00000009UL

Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL

Definition at line 453 of file efr32fg1p_cmu.h.

#define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_MASK   0x7FUL

Bit mask for CMU_IBTRIMXOCORE

Definition at line 452 of file efr32fg1p_cmu.h.

Referenced by CMU_HFXOInit(), and CMU_OscillatorTuningSet().

#define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_SHIFT   0

Shift value for CMU_IBTRIMXOCORE

Definition at line 451 of file efr32fg1p_cmu.h.

Referenced by CMU_HFXOInit().

#define _CMU_HFXOSTEADYSTATECTRL_MASK   0xF70FFFFFUL

Mask for CMU_HFXOSTEADYSTATECTRL

Definition at line 450 of file efr32fg1p_cmu.h.

#define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL

Definition at line 470 of file efr32fg1p_cmu.h.

#define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_MASK   0x4000000UL

Bit mask for CMU_PEAKDETEN

Definition at line 469 of file efr32fg1p_cmu.h.

#define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_SHIFT   26

Shift value for CMU_PEAKDETEN

Definition at line 468 of file efr32fg1p_cmu.h.

#define _CMU_HFXOSTEADYSTATECTRL_REGISH_DEFAULT   0x0000000AUL

Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL

Definition at line 457 of file efr32fg1p_cmu.h.

#define _CMU_HFXOSTEADYSTATECTRL_REGISH_MASK   0x780UL

Bit mask for CMU_REGISH

Definition at line 456 of file efr32fg1p_cmu.h.

Referenced by CMU_HFXOInit(), and CMU_OscillatorTuningSet().

#define _CMU_HFXOSTEADYSTATECTRL_REGISH_SHIFT   7

Shift value for CMU_REGISH

Definition at line 455 of file efr32fg1p_cmu.h.

Referenced by CMU_HFXOInit(), and CMU_OscillatorTuningSet().

#define _CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_DEFAULT   0x0000000AUL

Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL

Definition at line 474 of file efr32fg1p_cmu.h.

#define _CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_MASK   0xF0000000UL

Bit mask for CMU_REGISHUPPER

Definition at line 473 of file efr32fg1p_cmu.h.

Referenced by CMU_HFXOInit(), and CMU_OscillatorTuningSet().

#define _CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_SHIFT   28

Shift value for CMU_REGISHUPPER

Definition at line 472 of file efr32fg1p_cmu.h.

#define _CMU_HFXOSTEADYSTATECTRL_REGSELILOW_DEFAULT   0x00000003UL

Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL

Definition at line 465 of file efr32fg1p_cmu.h.

#define _CMU_HFXOSTEADYSTATECTRL_REGSELILOW_MASK   0x3000000UL

Bit mask for CMU_REGSELILOW

Definition at line 464 of file efr32fg1p_cmu.h.

#define _CMU_HFXOSTEADYSTATECTRL_REGSELILOW_SHIFT   24

Shift value for CMU_REGSELILOW

Definition at line 463 of file efr32fg1p_cmu.h.

#define _CMU_HFXOSTEADYSTATECTRL_RESETVALUE   0xA30AAD09UL

Default value for CMU_HFXOSTEADYSTATECTRL

Definition at line 449 of file efr32fg1p_cmu.h.

#define _CMU_HFXOTIMEOUTCTRL_MASK   0x000FFFFFUL

Mask for CMU_HFXOTIMEOUTCTRL

Definition at line 479 of file efr32fg1p_cmu.h.

#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES   0x00000002UL

Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL

Definition at line 540 of file efr32fg1p_cmu.h.

#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES   0x00000009UL

Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL

Definition at line 548 of file efr32fg1p_cmu.h.

#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES   0x00000005UL

Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL

Definition at line 543 of file efr32fg1p_cmu.h.

#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES   0x00000004UL

Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL

Definition at line 542 of file efr32fg1p_cmu.h.

#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES   0x00000000UL

Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL

Definition at line 538 of file efr32fg1p_cmu.h.

#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES   0x00000006UL

Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL

Definition at line 545 of file efr32fg1p_cmu.h.

#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES   0x00000003UL

Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL

Definition at line 541 of file efr32fg1p_cmu.h.

#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES   0x0000000AUL

Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL

Definition at line 549 of file efr32fg1p_cmu.h.

#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES   0x00000001UL

Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL

Definition at line 539 of file efr32fg1p_cmu.h.

#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES   0x00000007UL

Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL

Definition at line 546 of file efr32fg1p_cmu.h.

#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES   0x00000008UL

Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL

Definition at line 547 of file efr32fg1p_cmu.h.

#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT   0x00000006UL

Mode DEFAULT for CMU_HFXOTIMEOUTCTRL

Definition at line 544 of file efr32fg1p_cmu.h.

#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_MASK   0xF000UL

Bit mask for CMU_PEAKDETTIMEOUT

Definition at line 537 of file efr32fg1p_cmu.h.

#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_SHIFT   12

Shift value for CMU_PEAKDETTIMEOUT

Definition at line 536 of file efr32fg1p_cmu.h.

Referenced by CMU_HFXOInit().

#define _CMU_HFXOTIMEOUTCTRL_RESERVED2_DEFAULT   0x00000006UL

Mode DEFAULT for CMU_HFXOTIMEOUTCTRL

Definition at line 534 of file efr32fg1p_cmu.h.

#define _CMU_HFXOTIMEOUTCTRL_RESERVED2_MASK   0xF00UL

Bit mask for CMU_RESERVED2

Definition at line 533 of file efr32fg1p_cmu.h.

#define _CMU_HFXOTIMEOUTCTRL_RESERVED2_SHIFT   8

Shift value for CMU_RESERVED2

Definition at line 532 of file efr32fg1p_cmu.h.

#define _CMU_HFXOTIMEOUTCTRL_RESETVALUE   0x00026667UL

Default value for CMU_HFXOTIMEOUTCTRL

Definition at line 478 of file efr32fg1p_cmu.h.

#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_16CYCLES   0x00000002UL

Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL

Definition at line 567 of file efr32fg1p_cmu.h.

#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_16KCYCLES   0x00000009UL

Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL

Definition at line 574 of file efr32fg1p_cmu.h.

#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_1KCYCLES   0x00000005UL

Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL

Definition at line 570 of file efr32fg1p_cmu.h.

#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_256CYCLES   0x00000004UL

Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL

Definition at line 569 of file efr32fg1p_cmu.h.

#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_2CYCLES   0x00000000UL

Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL

Definition at line 564 of file efr32fg1p_cmu.h.

#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_2KCYCLES   0x00000006UL

Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL

Definition at line 571 of file efr32fg1p_cmu.h.

#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_32CYCLES   0x00000003UL

Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL

Definition at line 568 of file efr32fg1p_cmu.h.

#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_32KCYCLES   0x0000000AUL

Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL

Definition at line 575 of file efr32fg1p_cmu.h.

#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_4CYCLES   0x00000001UL

Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL

Definition at line 565 of file efr32fg1p_cmu.h.

#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_4KCYCLES   0x00000007UL

Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL

Definition at line 572 of file efr32fg1p_cmu.h.

#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_8KCYCLES   0x00000008UL

Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL

Definition at line 573 of file efr32fg1p_cmu.h.

#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_DEFAULT   0x00000002UL

Mode DEFAULT for CMU_HFXOTIMEOUTCTRL

Definition at line 566 of file efr32fg1p_cmu.h.

#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_MASK   0xF0000UL

Bit mask for CMU_SHUNTOPTTIMEOUT

Definition at line 563 of file efr32fg1p_cmu.h.

#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_SHIFT   16

Shift value for CMU_SHUNTOPTTIMEOUT

Definition at line 562 of file efr32fg1p_cmu.h.

Referenced by CMU_HFXOInit().

#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES   0x00000002UL

Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL

Definition at line 484 of file efr32fg1p_cmu.h.

#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES   0x00000009UL

Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL

Definition at line 492 of file efr32fg1p_cmu.h.

#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES   0x00000005UL

Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL

Definition at line 487 of file efr32fg1p_cmu.h.

#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES   0x00000004UL

Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL

Definition at line 486 of file efr32fg1p_cmu.h.

#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES   0x00000000UL

Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL

Definition at line 482 of file efr32fg1p_cmu.h.

#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES   0x00000006UL

Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL

Definition at line 488 of file efr32fg1p_cmu.h.

#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES   0x00000003UL

Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL

Definition at line 485 of file efr32fg1p_cmu.h.

#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES   0x0000000AUL

Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL

Definition at line 493 of file efr32fg1p_cmu.h.

#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES   0x00000001UL

Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL

Definition at line 483 of file efr32fg1p_cmu.h.

#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES   0x00000007UL

Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL

Definition at line 490 of file efr32fg1p_cmu.h.

#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES   0x00000008UL

Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL

Definition at line 491 of file efr32fg1p_cmu.h.

#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT   0x00000007UL

Mode DEFAULT for CMU_HFXOTIMEOUTCTRL

Definition at line 489 of file efr32fg1p_cmu.h.

#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_MASK   0xFUL

Bit mask for CMU_STARTUPTIMEOUT

Definition at line 481 of file efr32fg1p_cmu.h.

#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_SHIFT   0

Shift value for CMU_STARTUPTIMEOUT

Definition at line 480 of file efr32fg1p_cmu.h.

Referenced by CMU_HFXOInit().

#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES   0x00000002UL

Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL

Definition at line 510 of file efr32fg1p_cmu.h.

#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES   0x00000009UL

Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL

Definition at line 518 of file efr32fg1p_cmu.h.

#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES   0x00000005UL

Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL

Definition at line 513 of file efr32fg1p_cmu.h.

#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES   0x00000004UL

Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL

Definition at line 512 of file efr32fg1p_cmu.h.

#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES   0x00000000UL

Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL

Definition at line 508 of file efr32fg1p_cmu.h.

#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES   0x00000006UL

Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL

Definition at line 515 of file efr32fg1p_cmu.h.

#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES   0x00000003UL

Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL

Definition at line 511 of file efr32fg1p_cmu.h.

#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES   0x0000000AUL

Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL

Definition at line 519 of file efr32fg1p_cmu.h.

#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES   0x00000001UL

Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL

Definition at line 509 of file efr32fg1p_cmu.h.

#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES   0x00000007UL

Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL

Definition at line 516 of file efr32fg1p_cmu.h.

#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES   0x00000008UL

Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL

Definition at line 517 of file efr32fg1p_cmu.h.

#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT   0x00000006UL

Mode DEFAULT for CMU_HFXOTIMEOUTCTRL

Definition at line 514 of file efr32fg1p_cmu.h.

#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_MASK   0xF0UL

Bit mask for CMU_STEADYTIMEOUT

Definition at line 507 of file efr32fg1p_cmu.h.

#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_SHIFT   4

Shift value for CMU_STEADYTIMEOUT

Definition at line 506 of file efr32fg1p_cmu.h.

Referenced by CMU_HFXOInit().

#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_HFXOTRIMSTATUS

Definition at line 1047 of file efr32fg1p_cmu.h.

#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_MASK   0x7FUL

Bit mask for CMU_IBTRIMXOCORE

Definition at line 1046 of file efr32fg1p_cmu.h.

Referenced by CMU_OscillatorTuningGet().

#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_SHIFT   0

Shift value for CMU_IBTRIMXOCORE

Definition at line 1045 of file efr32fg1p_cmu.h.

#define _CMU_HFXOTRIMSTATUS_MASK   0x000007FFUL

Mask for CMU_HFXOTRIMSTATUS

Definition at line 1044 of file efr32fg1p_cmu.h.

#define _CMU_HFXOTRIMSTATUS_REGISH_DEFAULT   0x0000000AUL

Mode DEFAULT for CMU_HFXOTRIMSTATUS

Definition at line 1051 of file efr32fg1p_cmu.h.

#define _CMU_HFXOTRIMSTATUS_REGISH_MASK   0x780UL

Bit mask for CMU_REGISH

Definition at line 1050 of file efr32fg1p_cmu.h.

Referenced by CMU_OscillatorTuningGet().

#define _CMU_HFXOTRIMSTATUS_REGISH_SHIFT   7

Shift value for CMU_REGISH

Definition at line 1049 of file efr32fg1p_cmu.h.

#define _CMU_HFXOTRIMSTATUS_RESETVALUE   0x00000500UL

Default value for CMU_HFXOTRIMSTATUS

Definition at line 1043 of file efr32fg1p_cmu.h.

#define _CMU_IEN_AUXHFRCORDY_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_IEN

Definition at line 1317 of file efr32fg1p_cmu.h.

#define _CMU_IEN_AUXHFRCORDY_MASK   0x10UL

Bit mask for CMU_AUXHFRCORDY

Definition at line 1316 of file efr32fg1p_cmu.h.

#define _CMU_IEN_AUXHFRCORDY_SHIFT   4

Shift value for CMU_AUXHFRCORDY

Definition at line 1315 of file efr32fg1p_cmu.h.

#define _CMU_IEN_CALOF_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_IEN

Definition at line 1327 of file efr32fg1p_cmu.h.

#define _CMU_IEN_CALOF_MASK   0x40UL

Bit mask for CMU_CALOF

Definition at line 1326 of file efr32fg1p_cmu.h.

#define _CMU_IEN_CALOF_SHIFT   6

Shift value for CMU_CALOF

Definition at line 1325 of file efr32fg1p_cmu.h.

#define _CMU_IEN_CALRDY_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_IEN

Definition at line 1322 of file efr32fg1p_cmu.h.

#define _CMU_IEN_CALRDY_MASK   0x20UL

Bit mask for CMU_CALRDY

Definition at line 1321 of file efr32fg1p_cmu.h.

#define _CMU_IEN_CALRDY_SHIFT   5

Shift value for CMU_CALRDY

Definition at line 1320 of file efr32fg1p_cmu.h.

#define _CMU_IEN_CMUERR_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_IEN

Definition at line 1367 of file efr32fg1p_cmu.h.

#define _CMU_IEN_CMUERR_MASK   0x80000000UL

Bit mask for CMU_CMUERR

Definition at line 1366 of file efr32fg1p_cmu.h.

#define _CMU_IEN_CMUERR_SHIFT   31

Shift value for CMU_CMUERR

Definition at line 1365 of file efr32fg1p_cmu.h.

#define _CMU_IEN_HFRCODIS_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_IEN

Definition at line 1357 of file efr32fg1p_cmu.h.

#define _CMU_IEN_HFRCODIS_MASK   0x2000UL

Bit mask for CMU_HFRCODIS

Definition at line 1356 of file efr32fg1p_cmu.h.

#define _CMU_IEN_HFRCODIS_SHIFT   13

Shift value for CMU_HFRCODIS

Definition at line 1355 of file efr32fg1p_cmu.h.

#define _CMU_IEN_HFRCORDY_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_IEN

Definition at line 1297 of file efr32fg1p_cmu.h.

#define _CMU_IEN_HFRCORDY_MASK   0x1UL

Bit mask for CMU_HFRCORDY

Definition at line 1296 of file efr32fg1p_cmu.h.

#define _CMU_IEN_HFRCORDY_SHIFT   0

Shift value for CMU_HFRCORDY

Definition at line 1295 of file efr32fg1p_cmu.h.

#define _CMU_IEN_HFXOAUTOSW_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_IEN

Definition at line 1337 of file efr32fg1p_cmu.h.

#define _CMU_IEN_HFXOAUTOSW_MASK   0x200UL

Bit mask for CMU_HFXOAUTOSW

Definition at line 1336 of file efr32fg1p_cmu.h.

#define _CMU_IEN_HFXOAUTOSW_SHIFT   9

Shift value for CMU_HFXOAUTOSW

Definition at line 1335 of file efr32fg1p_cmu.h.

#define _CMU_IEN_HFXODISERR_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_IEN

Definition at line 1332 of file efr32fg1p_cmu.h.

#define _CMU_IEN_HFXODISERR_MASK   0x100UL

Bit mask for CMU_HFXODISERR

Definition at line 1331 of file efr32fg1p_cmu.h.

#define _CMU_IEN_HFXODISERR_SHIFT   8

Shift value for CMU_HFXODISERR

Definition at line 1330 of file efr32fg1p_cmu.h.

#define _CMU_IEN_HFXOPEAKDETERR_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_IEN

Definition at line 1342 of file efr32fg1p_cmu.h.

#define _CMU_IEN_HFXOPEAKDETERR_MASK   0x400UL

Bit mask for CMU_HFXOPEAKDETERR

Definition at line 1341 of file efr32fg1p_cmu.h.

#define _CMU_IEN_HFXOPEAKDETERR_SHIFT   10

Shift value for CMU_HFXOPEAKDETERR

Definition at line 1340 of file efr32fg1p_cmu.h.

#define _CMU_IEN_HFXOPEAKDETRDY_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_IEN

Definition at line 1347 of file efr32fg1p_cmu.h.

#define _CMU_IEN_HFXOPEAKDETRDY_MASK   0x800UL

Bit mask for CMU_HFXOPEAKDETRDY

Definition at line 1346 of file efr32fg1p_cmu.h.

#define _CMU_IEN_HFXOPEAKDETRDY_SHIFT   11

Shift value for CMU_HFXOPEAKDETRDY

Definition at line 1345 of file efr32fg1p_cmu.h.

#define _CMU_IEN_HFXORDY_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_IEN

Definition at line 1302 of file efr32fg1p_cmu.h.

#define _CMU_IEN_HFXORDY_MASK   0x2UL

Bit mask for CMU_HFXORDY

Definition at line 1301 of file efr32fg1p_cmu.h.

#define _CMU_IEN_HFXORDY_SHIFT   1

Shift value for CMU_HFXORDY

Definition at line 1300 of file efr32fg1p_cmu.h.

#define _CMU_IEN_HFXOSHUNTOPTRDY_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_IEN

Definition at line 1352 of file efr32fg1p_cmu.h.

#define _CMU_IEN_HFXOSHUNTOPTRDY_MASK   0x1000UL

Bit mask for CMU_HFXOSHUNTOPTRDY

Definition at line 1351 of file efr32fg1p_cmu.h.

#define _CMU_IEN_HFXOSHUNTOPTRDY_SHIFT   12

Shift value for CMU_HFXOSHUNTOPTRDY

Definition at line 1350 of file efr32fg1p_cmu.h.

#define _CMU_IEN_LFRCORDY_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_IEN

Definition at line 1307 of file efr32fg1p_cmu.h.

#define _CMU_IEN_LFRCORDY_MASK   0x4UL

Bit mask for CMU_LFRCORDY

Definition at line 1306 of file efr32fg1p_cmu.h.

#define _CMU_IEN_LFRCORDY_SHIFT   2

Shift value for CMU_LFRCORDY

Definition at line 1305 of file efr32fg1p_cmu.h.

#define _CMU_IEN_LFTIMEOUTERR_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_IEN

Definition at line 1362 of file efr32fg1p_cmu.h.

#define _CMU_IEN_LFTIMEOUTERR_MASK   0x4000UL

Bit mask for CMU_LFTIMEOUTERR

Definition at line 1361 of file efr32fg1p_cmu.h.

#define _CMU_IEN_LFTIMEOUTERR_SHIFT   14

Shift value for CMU_LFTIMEOUTERR

Definition at line 1360 of file efr32fg1p_cmu.h.

#define _CMU_IEN_LFXORDY_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_IEN

Definition at line 1312 of file efr32fg1p_cmu.h.

#define _CMU_IEN_LFXORDY_MASK   0x8UL

Bit mask for CMU_LFXORDY

Definition at line 1311 of file efr32fg1p_cmu.h.

#define _CMU_IEN_LFXORDY_SHIFT   3

Shift value for CMU_LFXORDY

Definition at line 1310 of file efr32fg1p_cmu.h.

#define _CMU_IEN_MASK   0x80007F7FUL

Mask for CMU_IEN

Definition at line 1293 of file efr32fg1p_cmu.h.

#define _CMU_IEN_RESETVALUE   0x00000000UL

Default value for CMU_IEN

Definition at line 1292 of file efr32fg1p_cmu.h.

#define _CMU_IF_AUXHFRCORDY_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_IF

Definition at line 1080 of file efr32fg1p_cmu.h.

#define _CMU_IF_AUXHFRCORDY_MASK   0x10UL

Bit mask for CMU_AUXHFRCORDY

Definition at line 1079 of file efr32fg1p_cmu.h.

#define _CMU_IF_AUXHFRCORDY_SHIFT   4

Shift value for CMU_AUXHFRCORDY

Definition at line 1078 of file efr32fg1p_cmu.h.

#define _CMU_IF_CALOF_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_IF

Definition at line 1090 of file efr32fg1p_cmu.h.

#define _CMU_IF_CALOF_MASK   0x40UL

Bit mask for CMU_CALOF

Definition at line 1089 of file efr32fg1p_cmu.h.

#define _CMU_IF_CALOF_SHIFT   6

Shift value for CMU_CALOF

Definition at line 1088 of file efr32fg1p_cmu.h.

#define _CMU_IF_CALRDY_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_IF

Definition at line 1085 of file efr32fg1p_cmu.h.

#define _CMU_IF_CALRDY_MASK   0x20UL

Bit mask for CMU_CALRDY

Definition at line 1084 of file efr32fg1p_cmu.h.

#define _CMU_IF_CALRDY_SHIFT   5

Shift value for CMU_CALRDY

Definition at line 1083 of file efr32fg1p_cmu.h.

#define _CMU_IF_CMUERR_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_IF

Definition at line 1130 of file efr32fg1p_cmu.h.

#define _CMU_IF_CMUERR_MASK   0x80000000UL

Bit mask for CMU_CMUERR

Definition at line 1129 of file efr32fg1p_cmu.h.

#define _CMU_IF_CMUERR_SHIFT   31

Shift value for CMU_CMUERR

Definition at line 1128 of file efr32fg1p_cmu.h.

#define _CMU_IF_HFRCODIS_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_IF

Definition at line 1120 of file efr32fg1p_cmu.h.

#define _CMU_IF_HFRCODIS_MASK   0x2000UL

Bit mask for CMU_HFRCODIS

Definition at line 1119 of file efr32fg1p_cmu.h.

#define _CMU_IF_HFRCODIS_SHIFT   13

Shift value for CMU_HFRCODIS

Definition at line 1118 of file efr32fg1p_cmu.h.

#define _CMU_IF_HFRCORDY_DEFAULT   0x00000001UL

Mode DEFAULT for CMU_IF

Definition at line 1060 of file efr32fg1p_cmu.h.

#define _CMU_IF_HFRCORDY_MASK   0x1UL

Bit mask for CMU_HFRCORDY

Definition at line 1059 of file efr32fg1p_cmu.h.

#define _CMU_IF_HFRCORDY_SHIFT   0

Shift value for CMU_HFRCORDY

Definition at line 1058 of file efr32fg1p_cmu.h.

#define _CMU_IF_HFXOAUTOSW_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_IF

Definition at line 1100 of file efr32fg1p_cmu.h.

#define _CMU_IF_HFXOAUTOSW_MASK   0x200UL

Bit mask for CMU_HFXOAUTOSW

Definition at line 1099 of file efr32fg1p_cmu.h.

#define _CMU_IF_HFXOAUTOSW_SHIFT   9

Shift value for CMU_HFXOAUTOSW

Definition at line 1098 of file efr32fg1p_cmu.h.

#define _CMU_IF_HFXODISERR_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_IF

Definition at line 1095 of file efr32fg1p_cmu.h.

#define _CMU_IF_HFXODISERR_MASK   0x100UL

Bit mask for CMU_HFXODISERR

Definition at line 1094 of file efr32fg1p_cmu.h.

#define _CMU_IF_HFXODISERR_SHIFT   8

Shift value for CMU_HFXODISERR

Definition at line 1093 of file efr32fg1p_cmu.h.

#define _CMU_IF_HFXOPEAKDETERR_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_IF

Definition at line 1105 of file efr32fg1p_cmu.h.

#define _CMU_IF_HFXOPEAKDETERR_MASK   0x400UL

Bit mask for CMU_HFXOPEAKDETERR

Definition at line 1104 of file efr32fg1p_cmu.h.

#define _CMU_IF_HFXOPEAKDETERR_SHIFT   10

Shift value for CMU_HFXOPEAKDETERR

Definition at line 1103 of file efr32fg1p_cmu.h.

#define _CMU_IF_HFXOPEAKDETRDY_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_IF

Definition at line 1110 of file efr32fg1p_cmu.h.

#define _CMU_IF_HFXOPEAKDETRDY_MASK   0x800UL

Bit mask for CMU_HFXOPEAKDETRDY

Definition at line 1109 of file efr32fg1p_cmu.h.

#define _CMU_IF_HFXOPEAKDETRDY_SHIFT   11

Shift value for CMU_HFXOPEAKDETRDY

Definition at line 1108 of file efr32fg1p_cmu.h.

#define _CMU_IF_HFXORDY_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_IF

Definition at line 1065 of file efr32fg1p_cmu.h.

#define _CMU_IF_HFXORDY_MASK   0x2UL

Bit mask for CMU_HFXORDY

Definition at line 1064 of file efr32fg1p_cmu.h.

#define _CMU_IF_HFXORDY_SHIFT   1

Shift value for CMU_HFXORDY

Definition at line 1063 of file efr32fg1p_cmu.h.

#define _CMU_IF_HFXOSHUNTOPTRDY_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_IF

Definition at line 1115 of file efr32fg1p_cmu.h.

#define _CMU_IF_HFXOSHUNTOPTRDY_MASK   0x1000UL

Bit mask for CMU_HFXOSHUNTOPTRDY

Definition at line 1114 of file efr32fg1p_cmu.h.

#define _CMU_IF_HFXOSHUNTOPTRDY_SHIFT   12

Shift value for CMU_HFXOSHUNTOPTRDY

Definition at line 1113 of file efr32fg1p_cmu.h.

#define _CMU_IF_LFRCORDY_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_IF

Definition at line 1070 of file efr32fg1p_cmu.h.

#define _CMU_IF_LFRCORDY_MASK   0x4UL

Bit mask for CMU_LFRCORDY

Definition at line 1069 of file efr32fg1p_cmu.h.

#define _CMU_IF_LFRCORDY_SHIFT   2

Shift value for CMU_LFRCORDY

Definition at line 1068 of file efr32fg1p_cmu.h.

#define _CMU_IF_LFTIMEOUTERR_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_IF

Definition at line 1125 of file efr32fg1p_cmu.h.

#define _CMU_IF_LFTIMEOUTERR_MASK   0x4000UL

Bit mask for CMU_LFTIMEOUTERR

Definition at line 1124 of file efr32fg1p_cmu.h.

#define _CMU_IF_LFTIMEOUTERR_SHIFT   14

Shift value for CMU_LFTIMEOUTERR

Definition at line 1123 of file efr32fg1p_cmu.h.

#define _CMU_IF_LFXORDY_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_IF

Definition at line 1075 of file efr32fg1p_cmu.h.

#define _CMU_IF_LFXORDY_MASK   0x8UL

Bit mask for CMU_LFXORDY

Definition at line 1074 of file efr32fg1p_cmu.h.

#define _CMU_IF_LFXORDY_SHIFT   3

Shift value for CMU_LFXORDY

Definition at line 1073 of file efr32fg1p_cmu.h.

#define _CMU_IF_MASK   0x80007F7FUL

Mask for CMU_IF

Definition at line 1056 of file efr32fg1p_cmu.h.

#define _CMU_IF_RESETVALUE   0x00000001UL

Default value for CMU_IF

Definition at line 1055 of file efr32fg1p_cmu.h.

#define _CMU_IFC_AUXHFRCORDY_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_IFC

Definition at line 1238 of file efr32fg1p_cmu.h.

#define _CMU_IFC_AUXHFRCORDY_MASK   0x10UL

Bit mask for CMU_AUXHFRCORDY

Definition at line 1237 of file efr32fg1p_cmu.h.

#define _CMU_IFC_AUXHFRCORDY_SHIFT   4

Shift value for CMU_AUXHFRCORDY

Definition at line 1236 of file efr32fg1p_cmu.h.

#define _CMU_IFC_CALOF_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_IFC

Definition at line 1248 of file efr32fg1p_cmu.h.

#define _CMU_IFC_CALOF_MASK   0x40UL

Bit mask for CMU_CALOF

Definition at line 1247 of file efr32fg1p_cmu.h.

#define _CMU_IFC_CALOF_SHIFT   6

Shift value for CMU_CALOF

Definition at line 1246 of file efr32fg1p_cmu.h.

#define _CMU_IFC_CALRDY_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_IFC

Definition at line 1243 of file efr32fg1p_cmu.h.

#define _CMU_IFC_CALRDY_MASK   0x20UL

Bit mask for CMU_CALRDY

Definition at line 1242 of file efr32fg1p_cmu.h.

#define _CMU_IFC_CALRDY_SHIFT   5

Shift value for CMU_CALRDY

Definition at line 1241 of file efr32fg1p_cmu.h.

#define _CMU_IFC_CMUERR_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_IFC

Definition at line 1288 of file efr32fg1p_cmu.h.

#define _CMU_IFC_CMUERR_MASK   0x80000000UL

Bit mask for CMU_CMUERR

Definition at line 1287 of file efr32fg1p_cmu.h.

#define _CMU_IFC_CMUERR_SHIFT   31

Shift value for CMU_CMUERR

Definition at line 1286 of file efr32fg1p_cmu.h.

#define _CMU_IFC_HFRCODIS_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_IFC

Definition at line 1278 of file efr32fg1p_cmu.h.

#define _CMU_IFC_HFRCODIS_MASK   0x2000UL

Bit mask for CMU_HFRCODIS

Definition at line 1277 of file efr32fg1p_cmu.h.

#define _CMU_IFC_HFRCODIS_SHIFT   13

Shift value for CMU_HFRCODIS

Definition at line 1276 of file efr32fg1p_cmu.h.

#define _CMU_IFC_HFRCORDY_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_IFC

Definition at line 1218 of file efr32fg1p_cmu.h.

#define _CMU_IFC_HFRCORDY_MASK   0x1UL

Bit mask for CMU_HFRCORDY

Definition at line 1217 of file efr32fg1p_cmu.h.

#define _CMU_IFC_HFRCORDY_SHIFT   0

Shift value for CMU_HFRCORDY

Definition at line 1216 of file efr32fg1p_cmu.h.

#define _CMU_IFC_HFXOAUTOSW_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_IFC

Definition at line 1258 of file efr32fg1p_cmu.h.

#define _CMU_IFC_HFXOAUTOSW_MASK   0x200UL

Bit mask for CMU_HFXOAUTOSW

Definition at line 1257 of file efr32fg1p_cmu.h.

#define _CMU_IFC_HFXOAUTOSW_SHIFT   9

Shift value for CMU_HFXOAUTOSW

Definition at line 1256 of file efr32fg1p_cmu.h.

#define _CMU_IFC_HFXODISERR_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_IFC

Definition at line 1253 of file efr32fg1p_cmu.h.

#define _CMU_IFC_HFXODISERR_MASK   0x100UL

Bit mask for CMU_HFXODISERR

Definition at line 1252 of file efr32fg1p_cmu.h.

#define _CMU_IFC_HFXODISERR_SHIFT   8

Shift value for CMU_HFXODISERR

Definition at line 1251 of file efr32fg1p_cmu.h.

#define _CMU_IFC_HFXOPEAKDETERR_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_IFC

Definition at line 1263 of file efr32fg1p_cmu.h.

#define _CMU_IFC_HFXOPEAKDETERR_MASK   0x400UL

Bit mask for CMU_HFXOPEAKDETERR

Definition at line 1262 of file efr32fg1p_cmu.h.

#define _CMU_IFC_HFXOPEAKDETERR_SHIFT   10

Shift value for CMU_HFXOPEAKDETERR

Definition at line 1261 of file efr32fg1p_cmu.h.

#define _CMU_IFC_HFXOPEAKDETRDY_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_IFC

Definition at line 1268 of file efr32fg1p_cmu.h.

#define _CMU_IFC_HFXOPEAKDETRDY_MASK   0x800UL

Bit mask for CMU_HFXOPEAKDETRDY

Definition at line 1267 of file efr32fg1p_cmu.h.

#define _CMU_IFC_HFXOPEAKDETRDY_SHIFT   11

Shift value for CMU_HFXOPEAKDETRDY

Definition at line 1266 of file efr32fg1p_cmu.h.

#define _CMU_IFC_HFXORDY_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_IFC

Definition at line 1223 of file efr32fg1p_cmu.h.

#define _CMU_IFC_HFXORDY_MASK   0x2UL

Bit mask for CMU_HFXORDY

Definition at line 1222 of file efr32fg1p_cmu.h.

#define _CMU_IFC_HFXORDY_SHIFT   1

Shift value for CMU_HFXORDY

Definition at line 1221 of file efr32fg1p_cmu.h.

#define _CMU_IFC_HFXOSHUNTOPTRDY_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_IFC

Definition at line 1273 of file efr32fg1p_cmu.h.

#define _CMU_IFC_HFXOSHUNTOPTRDY_MASK   0x1000UL

Bit mask for CMU_HFXOSHUNTOPTRDY

Definition at line 1272 of file efr32fg1p_cmu.h.

#define _CMU_IFC_HFXOSHUNTOPTRDY_SHIFT   12

Shift value for CMU_HFXOSHUNTOPTRDY

Definition at line 1271 of file efr32fg1p_cmu.h.

#define _CMU_IFC_LFRCORDY_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_IFC

Definition at line 1228 of file efr32fg1p_cmu.h.

#define _CMU_IFC_LFRCORDY_MASK   0x4UL

Bit mask for CMU_LFRCORDY

Definition at line 1227 of file efr32fg1p_cmu.h.

#define _CMU_IFC_LFRCORDY_SHIFT   2

Shift value for CMU_LFRCORDY

Definition at line 1226 of file efr32fg1p_cmu.h.

#define _CMU_IFC_LFTIMEOUTERR_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_IFC

Definition at line 1283 of file efr32fg1p_cmu.h.

#define _CMU_IFC_LFTIMEOUTERR_MASK   0x4000UL

Bit mask for CMU_LFTIMEOUTERR

Definition at line 1282 of file efr32fg1p_cmu.h.

#define _CMU_IFC_LFTIMEOUTERR_SHIFT   14

Shift value for CMU_LFTIMEOUTERR

Definition at line 1281 of file efr32fg1p_cmu.h.

#define _CMU_IFC_LFXORDY_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_IFC

Definition at line 1233 of file efr32fg1p_cmu.h.

#define _CMU_IFC_LFXORDY_MASK   0x8UL

Bit mask for CMU_LFXORDY

Definition at line 1232 of file efr32fg1p_cmu.h.

#define _CMU_IFC_LFXORDY_SHIFT   3

Shift value for CMU_LFXORDY

Definition at line 1231 of file efr32fg1p_cmu.h.

#define _CMU_IFC_MASK   0x80007F7FUL

Mask for CMU_IFC

Definition at line 1214 of file efr32fg1p_cmu.h.

#define _CMU_IFC_RESETVALUE   0x00000000UL

Default value for CMU_IFC

Definition at line 1213 of file efr32fg1p_cmu.h.

#define _CMU_IFS_AUXHFRCORDY_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_IFS

Definition at line 1159 of file efr32fg1p_cmu.h.

#define _CMU_IFS_AUXHFRCORDY_MASK   0x10UL

Bit mask for CMU_AUXHFRCORDY

Definition at line 1158 of file efr32fg1p_cmu.h.

#define _CMU_IFS_AUXHFRCORDY_SHIFT   4

Shift value for CMU_AUXHFRCORDY

Definition at line 1157 of file efr32fg1p_cmu.h.

#define _CMU_IFS_CALOF_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_IFS

Definition at line 1169 of file efr32fg1p_cmu.h.

#define _CMU_IFS_CALOF_MASK   0x40UL

Bit mask for CMU_CALOF

Definition at line 1168 of file efr32fg1p_cmu.h.

#define _CMU_IFS_CALOF_SHIFT   6

Shift value for CMU_CALOF

Definition at line 1167 of file efr32fg1p_cmu.h.

#define _CMU_IFS_CALRDY_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_IFS

Definition at line 1164 of file efr32fg1p_cmu.h.

#define _CMU_IFS_CALRDY_MASK   0x20UL

Bit mask for CMU_CALRDY

Definition at line 1163 of file efr32fg1p_cmu.h.

#define _CMU_IFS_CALRDY_SHIFT   5

Shift value for CMU_CALRDY

Definition at line 1162 of file efr32fg1p_cmu.h.

#define _CMU_IFS_CMUERR_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_IFS

Definition at line 1209 of file efr32fg1p_cmu.h.

#define _CMU_IFS_CMUERR_MASK   0x80000000UL

Bit mask for CMU_CMUERR

Definition at line 1208 of file efr32fg1p_cmu.h.

#define _CMU_IFS_CMUERR_SHIFT   31

Shift value for CMU_CMUERR

Definition at line 1207 of file efr32fg1p_cmu.h.

#define _CMU_IFS_HFRCODIS_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_IFS

Definition at line 1199 of file efr32fg1p_cmu.h.

#define _CMU_IFS_HFRCODIS_MASK   0x2000UL

Bit mask for CMU_HFRCODIS

Definition at line 1198 of file efr32fg1p_cmu.h.

#define _CMU_IFS_HFRCODIS_SHIFT   13

Shift value for CMU_HFRCODIS

Definition at line 1197 of file efr32fg1p_cmu.h.

#define _CMU_IFS_HFRCORDY_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_IFS

Definition at line 1139 of file efr32fg1p_cmu.h.

#define _CMU_IFS_HFRCORDY_MASK   0x1UL

Bit mask for CMU_HFRCORDY

Definition at line 1138 of file efr32fg1p_cmu.h.

#define _CMU_IFS_HFRCORDY_SHIFT   0

Shift value for CMU_HFRCORDY

Definition at line 1137 of file efr32fg1p_cmu.h.

#define _CMU_IFS_HFXOAUTOSW_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_IFS

Definition at line 1179 of file efr32fg1p_cmu.h.

#define _CMU_IFS_HFXOAUTOSW_MASK   0x200UL

Bit mask for CMU_HFXOAUTOSW

Definition at line 1178 of file efr32fg1p_cmu.h.

#define _CMU_IFS_HFXOAUTOSW_SHIFT   9

Shift value for CMU_HFXOAUTOSW

Definition at line 1177 of file efr32fg1p_cmu.h.

#define _CMU_IFS_HFXODISERR_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_IFS

Definition at line 1174 of file efr32fg1p_cmu.h.

#define _CMU_IFS_HFXODISERR_MASK   0x100UL

Bit mask for CMU_HFXODISERR

Definition at line 1173 of file efr32fg1p_cmu.h.

#define _CMU_IFS_HFXODISERR_SHIFT   8

Shift value for CMU_HFXODISERR

Definition at line 1172 of file efr32fg1p_cmu.h.

#define _CMU_IFS_HFXOPEAKDETERR_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_IFS

Definition at line 1184 of file efr32fg1p_cmu.h.

#define _CMU_IFS_HFXOPEAKDETERR_MASK   0x400UL

Bit mask for CMU_HFXOPEAKDETERR

Definition at line 1183 of file efr32fg1p_cmu.h.

#define _CMU_IFS_HFXOPEAKDETERR_SHIFT   10

Shift value for CMU_HFXOPEAKDETERR

Definition at line 1182 of file efr32fg1p_cmu.h.

#define _CMU_IFS_HFXOPEAKDETRDY_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_IFS

Definition at line 1189 of file efr32fg1p_cmu.h.

#define _CMU_IFS_HFXOPEAKDETRDY_MASK   0x800UL

Bit mask for CMU_HFXOPEAKDETRDY

Definition at line 1188 of file efr32fg1p_cmu.h.

#define _CMU_IFS_HFXOPEAKDETRDY_SHIFT   11

Shift value for CMU_HFXOPEAKDETRDY

Definition at line 1187 of file efr32fg1p_cmu.h.

#define _CMU_IFS_HFXORDY_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_IFS

Definition at line 1144 of file efr32fg1p_cmu.h.

#define _CMU_IFS_HFXORDY_MASK   0x2UL

Bit mask for CMU_HFXORDY

Definition at line 1143 of file efr32fg1p_cmu.h.

#define _CMU_IFS_HFXORDY_SHIFT   1

Shift value for CMU_HFXORDY

Definition at line 1142 of file efr32fg1p_cmu.h.

#define _CMU_IFS_HFXOSHUNTOPTRDY_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_IFS

Definition at line 1194 of file efr32fg1p_cmu.h.

#define _CMU_IFS_HFXOSHUNTOPTRDY_MASK   0x1000UL

Bit mask for CMU_HFXOSHUNTOPTRDY

Definition at line 1193 of file efr32fg1p_cmu.h.

#define _CMU_IFS_HFXOSHUNTOPTRDY_SHIFT   12

Shift value for CMU_HFXOSHUNTOPTRDY

Definition at line 1192 of file efr32fg1p_cmu.h.

#define _CMU_IFS_LFRCORDY_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_IFS

Definition at line 1149 of file efr32fg1p_cmu.h.

#define _CMU_IFS_LFRCORDY_MASK   0x4UL

Bit mask for CMU_LFRCORDY

Definition at line 1148 of file efr32fg1p_cmu.h.

#define _CMU_IFS_LFRCORDY_SHIFT   2

Shift value for CMU_LFRCORDY

Definition at line 1147 of file efr32fg1p_cmu.h.

#define _CMU_IFS_LFTIMEOUTERR_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_IFS

Definition at line 1204 of file efr32fg1p_cmu.h.

#define _CMU_IFS_LFTIMEOUTERR_MASK   0x4000UL

Bit mask for CMU_LFTIMEOUTERR

Definition at line 1203 of file efr32fg1p_cmu.h.

#define _CMU_IFS_LFTIMEOUTERR_SHIFT   14

Shift value for CMU_LFTIMEOUTERR

Definition at line 1202 of file efr32fg1p_cmu.h.

#define _CMU_IFS_LFXORDY_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_IFS

Definition at line 1154 of file efr32fg1p_cmu.h.

#define _CMU_IFS_LFXORDY_MASK   0x8UL

Bit mask for CMU_LFXORDY

Definition at line 1153 of file efr32fg1p_cmu.h.

#define _CMU_IFS_LFXORDY_SHIFT   3

Shift value for CMU_LFXORDY

Definition at line 1152 of file efr32fg1p_cmu.h.

#define _CMU_IFS_MASK   0x80007F7FUL

Mask for CMU_IFS

Definition at line 1135 of file efr32fg1p_cmu.h.

#define _CMU_IFS_RESETVALUE   0x00000000UL

Default value for CMU_IFS

Definition at line 1134 of file efr32fg1p_cmu.h.

#define _CMU_LFACLKEN0_LETIMER0_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_LFACLKEN0

Definition at line 1464 of file efr32fg1p_cmu.h.

#define _CMU_LFACLKEN0_LETIMER0_MASK   0x1UL

Bit mask for CMU_LETIMER0

Definition at line 1463 of file efr32fg1p_cmu.h.

#define _CMU_LFACLKEN0_LETIMER0_SHIFT   0

Shift value for CMU_LETIMER0

Definition at line 1462 of file efr32fg1p_cmu.h.

#define _CMU_LFACLKEN0_MASK   0x00000001UL

Mask for CMU_LFACLKEN0

Definition at line 1460 of file efr32fg1p_cmu.h.

#define _CMU_LFACLKEN0_RESETVALUE   0x00000000UL

Default value for CMU_LFACLKEN0

Definition at line 1459 of file efr32fg1p_cmu.h.

#define _CMU_LFACLKSEL_LFA_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_LFACLKSEL

Definition at line 892 of file efr32fg1p_cmu.h.

#define _CMU_LFACLKSEL_LFA_DISABLED   0x00000000UL

Mode DISABLED for CMU_LFACLKSEL

Definition at line 893 of file efr32fg1p_cmu.h.

Referenced by CMU_ClockSelectSet().

#define _CMU_LFACLKSEL_LFA_LFRCO   0x00000001UL

Mode LFRCO for CMU_LFACLKSEL

Definition at line 894 of file efr32fg1p_cmu.h.

Referenced by CMU_ClockSelectSet().

#define _CMU_LFACLKSEL_LFA_LFXO   0x00000002UL

Mode LFXO for CMU_LFACLKSEL

Definition at line 895 of file efr32fg1p_cmu.h.

Referenced by CMU_ClockSelectSet().

#define _CMU_LFACLKSEL_LFA_MASK   0x7UL

Bit mask for CMU_LFA

Definition at line 891 of file efr32fg1p_cmu.h.

Referenced by CMU_ClockSelectGet().

#define _CMU_LFACLKSEL_LFA_SHIFT   0

Shift value for CMU_LFA

Definition at line 890 of file efr32fg1p_cmu.h.

#define _CMU_LFACLKSEL_LFA_ULFRCO   0x00000004UL

Mode ULFRCO for CMU_LFACLKSEL

Definition at line 896 of file efr32fg1p_cmu.h.

Referenced by CMU_ClockSelectSet().

#define _CMU_LFACLKSEL_MASK   0x00000007UL

Mask for CMU_LFACLKSEL

Definition at line 889 of file efr32fg1p_cmu.h.

#define _CMU_LFACLKSEL_RESETVALUE   0x00000000UL

Default value for CMU_LFACLKSEL

Definition at line 888 of file efr32fg1p_cmu.h.

#define _CMU_LFAPRESC0_LETIMER0_DIV1   0x00000000UL

Mode DIV1 for CMU_LFAPRESC0

Definition at line 1538 of file efr32fg1p_cmu.h.

#define _CMU_LFAPRESC0_LETIMER0_DIV1024   0x0000000AUL

Mode DIV1024 for CMU_LFAPRESC0

Definition at line 1548 of file efr32fg1p_cmu.h.

#define _CMU_LFAPRESC0_LETIMER0_DIV128   0x00000007UL

Mode DIV128 for CMU_LFAPRESC0

Definition at line 1545 of file efr32fg1p_cmu.h.

#define _CMU_LFAPRESC0_LETIMER0_DIV16   0x00000004UL

Mode DIV16 for CMU_LFAPRESC0

Definition at line 1542 of file efr32fg1p_cmu.h.

#define _CMU_LFAPRESC0_LETIMER0_DIV16384   0x0000000EUL

Mode DIV16384 for CMU_LFAPRESC0

Definition at line 1552 of file efr32fg1p_cmu.h.

#define _CMU_LFAPRESC0_LETIMER0_DIV2   0x00000001UL

Mode DIV2 for CMU_LFAPRESC0

Definition at line 1539 of file efr32fg1p_cmu.h.

#define _CMU_LFAPRESC0_LETIMER0_DIV2048   0x0000000BUL

Mode DIV2048 for CMU_LFAPRESC0

Definition at line 1549 of file efr32fg1p_cmu.h.

#define _CMU_LFAPRESC0_LETIMER0_DIV256   0x00000008UL

Mode DIV256 for CMU_LFAPRESC0

Definition at line 1546 of file efr32fg1p_cmu.h.

#define _CMU_LFAPRESC0_LETIMER0_DIV32   0x00000005UL

Mode DIV32 for CMU_LFAPRESC0

Definition at line 1543 of file efr32fg1p_cmu.h.

#define _CMU_LFAPRESC0_LETIMER0_DIV32768   0x0000000FUL

Mode DIV32768 for CMU_LFAPRESC0

Definition at line 1553 of file efr32fg1p_cmu.h.

#define _CMU_LFAPRESC0_LETIMER0_DIV4   0x00000002UL

Mode DIV4 for CMU_LFAPRESC0

Definition at line 1540 of file efr32fg1p_cmu.h.

#define _CMU_LFAPRESC0_LETIMER0_DIV4096   0x0000000CUL

Mode DIV4096 for CMU_LFAPRESC0

Definition at line 1550 of file efr32fg1p_cmu.h.

#define _CMU_LFAPRESC0_LETIMER0_DIV512   0x00000009UL

Mode DIV512 for CMU_LFAPRESC0

Definition at line 1547 of file efr32fg1p_cmu.h.

#define _CMU_LFAPRESC0_LETIMER0_DIV64   0x00000006UL

Mode DIV64 for CMU_LFAPRESC0

Definition at line 1544 of file efr32fg1p_cmu.h.

#define _CMU_LFAPRESC0_LETIMER0_DIV8   0x00000003UL

Mode DIV8 for CMU_LFAPRESC0

Definition at line 1541 of file efr32fg1p_cmu.h.

#define _CMU_LFAPRESC0_LETIMER0_DIV8192   0x0000000DUL

Mode DIV8192 for CMU_LFAPRESC0

Definition at line 1551 of file efr32fg1p_cmu.h.

#define _CMU_LFAPRESC0_LETIMER0_MASK   0xFUL

Bit mask for CMU_LETIMER0

Definition at line 1537 of file efr32fg1p_cmu.h.

Referenced by CMU_ClockDivGet(), CMU_ClockDivSet(), CMU_ClockFreqGet(), CMU_ClockPrescGet(), and CMU_ClockPrescSet().

#define _CMU_LFAPRESC0_LETIMER0_SHIFT   0

Shift value for CMU_LETIMER0

Definition at line 1536 of file efr32fg1p_cmu.h.

Referenced by CMU_ClockDivGet(), CMU_ClockDivSet(), CMU_ClockFreqGet(), CMU_ClockPrescGet(), and CMU_ClockPrescSet().

#define _CMU_LFAPRESC0_MASK   0x0000000FUL

Mask for CMU_LFAPRESC0

Definition at line 1535 of file efr32fg1p_cmu.h.

#define _CMU_LFAPRESC0_RESETVALUE   0x00000000UL

Default value for CMU_LFAPRESC0

Definition at line 1534 of file efr32fg1p_cmu.h.

#define _CMU_LFBCLKEN0_LEUART0_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_LFBCLKEN0

Definition at line 1473 of file efr32fg1p_cmu.h.

#define _CMU_LFBCLKEN0_LEUART0_MASK   0x1UL

Bit mask for CMU_LEUART0

Definition at line 1472 of file efr32fg1p_cmu.h.

#define _CMU_LFBCLKEN0_LEUART0_SHIFT   0

Shift value for CMU_LEUART0

Definition at line 1471 of file efr32fg1p_cmu.h.

#define _CMU_LFBCLKEN0_MASK   0x00000001UL

Mask for CMU_LFBCLKEN0

Definition at line 1469 of file efr32fg1p_cmu.h.

#define _CMU_LFBCLKEN0_RESETVALUE   0x00000000UL

Default value for CMU_LFBCLKEN0

Definition at line 1468 of file efr32fg1p_cmu.h.

#define _CMU_LFBCLKSEL_LFB_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_LFBCLKSEL

Definition at line 908 of file efr32fg1p_cmu.h.

#define _CMU_LFBCLKSEL_LFB_DISABLED   0x00000000UL

Mode DISABLED for CMU_LFBCLKSEL

Definition at line 909 of file efr32fg1p_cmu.h.

#define _CMU_LFBCLKSEL_LFB_HFCLKLE   0x00000003UL

Mode HFCLKLE for CMU_LFBCLKSEL

Definition at line 912 of file efr32fg1p_cmu.h.

Referenced by CMU_ClockSelectSet().

#define _CMU_LFBCLKSEL_LFB_LFRCO   0x00000001UL

Mode LFRCO for CMU_LFBCLKSEL

Definition at line 910 of file efr32fg1p_cmu.h.

#define _CMU_LFBCLKSEL_LFB_LFXO   0x00000002UL

Mode LFXO for CMU_LFBCLKSEL

Definition at line 911 of file efr32fg1p_cmu.h.

#define _CMU_LFBCLKSEL_LFB_MASK   0x7UL

Bit mask for CMU_LFB

Definition at line 907 of file efr32fg1p_cmu.h.

Referenced by CMU_ClockSelectGet().

#define _CMU_LFBCLKSEL_LFB_SHIFT   0

Shift value for CMU_LFB

Definition at line 906 of file efr32fg1p_cmu.h.

#define _CMU_LFBCLKSEL_LFB_ULFRCO   0x00000004UL

Mode ULFRCO for CMU_LFBCLKSEL

Definition at line 913 of file efr32fg1p_cmu.h.

#define _CMU_LFBCLKSEL_MASK   0x00000007UL

Mask for CMU_LFBCLKSEL

Definition at line 905 of file efr32fg1p_cmu.h.

#define _CMU_LFBCLKSEL_RESETVALUE   0x00000000UL

Default value for CMU_LFBCLKSEL

Definition at line 904 of file efr32fg1p_cmu.h.

#define _CMU_LFBPRESC0_LEUART0_DIV1   0x00000000UL

Mode DIV1 for CMU_LFBPRESC0

Definition at line 1576 of file efr32fg1p_cmu.h.

#define _CMU_LFBPRESC0_LEUART0_DIV2   0x00000001UL

Mode DIV2 for CMU_LFBPRESC0

Definition at line 1577 of file efr32fg1p_cmu.h.

#define _CMU_LFBPRESC0_LEUART0_DIV4   0x00000002UL

Mode DIV4 for CMU_LFBPRESC0

Definition at line 1578 of file efr32fg1p_cmu.h.

#define _CMU_LFBPRESC0_LEUART0_DIV8   0x00000003UL

Mode DIV8 for CMU_LFBPRESC0

Definition at line 1579 of file efr32fg1p_cmu.h.

#define _CMU_LFBPRESC0_LEUART0_MASK   0x3UL

Bit mask for CMU_LEUART0

Definition at line 1575 of file efr32fg1p_cmu.h.

Referenced by CMU_ClockDivGet(), CMU_ClockDivSet(), CMU_ClockFreqGet(), CMU_ClockPrescGet(), CMU_ClockPrescSet(), and UARTDRV_InitLeuart().

#define _CMU_LFBPRESC0_LEUART0_SHIFT   0

Shift value for CMU_LEUART0

Definition at line 1574 of file efr32fg1p_cmu.h.

Referenced by CMU_ClockDivGet(), CMU_ClockDivSet(), CMU_ClockFreqGet(), CMU_ClockPrescGet(), CMU_ClockPrescSet(), and UARTDRV_InitLeuart().

#define _CMU_LFBPRESC0_MASK   0x00000003UL

Mask for CMU_LFBPRESC0

Definition at line 1573 of file efr32fg1p_cmu.h.

#define _CMU_LFBPRESC0_RESETVALUE   0x00000000UL

Default value for CMU_LFBPRESC0

Definition at line 1572 of file efr32fg1p_cmu.h.

#define _CMU_LFECLKEN0_MASK   0x00000001UL

Mask for CMU_LFECLKEN0

Definition at line 1478 of file efr32fg1p_cmu.h.

#define _CMU_LFECLKEN0_RESETVALUE   0x00000000UL

Default value for CMU_LFECLKEN0

Definition at line 1477 of file efr32fg1p_cmu.h.

#define _CMU_LFECLKEN0_RTCC_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_LFECLKEN0

Definition at line 1482 of file efr32fg1p_cmu.h.

#define _CMU_LFECLKEN0_RTCC_MASK   0x1UL

Bit mask for CMU_RTCC

Definition at line 1481 of file efr32fg1p_cmu.h.

#define _CMU_LFECLKEN0_RTCC_SHIFT   0

Shift value for CMU_RTCC

Definition at line 1480 of file efr32fg1p_cmu.h.

#define _CMU_LFECLKSEL_LFE_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_LFECLKSEL

Definition at line 926 of file efr32fg1p_cmu.h.

#define _CMU_LFECLKSEL_LFE_DISABLED   0x00000000UL

Mode DISABLED for CMU_LFECLKSEL

Definition at line 927 of file efr32fg1p_cmu.h.

#define _CMU_LFECLKSEL_LFE_LFRCO   0x00000001UL

Mode LFRCO for CMU_LFECLKSEL

Definition at line 928 of file efr32fg1p_cmu.h.

#define _CMU_LFECLKSEL_LFE_LFXO   0x00000002UL

Mode LFXO for CMU_LFECLKSEL

Definition at line 929 of file efr32fg1p_cmu.h.

#define _CMU_LFECLKSEL_LFE_MASK   0x7UL

Bit mask for CMU_LFE

Definition at line 925 of file efr32fg1p_cmu.h.

Referenced by CMU_ClockSelectGet().

#define _CMU_LFECLKSEL_LFE_SHIFT   0

Shift value for CMU_LFE

Definition at line 924 of file efr32fg1p_cmu.h.

#define _CMU_LFECLKSEL_LFE_ULFRCO   0x00000004UL

Mode ULFRCO for CMU_LFECLKSEL

Definition at line 930 of file efr32fg1p_cmu.h.

#define _CMU_LFECLKSEL_MASK   0x00000007UL

Mask for CMU_LFECLKSEL

Definition at line 923 of file efr32fg1p_cmu.h.

#define _CMU_LFECLKSEL_RESETVALUE   0x00000000UL

Default value for CMU_LFECLKSEL

Definition at line 922 of file efr32fg1p_cmu.h.

#define _CMU_LFEPRESC0_MASK   0x0000000FUL

Mask for CMU_LFEPRESC0

Definition at line 1587 of file efr32fg1p_cmu.h.

#define _CMU_LFEPRESC0_RESETVALUE   0x00000000UL

Default value for CMU_LFEPRESC0

Definition at line 1586 of file efr32fg1p_cmu.h.

#define _CMU_LFEPRESC0_RTCC_DIV1   0x00000000UL

Mode DIV1 for CMU_LFEPRESC0

Definition at line 1590 of file efr32fg1p_cmu.h.

Referenced by CMU_ClockPrescGet().

#define _CMU_LFEPRESC0_RTCC_MASK   0xFUL

Bit mask for CMU_RTCC

Definition at line 1589 of file efr32fg1p_cmu.h.

Referenced by CMU_ClockPrescSet().

#define _CMU_LFEPRESC0_RTCC_SHIFT   0

Shift value for CMU_RTCC

Definition at line 1588 of file efr32fg1p_cmu.h.

Referenced by CMU_ClockPrescSet().

#define _CMU_LFRCOCTRL_ENCHOP_DEFAULT   0x00000001UL

Mode DEFAULT for CMU_LFRCOCTRL

Definition at line 321 of file efr32fg1p_cmu.h.

#define _CMU_LFRCOCTRL_ENCHOP_MASK   0x20000UL

Bit mask for CMU_ENCHOP

Definition at line 320 of file efr32fg1p_cmu.h.

#define _CMU_LFRCOCTRL_ENCHOP_SHIFT   17

Shift value for CMU_ENCHOP

Definition at line 319 of file efr32fg1p_cmu.h.

#define _CMU_LFRCOCTRL_ENDEM_DEFAULT   0x00000001UL

Mode DEFAULT for CMU_LFRCOCTRL

Definition at line 326 of file efr32fg1p_cmu.h.

#define _CMU_LFRCOCTRL_ENDEM_MASK   0x40000UL

Bit mask for CMU_ENDEM

Definition at line 325 of file efr32fg1p_cmu.h.

#define _CMU_LFRCOCTRL_ENDEM_SHIFT   18

Shift value for CMU_ENDEM

Definition at line 324 of file efr32fg1p_cmu.h.

#define _CMU_LFRCOCTRL_ENVREF_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_LFRCOCTRL

Definition at line 316 of file efr32fg1p_cmu.h.

#define _CMU_LFRCOCTRL_ENVREF_MASK   0x10000UL

Bit mask for CMU_ENVREF

Definition at line 315 of file efr32fg1p_cmu.h.

#define _CMU_LFRCOCTRL_ENVREF_SHIFT   16

Shift value for CMU_ENVREF

Definition at line 314 of file efr32fg1p_cmu.h.

#define _CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT   0x00000008UL

Mode DEFAULT for CMU_LFRCOCTRL

Definition at line 340 of file efr32fg1p_cmu.h.

#define _CMU_LFRCOCTRL_GMCCURTUNE_MASK   0xF0000000UL

Bit mask for CMU_GMCCURTUNE

Definition at line 339 of file efr32fg1p_cmu.h.

#define _CMU_LFRCOCTRL_GMCCURTUNE_SHIFT   28

Shift value for CMU_GMCCURTUNE

Definition at line 338 of file efr32fg1p_cmu.h.

#define _CMU_LFRCOCTRL_MASK   0xF30701FFUL

Mask for CMU_LFRCOCTRL

Definition at line 308 of file efr32fg1p_cmu.h.

#define _CMU_LFRCOCTRL_RESETVALUE   0x81060100UL

Default value for CMU_LFRCOCTRL

Definition at line 307 of file efr32fg1p_cmu.h.

#define _CMU_LFRCOCTRL_TIMEOUT_16CYCLES   0x00000001UL

Mode 16CYCLES for CMU_LFRCOCTRL

Definition at line 332 of file efr32fg1p_cmu.h.

#define _CMU_LFRCOCTRL_TIMEOUT_2CYCLES   0x00000000UL

Mode 2CYCLES for CMU_LFRCOCTRL

Definition at line 330 of file efr32fg1p_cmu.h.

#define _CMU_LFRCOCTRL_TIMEOUT_32CYCLES   0x00000002UL

Mode 32CYCLES for CMU_LFRCOCTRL

Definition at line 333 of file efr32fg1p_cmu.h.

#define _CMU_LFRCOCTRL_TIMEOUT_DEFAULT   0x00000001UL

Mode DEFAULT for CMU_LFRCOCTRL

Definition at line 331 of file efr32fg1p_cmu.h.

#define _CMU_LFRCOCTRL_TIMEOUT_MASK   0x3000000UL

Bit mask for CMU_TIMEOUT

Definition at line 329 of file efr32fg1p_cmu.h.

#define _CMU_LFRCOCTRL_TIMEOUT_SHIFT   24

Shift value for CMU_TIMEOUT

Definition at line 328 of file efr32fg1p_cmu.h.

#define _CMU_LFRCOCTRL_TUNING_DEFAULT   0x00000100UL

Mode DEFAULT for CMU_LFRCOCTRL

Definition at line 311 of file efr32fg1p_cmu.h.

#define _CMU_LFRCOCTRL_TUNING_MASK   0x1FFUL

Bit mask for CMU_TUNING

Definition at line 310 of file efr32fg1p_cmu.h.

Referenced by CMU_OscillatorTuningGet(), and CMU_OscillatorTuningSet().

#define _CMU_LFRCOCTRL_TUNING_SHIFT   0

Shift value for CMU_TUNING

Definition at line 309 of file efr32fg1p_cmu.h.

Referenced by CMU_OscillatorTuningGet(), and CMU_OscillatorTuningSet().

#define _CMU_LFXOCTRL_AGC_DEFAULT   0x00000001UL

Mode DEFAULT for CMU_LFXOCTRL

Definition at line 618 of file efr32fg1p_cmu.h.

#define _CMU_LFXOCTRL_AGC_MASK   0x8000UL

Bit mask for CMU_AGC

Definition at line 617 of file efr32fg1p_cmu.h.

#define _CMU_LFXOCTRL_AGC_SHIFT   15

Shift value for CMU_AGC

Definition at line 616 of file efr32fg1p_cmu.h.

#define _CMU_LFXOCTRL_BUFCUR_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_LFXOCTRL

Definition at line 627 of file efr32fg1p_cmu.h.

#define _CMU_LFXOCTRL_BUFCUR_MASK   0x100000UL

Bit mask for CMU_BUFCUR

Definition at line 626 of file efr32fg1p_cmu.h.

#define _CMU_LFXOCTRL_BUFCUR_SHIFT   20

Shift value for CMU_BUFCUR

Definition at line 625 of file efr32fg1p_cmu.h.

#define _CMU_LFXOCTRL_CUR_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_LFXOCTRL

Definition at line 622 of file efr32fg1p_cmu.h.

#define _CMU_LFXOCTRL_CUR_MASK   0x30000UL

Bit mask for CMU_CUR

Definition at line 621 of file efr32fg1p_cmu.h.

#define _CMU_LFXOCTRL_CUR_SHIFT   16

Shift value for CMU_CUR

Definition at line 620 of file efr32fg1p_cmu.h.

#define _CMU_LFXOCTRL_GAIN_DEFAULT   0x00000002UL

Mode DEFAULT for CMU_LFXOCTRL

Definition at line 608 of file efr32fg1p_cmu.h.

#define _CMU_LFXOCTRL_GAIN_MASK   0x1800UL

Bit mask for CMU_GAIN

Definition at line 607 of file efr32fg1p_cmu.h.

Referenced by CMU_LFXOInit().

#define _CMU_LFXOCTRL_GAIN_SHIFT   11

Shift value for CMU_GAIN

Definition at line 606 of file efr32fg1p_cmu.h.

Referenced by CMU_LFXOInit().

#define _CMU_LFXOCTRL_HIGHAMPL_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_LFXOCTRL

Definition at line 613 of file efr32fg1p_cmu.h.

#define _CMU_LFXOCTRL_HIGHAMPL_MASK   0x4000UL

Bit mask for CMU_HIGHAMPL

Definition at line 612 of file efr32fg1p_cmu.h.

#define _CMU_LFXOCTRL_HIGHAMPL_SHIFT   14

Shift value for CMU_HIGHAMPL

Definition at line 611 of file efr32fg1p_cmu.h.

#define _CMU_LFXOCTRL_MASK   0x0713DB7FUL

Mask for CMU_LFXOCTRL

Definition at line 591 of file efr32fg1p_cmu.h.

#define _CMU_LFXOCTRL_MODE_BUFEXTCLK   0x00000001UL

Mode BUFEXTCLK for CMU_LFXOCTRL

Definition at line 600 of file efr32fg1p_cmu.h.

#define _CMU_LFXOCTRL_MODE_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_LFXOCTRL

Definition at line 598 of file efr32fg1p_cmu.h.

#define _CMU_LFXOCTRL_MODE_DIGEXTCLK   0x00000002UL

Mode DIGEXTCLK for CMU_LFXOCTRL

Definition at line 601 of file efr32fg1p_cmu.h.

#define _CMU_LFXOCTRL_MODE_MASK   0x300UL

Bit mask for CMU_MODE

Definition at line 597 of file efr32fg1p_cmu.h.

Referenced by CMU_LFXOInit().

#define _CMU_LFXOCTRL_MODE_SHIFT   8

Shift value for CMU_MODE

Definition at line 596 of file efr32fg1p_cmu.h.

Referenced by CMU_LFXOInit().

#define _CMU_LFXOCTRL_MODE_XTAL   0x00000000UL

Mode XTAL for CMU_LFXOCTRL

Definition at line 599 of file efr32fg1p_cmu.h.

#define _CMU_LFXOCTRL_RESETVALUE   0x07009000UL

Default value for CMU_LFXOCTRL

Definition at line 590 of file efr32fg1p_cmu.h.

#define _CMU_LFXOCTRL_TIMEOUT_16KCYCLES   0x00000006UL

Mode 16KCYCLES for CMU_LFXOCTRL

Definition at line 637 of file efr32fg1p_cmu.h.

#define _CMU_LFXOCTRL_TIMEOUT_1KCYCLES   0x00000002UL

Mode 1KCYCLES for CMU_LFXOCTRL

Definition at line 633 of file efr32fg1p_cmu.h.

#define _CMU_LFXOCTRL_TIMEOUT_256CYCLES   0x00000001UL

Mode 256CYCLES for CMU_LFXOCTRL

Definition at line 632 of file efr32fg1p_cmu.h.

#define _CMU_LFXOCTRL_TIMEOUT_2CYCLES   0x00000000UL

Mode 2CYCLES for CMU_LFXOCTRL

Definition at line 631 of file efr32fg1p_cmu.h.

#define _CMU_LFXOCTRL_TIMEOUT_2KCYCLES   0x00000003UL

Mode 2KCYCLES for CMU_LFXOCTRL

Definition at line 634 of file efr32fg1p_cmu.h.

#define _CMU_LFXOCTRL_TIMEOUT_32KCYCLES   0x00000007UL

Mode 32KCYCLES for CMU_LFXOCTRL

Definition at line 639 of file efr32fg1p_cmu.h.

#define _CMU_LFXOCTRL_TIMEOUT_4KCYCLES   0x00000004UL

Mode 4KCYCLES for CMU_LFXOCTRL

Definition at line 635 of file efr32fg1p_cmu.h.

#define _CMU_LFXOCTRL_TIMEOUT_8KCYCLES   0x00000005UL

Mode 8KCYCLES for CMU_LFXOCTRL

Definition at line 636 of file efr32fg1p_cmu.h.

#define _CMU_LFXOCTRL_TIMEOUT_DEFAULT   0x00000007UL

Mode DEFAULT for CMU_LFXOCTRL

Definition at line 638 of file efr32fg1p_cmu.h.

#define _CMU_LFXOCTRL_TIMEOUT_MASK   0x7000000UL

Bit mask for CMU_TIMEOUT

Definition at line 630 of file efr32fg1p_cmu.h.

Referenced by CMU_LFXOInit().

#define _CMU_LFXOCTRL_TIMEOUT_SHIFT   24

Shift value for CMU_TIMEOUT

Definition at line 629 of file efr32fg1p_cmu.h.

Referenced by CMU_LFXOInit().

#define _CMU_LFXOCTRL_TUNING_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_LFXOCTRL

Definition at line 594 of file efr32fg1p_cmu.h.

#define _CMU_LFXOCTRL_TUNING_MASK   0x7FUL

Bit mask for CMU_TUNING

Definition at line 593 of file efr32fg1p_cmu.h.

Referenced by CMU_LFXOInit().

#define _CMU_LFXOCTRL_TUNING_SHIFT   0

Shift value for CMU_TUNING

Definition at line 592 of file efr32fg1p_cmu.h.

Referenced by CMU_LFXOInit().

#define _CMU_LOCK_LOCKKEY_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_LOCK

Definition at line 1772 of file efr32fg1p_cmu.h.

#define _CMU_LOCK_LOCKKEY_LOCK   0x00000000UL

Mode LOCK for CMU_LOCK

Definition at line 1773 of file efr32fg1p_cmu.h.

#define _CMU_LOCK_LOCKKEY_LO