EFR32FG1P133F256GM48Devices
Modules |
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| Bit Fields | |
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Processor and Core Peripheral Section.
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| Part | |
| Peripheral Declarations | |
| Peripheral Memory Map | |
| Peripheral Offsets | |
| Peripheral TypeDefs | |
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Device Specific Peripheral Register Structures.
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Macros |
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| #define | SET_BIT_FIELD (REG, MASK, VALUE, OFFSET) REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK)); |
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Set the value of a bit field within a register.
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Typedefs |
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| typedef enum IRQn | IRQn_Type |
Enumerations |
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| enum |
IRQn
{
NonMaskableInt_IRQn = -14, HardFault_IRQn = -13, MemoryManagement_IRQn = -12, BusFault_IRQn = -11, UsageFault_IRQn = -10, SVCall_IRQn = -5, DebugMonitor_IRQn = -4, PendSV_IRQn = -2, SysTick_IRQn = -1, EMU_IRQn = 0, FRC_PRI_IRQn = 1, WDOG0_IRQn = 2, FRC_IRQn = 3, MODEM_IRQn = 4, RAC_SEQ_IRQn = 5, RAC_RSM_IRQn = 6, BUFC_IRQn = 7, LDMA_IRQn = 8, GPIO_EVEN_IRQn = 9, TIMER0_IRQn = 10, USART0_RX_IRQn = 11, USART0_TX_IRQn = 12, ACMP0_IRQn = 13, ADC0_IRQn = 14, IDAC0_IRQn = 15, I2C0_IRQn = 16, GPIO_ODD_IRQn = 17, TIMER1_IRQn = 18, USART1_RX_IRQn = 19, USART1_TX_IRQn = 20, LEUART0_IRQn = 21, PCNT0_IRQn = 22, CMU_IRQn = 23, MSC_IRQn = 24, CRYPTO_IRQn = 25, LETIMER0_IRQn = 26, AGC_IRQn = 27, PROTIMER_IRQn = 28, RTCC_IRQn = 29, SYNTH_IRQn = 30, CRYOTIMER_IRQn = 31, RFSENSE_IRQn = 32, FPUEH_IRQn = 33 } |
Macro Definition Documentation
| #define SET_BIT_FIELD | ( |
REG,
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MASK,
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VALUE,
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OFFSET
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| ) | REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK)); |
Set the value of a bit field within a register.
- Parameters
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REGThe register to update MASKThe mask for the bit field to update VALUEThe value to write to the bit field OFFSETThe number of bits that the field is offset within the register. 0 (zero) means LSB.
Definition at line
439
of file
efr32fg1p133f256gm48.h
.
Typedef Documentation
Enumeration Type Documentation
| enum IRQn |
Interrupt Number Definition
Definition at line
58
of file
efr32fg1p133f256gm48.h
.