Peripheral Memory MapDevices > EFR32FG1P133F256GM48
Macros | |
#define | ACMP0_BASE (0x40000000UL) |
#define | ACMP1_BASE (0x40000400UL) |
#define | ADC0_BASE (0x40002000UL) |
#define | CMU_BASE (0x400E4000UL) |
#define | CRYOTIMER_BASE (0x4001E000UL) |
#define | CRYPTO_BASE (0x400F0000UL) |
#define | DEVINFO_BASE (0x0FE081B0UL) |
#define | EMU_BASE (0x400E3000UL) |
#define | FPUEH_BASE (0x400E1000UL) |
#define | GPCRC_BASE (0x4001C000UL) |
#define | GPIO_BASE (0x4000A000UL) |
#define | I2C0_BASE (0x4000C000UL) |
#define | IDAC0_BASE (0x40006000UL) |
#define | LDMA_BASE (0x400E2000UL) |
#define | LETIMER0_BASE (0x40046000UL) |
#define | LEUART0_BASE (0x4004A000UL) |
#define | LOCKBITS_BASE (0x0FE04000UL) |
#define | MSC_BASE (0x400E0000UL) |
#define | PCNT0_BASE (0x4004E000UL) |
#define | PRS_BASE (0x400E6000UL) |
#define | RMU_BASE (0x400E5000UL) |
#define | ROMTABLE_BASE (0xE00FFFD0UL) |
#define | RTCC_BASE (0x40042000UL) |
#define | TIMER0_BASE (0x40018000UL) |
#define | TIMER1_BASE (0x40018400UL) |
#define | USART0_BASE (0x40010000UL) |
#define | USART1_BASE (0x40010400UL) |
#define | USERDATA_BASE (0x0FE00000UL) |
#define | WDOG0_BASE (0x40052000UL) |
Macro Definition Documentation
#define ACMP0_BASE (0x40000000UL) |
ACMP0 base address
Definition at line 334
of file efr32fg1p133f256gm48.h
.
#define ACMP1_BASE (0x40000400UL) |
ACMP1 base address
Definition at line 335
of file efr32fg1p133f256gm48.h
.
#define ADC0_BASE (0x40002000UL) |
ADC0 base address
Definition at line 333
of file efr32fg1p133f256gm48.h
.
#define CMU_BASE (0x400E4000UL) |
CMU base address
Definition at line 317
of file efr32fg1p133f256gm48.h
.
#define CRYOTIMER_BASE (0x4001E000UL) |
CRYOTIMER base address
Definition at line 330
of file efr32fg1p133f256gm48.h
.
#define CRYPTO_BASE (0x400F0000UL) |
CRYPTO base address
Definition at line 318
of file efr32fg1p133f256gm48.h
.
#define DEVINFO_BASE (0x0FE081B0UL) |
DEVINFO base address
Definition at line 339
of file efr32fg1p133f256gm48.h
.
Referenced by SYSTEM_GetCalibrationValue().
#define EMU_BASE (0x400E3000UL) |
EMU base address
Definition at line 315
of file efr32fg1p133f256gm48.h
.
Referenced by CHIP_Init(), EMU_EnterEM4(), and RMU_ResetCauseGet().
#define FPUEH_BASE (0x400E1000UL) |
FPUEH base address
Definition at line 322
of file efr32fg1p133f256gm48.h
.
#define GPCRC_BASE (0x4001C000UL) |
GPCRC base address
Definition at line 323
of file efr32fg1p133f256gm48.h
.
#define GPIO_BASE (0x4000A000UL) |
GPIO base address
Definition at line 319
of file efr32fg1p133f256gm48.h
.
#define I2C0_BASE (0x4000C000UL) |
I2C0 base address
Definition at line 332
of file efr32fg1p133f256gm48.h
.
#define IDAC0_BASE (0x40006000UL) |
IDAC0 base address
Definition at line 336
of file efr32fg1p133f256gm48.h
.
#define LDMA_BASE (0x400E2000UL) |
LDMA base address
Definition at line 321
of file efr32fg1p133f256gm48.h
.
#define LETIMER0_BASE (0x40046000UL) |
LETIMER0 base address
Definition at line 329
of file efr32fg1p133f256gm48.h
.
#define LEUART0_BASE (0x4004A000UL) |
LEUART0 base address
Definition at line 328
of file efr32fg1p133f256gm48.h
.
#define LOCKBITS_BASE (0x0FE04000UL) |
Lock-bits page base address
Definition at line 341
of file efr32fg1p133f256gm48.h
.
#define MSC_BASE (0x400E0000UL) |
MSC base address
Definition at line 314
of file efr32fg1p133f256gm48.h
.
#define PCNT0_BASE (0x4004E000UL) |
PCNT0 base address
Definition at line 331
of file efr32fg1p133f256gm48.h
.
#define PRS_BASE (0x400E6000UL) |
PRS base address
Definition at line 320
of file efr32fg1p133f256gm48.h
.
#define RMU_BASE (0x400E5000UL) |
RMU base address
Definition at line 316
of file efr32fg1p133f256gm48.h
.
#define ROMTABLE_BASE (0xE00FFFD0UL) |
ROMTABLE base address
Definition at line 340
of file efr32fg1p133f256gm48.h
.
#define RTCC_BASE (0x40042000UL) |
RTCC base address
Definition at line 337
of file efr32fg1p133f256gm48.h
.
#define TIMER0_BASE (0x40018000UL) |
TIMER0 base address
Definition at line 324
of file efr32fg1p133f256gm48.h
.
#define TIMER1_BASE (0x40018400UL) |
TIMER1 base address
Definition at line 325
of file efr32fg1p133f256gm48.h
.
#define USART0_BASE (0x40010000UL) |
USART0 base address
Definition at line 326
of file efr32fg1p133f256gm48.h
.
#define USART1_BASE (0x40010400UL) |
USART1 base address
Definition at line 327
of file efr32fg1p133f256gm48.h
.
#define USERDATA_BASE (0x0FE00000UL) |
User data page base address
Definition at line 342
of file efr32fg1p133f256gm48.h
.
#define WDOG0_BASE (0x40052000UL) |
WDOG0 base address
Definition at line 338
of file efr32fg1p133f256gm48.h
.