A configuration for antenna selection.

Public Attributes#

bool

Antenna 0 Pin Enable.

bool

Antenna 1 Pin Enable.

uint8_t

Antenna 0 location for pin/port (EFR32 series 1) On EFR32 series 2 this field is called defaultPath and specifies the internal default RF path.

uint8_t

Antenna 0 output GPIO port.

uint8_t

Antenna 0 output GPIO pin.

uint8_t

Antenna 1 location for pin/port (EFR32 series 1 only)

uint8_t

Antenna 1 output GPIO port.

uint8_t

Antenna 1 output GPIO pin.

Public Attribute Documentation#

ant0PinEn#

bool RAIL_AntennaConfig_t::ant0PinEn

Antenna 0 Pin Enable.


Definition at line 300 of file chip/efr32/efr32xg1x/rail_chip_specific.h

ant1PinEn#

bool RAIL_AntennaConfig_t::ant1PinEn

Antenna 1 Pin Enable.


Definition at line 302 of file chip/efr32/efr32xg1x/rail_chip_specific.h

ant0Loc#

uint8_t RAIL_AntennaConfig_t::ant0Loc

Antenna 0 location for pin/port (EFR32 series 1) On EFR32 series 2 this field is called defaultPath and specifies the internal default RF path.

It is ignored on EFR32 series 2 parts that have only one RF path bonded out and on EFR32xG27 dual-band OPNs where the appropriate RF path is automatically set by RAIL to 0 for 2.4GHZ band and 1 for SubGHz band PHYs.


Definition at line 311 of file chip/efr32/efr32xg1x/rail_chip_specific.h

ant0Port#

uint8_t RAIL_AntennaConfig_t::ant0Port

Antenna 0 output GPIO port.


Definition at line 313 of file chip/efr32/efr32xg1x/rail_chip_specific.h

ant0Pin#

uint8_t RAIL_AntennaConfig_t::ant0Pin

Antenna 0 output GPIO pin.


Definition at line 315 of file chip/efr32/efr32xg1x/rail_chip_specific.h

ant1Loc#

uint8_t RAIL_AntennaConfig_t::ant1Loc

Antenna 1 location for pin/port (EFR32 series 1 only)


Definition at line 317 of file chip/efr32/efr32xg1x/rail_chip_specific.h

ant1Port#

uint8_t RAIL_AntennaConfig_t::ant1Port

Antenna 1 output GPIO port.


Definition at line 319 of file chip/efr32/efr32xg1x/rail_chip_specific.h

ant1Pin#

uint8_t RAIL_AntennaConfig_t::ant1Pin

Antenna 1 output GPIO pin.


Definition at line 321 of file chip/efr32/efr32xg1x/rail_chip_specific.h