PSRAM Driver#

PSRAM Memory Management driver.

Introduction#

PSRAM (Pseudo Static Random Access Memory) is a random-access memory whose internal structure is based on dynamic memory with refresh control signals generated internally, in the standby mode, so that it can mimic the functionality of a static memory. It combines the high density of DRAM with the ease-of-use of true SRAM. The M4 core communicates with the PSRAM via Quad SPI interface.

PSRAM Device Configuration#

The PSRAM Driver offers configuring the following:

  • Read-Write type

    • Normal: This supported only in SPI interface mode. Supports maximum frequency of 33MHz. Uses normal read and normal write command.

    • Fast: Supported in SPI and QPI mode. Uses fast read and normal write.

    • Quad IO: Supported in SPI and QPI mode. Uses fast quad read and write.

  • Interface mode

    • SPI Mode (Serial IO)

    • QPI Mode (Quad IO)

  • Operation frequency Source

    • Interface PLL Clock

    • ULP Reference clock

    • Modem PLL clock

    • SoC PLL clock

Linker configurations#

The text segment, data segment, bss, heap and stack can be placed in PSRAM by installing the respective components present under "PSRAM Linker Configurations" from "SOFTWARE COMPONENTS" GUI. Since PSRAM is already initiliazed in bootloader, these components can be installed and the respective segments can be placed in PSRAM without installing "PSRAM Core" component and without initializing psram from application.

Usage#

PSRAM Driver and QSPI are initiliazed by bootloader with Quad IO read-write type and QPI interface. The application is not required to reinitialize PSRAM device and QSPI unless the configurations required are different from the default set by the bootloader.

The PSRAM device handle "PSRAM_Device" of type sl_psram_info_type_t is defined "in sl_si91x_psram_handle.c".

sl_si91x_psram_uninit assumes that PSRAM was initialized with QPI mode and exits QPI mode within definition. If the PSRAM configuration in bootcode has SPI mode enabled, user is expected to comment the exit QPI mode function call in sl_si91x_psram_uninit.

To reconfigure and initliaze PSRAM, set required configurations from PSRAM Core component and call sl_si91x_psram_init within application.

Modules#

sl_psram_id_type_t

sl_psram_info_type_t

Enumerations#

enum
sl_psram_return_type_t {
PSRAM_SUCCESS
PSRAM_FAILURE
PSRAM_UNKNOWN
PSRAM_UNKNOWN_DEVICE
PSRAM_CLOCK_INIT_FAILURE
PSRAM_NOT_INITIALIZED
PSRAM_SUPPORTED_DEVICE
PSRAM_DEVICE_MISMATCH
PSRAM_INVALID_HSIZE
PSRAM_NULL_ADDRESS
PSRAM_INVALID_ADDRESS_LENGTH
PSRAM_AUTO_MODE
PSRAM_MANUAL_MODE
PSRAM_UNSUPPORTED_SECURITY
PSRAM_MAX_SEC_SEGMENT_REACH
}

PSRAM return error code.

enum
sl_psram_burst_size_type_t {
_WRAP16
_WRAP32
_WRAP64
_WRAP512
}

Wrap burst size enum.

enum
sl_psram_dma_status_type_t {
DMA_NONE
DMA_DONE
DMA_FAIL
}

PSRAM DMA status enum.

Functions#

sl_psram_return_type_t
sl_si91x_psram_init(void)

Initialize the PSRAM Device

sl_psram_return_type_t
sl_si91x_psram_uninit(void)

Uninitialize the PSRAM Device

sl_psram_return_type_t
sl_si91x_psram_reset(void)

Reset the PSRAM Device

sl_psram_return_type_t
sl_si91x_psram_manual_write_in_blocking_mode(uint32_t addr, void *SourceBuf, uint8_t hSize, uint32_t length)

Write data to PSRAM in manual mode

sl_psram_return_type_t
sl_si91x_psram_manual_read_in_blocking_mode(uint32_t addr, void *DestBuf, uint8_t hSize, uint32_t length)

Read data from PSRAM in manual mode

sl_psram_return_type_t
sl_si91x_psram_manual_write_in_dma_mode(uint32_t addr, void *SourceBuf, uint8_t hSize, uint32_t length, sl_psram_dma_status_type_t *dmastatus)

Write data to PSRAM in manual mode using DMA

sl_psram_return_type_t
sl_si91x_psram_manual_read_in_dma_mode(uint32_t addr, void *DestBuf, uint8_t hSize, uint32_t length, sl_psram_dma_status_type_t *dmaStatus)

Read data from PSRAM in manual mode using DMA

sl_psram_return_type_t
sl_si91x_psram_enable_encry_decry(uint16_t keySize)

Enable CTR encryption-decryption on PSRAM

Macros#

#define
PSRAM_READ_ID (0x9F)

Read ID command.

#define
PSRAM_ENTER_QPI (0x35)

Enter QPI interface mode command.

#define
PSRAM_EXIT_QPI (0xF5)

Exit QPI interface mode command.

#define
PSRAM_RESET_EN (0x66)

Reset Enable command.

#define
PSRAM_RESET (0x99)

Reset command.

#define
PSRAM_BURST_LEN (0xC0)

Burst Length Toggle command.

#define
PSRAM_MODE_REG_READ (0xB5)

Mode Register Read command.

#define
PSRAM_MODE_REG_WRITE (0xB1)

Mode Register Write command.

#define
PSRAM_HALF_SLEEP (0xC0)

Sleep Entry command.

#define
tXPHS_US (12)

Sleep Exit chip select low pulse width in us.

#define
tXHS_US (160)

Sleep Exit chip select low to CLK setup in us.

#define
tHS_US (8)

Minimum sleep duration in us.

Enumeration Documentation#

sl_psram_return_type_t#

sl_psram_return_type_t

PSRAM return error code.

Enumerator
PSRAM_SUCCESS
PSRAM_FAILURE
PSRAM_UNKNOWN
PSRAM_UNKNOWN_DEVICE
PSRAM_CLOCK_INIT_FAILURE
PSRAM_NOT_INITIALIZED
PSRAM_SUPPORTED_DEVICE
PSRAM_DEVICE_MISMATCH
PSRAM_INVALID_HSIZE
PSRAM_NULL_ADDRESS
PSRAM_INVALID_ADDRESS_LENGTH
PSRAM_AUTO_MODE
PSRAM_MANUAL_MODE
PSRAM_UNSUPPORTED_SECURITY
PSRAM_MAX_SEC_SEGMENT_REACH

Definition at line 79 of file components/device/silabs/si91x/mcu/drivers/unified_api/inc/sl_si91x_psram.h

sl_psram_burst_size_type_t#

sl_psram_burst_size_type_t

Wrap burst size enum.

Enumerator
_WRAP16
_WRAP32
_WRAP64
_WRAP512

Definition at line 98 of file components/device/silabs/si91x/mcu/drivers/unified_api/inc/sl_si91x_psram.h

sl_psram_dma_status_type_t#

sl_psram_dma_status_type_t

PSRAM DMA status enum.

Enumerator
DMA_NONE
DMA_DONE
DMA_FAIL

Definition at line 101 of file components/device/silabs/si91x/mcu/drivers/unified_api/inc/sl_si91x_psram.h

Function Documentation#

sl_si91x_psram_init#

sl_psram_return_type_t sl_si91x_psram_init (void )

Initialize the PSRAM Device

Parameters
N/A

Returns

  • Status Code of the operation


Definition at line 192 of file components/device/silabs/si91x/mcu/drivers/unified_api/inc/sl_si91x_psram.h

sl_si91x_psram_uninit#

sl_psram_return_type_t sl_si91x_psram_uninit (void )

Uninitialize the PSRAM Device

Parameters
N/A

Returns

  • Status Code of the operation


Definition at line 201 of file components/device/silabs/si91x/mcu/drivers/unified_api/inc/sl_si91x_psram.h

sl_si91x_psram_reset#

sl_psram_return_type_t sl_si91x_psram_reset (void )

Reset the PSRAM Device

Parameters
N/A

Returns

  • Status Code of the operation


Definition at line 210 of file components/device/silabs/si91x/mcu/drivers/unified_api/inc/sl_si91x_psram.h

sl_si91x_psram_manual_write_in_blocking_mode#

sl_psram_return_type_t sl_si91x_psram_manual_write_in_blocking_mode (uint32_t addr, void * SourceBuf, uint8_t hSize, uint32_t length)

Write data to PSRAM in manual mode

Parameters
[in]addr

PSRAM address for write operation

[in]SourceBuf

Reference of the Source buffer

[in]hSize

Size of each element

[in]length

Number of elements for write operation

Returns

  • Status Code of the operation


Definition at line 231 of file components/device/silabs/si91x/mcu/drivers/unified_api/inc/sl_si91x_psram.h

sl_si91x_psram_manual_read_in_blocking_mode#

sl_psram_return_type_t sl_si91x_psram_manual_read_in_blocking_mode (uint32_t addr, void * DestBuf, uint8_t hSize, uint32_t length)

Read data from PSRAM in manual mode

Parameters
[in]addr

PSRAM address for read operation

[in]DestBuf

Size of each element

[in]hSize

Number of elements for read operation

[out]length

Reference of the Destination buffer

Returns

  • Status Code of the operation


Definition at line 255 of file components/device/silabs/si91x/mcu/drivers/unified_api/inc/sl_si91x_psram.h

sl_si91x_psram_manual_write_in_dma_mode#

sl_psram_return_type_t sl_si91x_psram_manual_write_in_dma_mode (uint32_t addr, void * SourceBuf, uint8_t hSize, uint32_t length, sl_psram_dma_status_type_t * dmastatus)

Write data to PSRAM in manual mode using DMA

Parameters
[in]addr

PSRAM address for write operation

[in]SourceBuf

Reference of the Source buffer

[in]hSize

Size of each element

[in]length

Number of elements for write operation

[out]dmastatus

DMA operation completion status

Returns

  • Status Code of the operation


Definition at line 282 of file components/device/silabs/si91x/mcu/drivers/unified_api/inc/sl_si91x_psram.h

sl_si91x_psram_manual_read_in_dma_mode#

sl_psram_return_type_t sl_si91x_psram_manual_read_in_dma_mode (uint32_t addr, void * DestBuf, uint8_t hSize, uint32_t length, sl_psram_dma_status_type_t * dmaStatus)

Read data from PSRAM in manual mode using DMA

Parameters
[in]addr

PSRAM address for read operation

[in]DestBuf

Size of each element

[in]hSize

Number of elements for read operation

[out]length

Reference of the Destination buffer

[out]dmaStatus

DMA operation completion status

Returns

  • Status Code of the operation


Definition at line 310 of file components/device/silabs/si91x/mcu/drivers/unified_api/inc/sl_si91x_psram.h

sl_si91x_psram_enable_encry_decry#

sl_psram_return_type_t sl_si91x_psram_enable_encry_decry (uint16_t keySize)

Enable CTR encryption-decryption on PSRAM

Parameters
[in]keySize

Pass 128/256-Bit size

Returns

  • Status Code of the operation


Definition at line 346 of file components/device/silabs/si91x/mcu/drivers/unified_api/inc/sl_si91x_psram.h

Macro Definition Documentation#

PSRAM_READ_ID#

#define PSRAM_READ_ID
Value:
(0x9F)

Read ID command.


Definition at line 36 of file components/device/silabs/si91x/mcu/drivers/unified_api/inc/sl_si91x_psram.h

PSRAM_ENTER_QPI#

#define PSRAM_ENTER_QPI
Value:
(0x35)

Enter QPI interface mode command.


Definition at line 37 of file components/device/silabs/si91x/mcu/drivers/unified_api/inc/sl_si91x_psram.h

PSRAM_EXIT_QPI#

#define PSRAM_EXIT_QPI
Value:
(0xF5)

Exit QPI interface mode command.


Definition at line 38 of file components/device/silabs/si91x/mcu/drivers/unified_api/inc/sl_si91x_psram.h

PSRAM_RESET_EN#

#define PSRAM_RESET_EN
Value:
(0x66)

Reset Enable command.


Definition at line 39 of file components/device/silabs/si91x/mcu/drivers/unified_api/inc/sl_si91x_psram.h

PSRAM_RESET#

#define PSRAM_RESET
Value:
(0x99)

Reset command.


Definition at line 40 of file components/device/silabs/si91x/mcu/drivers/unified_api/inc/sl_si91x_psram.h

PSRAM_BURST_LEN#

#define PSRAM_BURST_LEN
Value:
(0xC0)

Burst Length Toggle command.


Definition at line 41 of file components/device/silabs/si91x/mcu/drivers/unified_api/inc/sl_si91x_psram.h

PSRAM_MODE_REG_READ#

#define PSRAM_MODE_REG_READ
Value:
(0xB5)

Mode Register Read command.


Definition at line 42 of file components/device/silabs/si91x/mcu/drivers/unified_api/inc/sl_si91x_psram.h

PSRAM_MODE_REG_WRITE#

#define PSRAM_MODE_REG_WRITE
Value:
(0xB1)

Mode Register Write command.


Definition at line 43 of file components/device/silabs/si91x/mcu/drivers/unified_api/inc/sl_si91x_psram.h

PSRAM_HALF_SLEEP#

#define PSRAM_HALF_SLEEP
Value:
(0xC0)

Sleep Entry command.


Definition at line 44 of file components/device/silabs/si91x/mcu/drivers/unified_api/inc/sl_si91x_psram.h

tXPHS_US#

#define tXPHS_US
Value:
(12)

Sleep Exit chip select low pulse width in us.


Definition at line 70 of file components/device/silabs/si91x/mcu/drivers/unified_api/inc/sl_si91x_psram.h

tXHS_US#

#define tXHS_US
Value:
(160)

Sleep Exit chip select low to CLK setup in us.


Definition at line 71 of file components/device/silabs/si91x/mcu/drivers/unified_api/inc/sl_si91x_psram.h

tHS_US#

#define tHS_US
Value:
(8)

Minimum sleep duration in us.


Definition at line 72 of file components/device/silabs/si91x/mcu/drivers/unified_api/inc/sl_si91x_psram.h