Configuration Feature Bitmap#

SL_SI91X_FEAT_SLEEP_GPIO_SEL_BITMAP#

#define SL_SI91X_FEAT_SLEEP_GPIO_SEL_BITMAP

BIT(0)

Selects the GPIO for wakeup indication to the host.

When this bit is disabled, UULP_GPIO_3 is used as the wakeup indication. When enabled, UULP_GPIO_0 is used instead.

Note

• Bit 1 is reserved and should not be used.

• Not applicable for SI917.

SL_SI91X_FEAT_DVS_SEL_CONFIG_1#

#define SL_SI91X_FEAT_DVS_SEL_CONFIG_1

BIT(2)

Enables Dynamic Voltage Selection (DVS) Configuration 1.

This bit configures the dynamic voltage selection for the system.

Note

• Not applicable for SI917.

SL_SI91X_FEAT_DVS_SEL_CONFIG_2#

#define SL_SI91X_FEAT_DVS_SEL_CONFIG_2

BIT(3)

Enables Dynamic Voltage Selection (DVS) Configuration 2.

This bit configures the dynamic voltage selection for the system.

Note

• Not applicable for SI917.

SL_SI91X_FEAT_DVS_SEL_CONFIG_3#

#define SL_SI91X_FEAT_DVS_SEL_CONFIG_3

BIT(4)

Enables Dynamic Voltage Selection (DVS) Configuration 3.

This bit configures the dynamic voltage selection for the system.

Note

• Not applicable for SI917.

SL_SI91X_FEAT_DVS_SEL_CONFIG_4#

#define SL_SI91X_FEAT_DVS_SEL_CONFIG_4

BIT(5)

Enables Dynamic Voltage Selection (DVS) Configuration 4.

This bit configures the dynamic voltage selection for the system.

Note

• Not applicable for SI917.

SL_SI91X_EXTERNAL_PMU_GOOD_TIME_100us#

#define SL_SI91X_EXTERNAL_PMU_GOOD_TIME_100us

BIT(6)

Configures External PMU good time to 100 µs.

This bit selects an external PMU good time of 100 microseconds.

Note

• These bits are used to select external PMU good time. 1 to 15 means 100 usec to 1500 usec (in 100 usec granularity)

• Not applicable for SI917.

SL_SI91X_EXTERNAL_PMU_GOOD_TIME_200us#

#define SL_SI91X_EXTERNAL_PMU_GOOD_TIME_200us

BIT(7)

Configures External PMU good time to 200 µs.

This bit selects an external PMU good time of 200 microseconds.

Note

• Not applicable for SI917.

SL_SI91X_EXTERNAL_PMU_GOOD_TIME_300us#

#define SL_SI91X_EXTERNAL_PMU_GOOD_TIME_300us

(BIT(6) | BIT(7))

Configures External PMU good time to 300 µs.

This is a combination of 100 µs and 200 µs good times, totaling 300 microseconds.

Note

• Not applicable for SI917.

SL_SI91X_EXTERNAL_PMU_GOOD_TIME_400us#

#define SL_SI91X_EXTERNAL_PMU_GOOD_TIME_400us

BIT(8)

Configures External PMU good time to 400 µs.

This bit selects an external PMU good time of 400 microseconds.

Note

• Not applicable for SI917.

SL_SI91X_EXTERNAL_PMU_GOOD_TIME_500us#

#define SL_SI91X_EXTERNAL_PMU_GOOD_TIME_500us

(BIT(6) | BIT(8))

Configures External PMU good time to 500 µs.

This is a combination of 100 µs and 400 µs good times, totaling 500 microseconds.

Note

• Not applicable for SI917.

SL_SI91X_EXTERNAL_PMU_GOOD_TIME_600us#

#define SL_SI91X_EXTERNAL_PMU_GOOD_TIME_600us

(BIT(7) | BIT(8))

Configures External PMU good time to 600 µs.

This is a combination of 200 µs and 400 µs good times, totaling 600 microseconds.

Note

• Not applicable for SI917.

SL_SI91X_EXTERNAL_PMU_GOOD_TIME_700us#

#define SL_SI91X_EXTERNAL_PMU_GOOD_TIME_700us

(BIT(6) | BIT(7) | BIT(8))

Configures External PMU good time to 700 µs.

This is a combination of 100 µs, 200 µs, and 400 µs good times, totaling 700 microseconds.

Note

• Not applicable for SI917.

SL_SI91X_EXTERNAL_PMU_GOOD_TIME_800us#

#define SL_SI91X_EXTERNAL_PMU_GOOD_TIME_800us

BIT(9)

Configures External PMU good time to 800 µs.

This bit selects an external PMU good time of 800 microseconds.

Note

• Not applicable for SI917.

SL_SI91X_EXTERNAL_PMU_GOOD_TIME_900us#

#define SL_SI91X_EXTERNAL_PMU_GOOD_TIME_900us

(BIT(6) | BIT(9))

Configures External PMU good time to 900 µs.

This is a combination of 100 µs and 800 µs good times, totaling 900 microseconds.

Note

• Not applicable for SI917.

SL_SI91X_EXTERNAL_PMU_GOOD_TIME_1000us#

#define SL_SI91X_EXTERNAL_PMU_GOOD_TIME_1000us

(BIT(7) | BIT(9))

Configures External PMU good time to 1000 µs.

This is a combination of 200 µs and 800 µs good times, totaling 1000 microseconds.

Note

• Not applicable for SI917.

SL_SI91X_EXTERNAL_PMU_GOOD_TIME_1100us#

#define SL_SI91X_EXTERNAL_PMU_GOOD_TIME_1100us

(BIT(6) | BIT(7) | BIT(9))

Configures External PMU good time to 1100 µs.

This is a combination of 100 µs, 200 µs, and 800 µs good times, totaling 1100 microseconds.

Note

• Not applicable for SI917.

SL_SI91X_EXTERNAL_PMU_GOOD_TIME_1200us#

#define SL_SI91X_EXTERNAL_PMU_GOOD_TIME_1200us

(BIT(8) | BIT(9))

Configures External PMU good time to 1200 µs.

This is a combination of 400 µs and 800 µs good times, totaling 1200 microseconds.

Note

• Not applicable for SI917.

SL_SI91X_EXTERNAL_PMU_GOOD_TIME_1300us#

#define SL_SI91X_EXTERNAL_PMU_GOOD_TIME_1300us

(BIT(6) | BIT(8) | BIT(9))

Configures External PMU good time to 1300 µs.

This is a combination of 100 µs, 400 µs, and 800 µs good times, totaling 1300 microseconds.

Note

• Not applicable for SI917.

SL_SI91X_EXTERNAL_PMU_GOOD_TIME_1400us#

#define SL_SI91X_EXTERNAL_PMU_GOOD_TIME_1400us

(BIT(7) | BIT(8) | BIT(9))

Configures External PMU good time to 1400 µs.

This is a combination of 200 µs, 400 µs, and 800 µs good times, totaling 1400 microseconds.

Note

• Not applicable for SI917.

SL_SI91X_EXTERNAL_PMU_GOOD_TIME_1500us#

#define SL_SI91X_EXTERNAL_PMU_GOOD_TIME_1500us

(BIT(6) | BIT(7) | BIT(8) | BIT(9))

Configures External PMU good time to 1500 µs.

This is a combination of 100 µs, 200 µs, 400 µs, and 800 µs good times, totaling 1500 microseconds.

Note

• Not applicable for SI917.

SL_SI91X_FEAT_EXTERNAL_LDO_SEL#

#define SL_SI91X_FEAT_EXTERNAL_LDO_SEL

BIT(10)

Enables selection of external LDO voltage.

When enabled, this bit allows the selection between using an external LDO or an internal PMU. If both the external LDO selection and the LDO voltage are configured, the system uses the external LDO. If this bit is cleared, the internal PMU is used.

Note

• These bits are used for External LDO selection External PMU:

  1. Incase of External PMU, User has to set EXTERNAL_PMU_GOOD_TIME_CONFIGURATION value to external PMU good time, If this is zero then it indicates using Internal PMU.

  2. Incase of External PMU 1.0v or 1.05v, User has to set both the bits config_feature_bit_map[11] & config_feature_bit_map[10].

• Not applicable for SI917.

SL_SI91X_FEAT_EXTERNAL_LDO_VOL#

#define SL_SI91X_FEAT_EXTERNAL_LDO_VOL

BIT(11)

Selects the external LDO voltage.

This field is relevant only if SL_SI91X_FEAT_EXTERNAL_LDO_SEL is enabled (i.e., BIT(10) is set). If this bit is set, the LDO voltage is configured to 1.0V; if cleared, it is set to 1.1V.

Note

• Not applicable for SI917.

SL_SI91X_FEAT_EAP_TLS_V1P0#

#define SL_SI91X_FEAT_EAP_TLS_V1P0

BIT(14)

Enables TLS version 1.0 for enterprise security.

Note

• Bit 12 -13 are reserved

SL_SI91X_FEAT_EAP_TLS_V1P2#

#define SL_SI91X_FEAT_EAP_TLS_V1P2

BIT(15)

Enables TLS version 1.2 for enterprise security.

SL_SI91X_FEAT_CONC_STA_AP_DYN_SWITCH_SEL#

#define SL_SI91X_FEAT_CONC_STA_AP_DYN_SWITCH_SEL

BIT(17)

Configures dynamic switching between STA and AP modes.

This bit enables or disables dynamic switching between Station (STA) and Access Point (AP) modes. When enabled, the system can dynamically switch between STA and AP modes based on operational requirements or network conditions. This feature is useful for applications requiring flexible mode changes to optimize performance or power consumption.

Note

• Enabling this feature allows the system to switch modes dynamically, which can improve adaptability in varying network scenarios. Make sure to configure the system appropriately for the desired switching behavior.

• Bit 16 is reserved

SL_SI91X_ULP_GPIO9_FOR_UART2_TX#

#define SL_SI91X_ULP_GPIO9_FOR_UART2_TX

BIT(18)

Selects ULP_GPIO_9 to enable firmware debug prints.

If this bit is not set, the default UART2-TX pin GPIO_6 is used.

Note

• SI917 supports prints only on ULP_GPIO_9.

SL_SI91X_FEAT_DISABLE_MCS_5_6_7_DATARATES#

#define SL_SI91X_FEAT_DISABLE_MCS_5_6_7_DATARATES

BIT(19)

Disables MCS-5, 6, and 7 data rates.

This bit is used to disable the higher MCS data rates (5, 6, and 7) for reduced data rate requirements.

SL_SI91X_FEAT_DISABLE_SHORT_GI#

#define SL_SI91X_FEAT_DISABLE_SHORT_GI

BIT(20)

Disables Short Guard Interval (Short-GI).

This bit disables the use of Short-GI, which may affect the timing and performance of the system.

SL_SI91X_PTA_3WIRE_EN#

#define SL_SI91X_PTA_3WIRE_EN

BIT(21)

Enables the PTA-3WIRE feature.

Set this bit to enable and use the PTA 3-wire feature, which requires additional configuration settings.

SL_SI91X_PTA_3WIRE_CONFIG_SEL#

#define SL_SI91X_PTA_3WIRE_CONFIG_SEL

(config_sel)

Selects the PTA-3WIRE configuration.

This macro configures the PTA-3WIRE settings. Bits 22 and 23 are used to set NUM_CONN_EVENTS. A reserved setting of 0 should be used for future use. The 3-wire configuration includes ULP_GPIO_0 (Grant pin driven by DUT), ULP_GPIO_1 (Request input pin for DUT), and ULP_GPIO_6 (Priority input pin for DUT).

SL_SI91X_XTAL_GOODTIME_1000us#

#define SL_SI91X_XTAL_GOODTIME_1000us

0

Configures XTAL good time to 1000 µs.

This bit selects a default XTAL good time of 1000 microseconds. This setting is applicable from Release 2.3.0 onward. Prior releases have reserved config_feature_bitmap[31:17]. This setting is intended for chip users and not applicable for device users.

Note

• Not applicable for SI917.

SL_SI91X_XTAL_GOODTIME_2000us#

#define SL_SI91X_XTAL_GOODTIME_2000us

BIT(24)

Configures XTAL good time to 2000 µs.

This bit selects an XTAL good time of 2000 microseconds.

Note

• Not applicable for SI917.

SL_SI91X_XTAL_GOODTIME_3000us#

#define SL_SI91X_XTAL_GOODTIME_3000us

BIT(25)

Configures XTAL good time to 3000 µs.

This bit selects an XTAL good time of 3000 microseconds.

Note

• Not applicable for SI917.

SL_SI91X_XTAL_GOODTIME_600us#

#define SL_SI91X_XTAL_GOODTIME_600us

(BIT(24) | BIT(25))

Configures XTAL good time to 600 µs.

This is a combination of 2000 µs and 3000 µs XTAL good times, totaling 600 microseconds.

Note

• Not applicable for SI917.

SL_SI91X_ENABLE_ENHANCED_MAX_PSP#

#define SL_SI91X_ENABLE_ENHANCED_MAX_PSP

BIT(26)

Enables Enhanced Max PSP.

Set this bit to enable the Enhanced Max PSP feature for improved performance.

SL_SI91X_ENABLE_DEBUG_BBP_TEST_PINS#

#define SL_SI91X_ENABLE_DEBUG_BBP_TEST_PINS

BIT(27)

Enables BBP Test Pins.

Set this bit to enable the use of BBP test pins for debugging and testing purposes.

Note

• Bits 28 - 31 are reserved for future use.