Clock Manager#
Introduction#
The Clock Manager module is responsible for configuring the clock tree in the Si91x system. It enhances the clock management features provided by the GSDK's emlib and device_init services, offering additional functionality for selecting clock sources and setting dividers. This module ensures optimized performance and power efficiency across various system components by managing clock configurations according to application requirements.
Configuration#
The Clock Manager supports a variety of configurations:
Clock Source Selection: Allows specific clock sources to be chosen for different branches.
Divider Configuration: Modifies clock frequencies by setting divider values.
Configuration is typically performed during device initialization using configuration files and source code.
Usage#
The following steps outline typical usage of the Clock Manager:
Initialize the Clock Manager with desired configuration settings.
Set up oscillator sources and configure clock dividers.
Use runtime APIs to manage dynamic clock changes.
Maintain stable clock configurations to ensure system reliability.
Benefits#
Manages complex clock trees efficiently.
Enhances system stability and performance.
Supports a wide range of Si91x devices.
Optimizes power consumption through efficient clock management.
Typedefs#
Typedef to select the clock source for the M4 core in the Si91x SOC.
Functions#
To configure the M4 core clock source and configure the PLL frequency if selected as source.
To set the selected PLL (Phase-Locked Loop) clock to the desired frequency.
To read the currently active M4 core clock source and its frequency.
Macros#
PLL reference clock frequency value of RC_32MHZ_CLK.
PLL reference clock frequency value of XTAL_CLK.
Typedef Documentation#
sl_si91x_m4_soc_clk_src_sel_t#
sl_si91x_m4_soc_clk_src_sel_t
Typedef to select the clock source for the M4 core in the Si91x SOC.
This typedef maps to the M4_SOC_CLK_SRC_SEL_T type, which defines the possible clock source selections for the M4 core. The clock source selection impacts the operating frequency and performance characteristics of the M4 processor within the Si91x SOC.
Users can configure the clock source to optimize power consumption or performance based on application requirements.
Note
Ensure that the selected clock source is properly configured and stable before switching to avoid system instability.
68 of file components/device/silabs/si91x/mcu/drivers/service/clock_manager/inc/sl_si91x_clock_manager.hFunction Documentation#
sl_si91x_clock_manager_m4_set_core_clk#
sl_status_t sl_si91x_clock_manager_m4_set_core_clk (M4_SOC_CLK_SRC_SEL_T clk_source, uint32_t pll_freq)
To configure the M4 core clock source and configure the PLL frequency if selected as source.
| [in] | clk_source | Enum value representing different core clock sources. |
| [in] | pll_freq | Desired M4 core frequency in MHz. |
Returns
sl_status_t Status code indicating the result:
SL_STATUS_OK (0x0000) - Success.
Corresponding error code on failure.
For more information on status codes, see SL STATUS DOCUMENTATION.
87 of file components/device/silabs/si91x/mcu/drivers/service/clock_manager/inc/sl_si91x_clock_manager.hsl_si91x_clock_manager_set_pll_freq#
sl_status_t sl_si91x_clock_manager_set_pll_freq (PLL_TYPE_T pll_type, uint32_t pll_freq, uint32_t pll_ref_clk)
To set the selected PLL (Phase-Locked Loop) clock to the desired frequency.
| [in] | pll_type | Enum specifying the type of PLL to configure. |
| [in] | pll_freq | Desired frequency for the PLL clock (in MHz). |
| [in] | pll_ref_clk | Reference clock frequency for the PLL configuration. |
Returns
sl_status_t Status code indicating the result:
SL_STATUS_OK (0x0000) - Success.
Corresponding error code on failure.
For more information on status codes, see SL STATUS DOCUMENTATION.
104 of file components/device/silabs/si91x/mcu/drivers/service/clock_manager/inc/sl_si91x_clock_manager.hsl_si91x_clock_manager_m4_get_core_clk_src_freq#
sl_si91x_m4_soc_clk_src_sel_t sl_si91x_clock_manager_m4_get_core_clk_src_freq (uint32_t * core_clock)
To read the currently active M4 core clock source and its frequency.
| [out] | core_clock | Pointer to a variable where the current core clock frequency will be stored (in MHz). |
Returns
sl_si91x_m4_soc_clk_src_sel_t The currently active core clock source:
0: M4_ULPREFCLK
2: M4_SOCPLLCLK
3: M4_MODEMPLLCLK1
4: M4_INTFPLLCLK
5: M4_SLEEPCLK
For more information on status codes, see SL STATUS DOCUMENTATION.
121 of file components/device/silabs/si91x/mcu/drivers/service/clock_manager/inc/sl_si91x_clock_manager.hMacro Definition Documentation#
PLL_REF_CLK_VAL_RC_32MHZ#
#define PLL_REF_CLK_VAL_RC_32MHZValue:
((uint32_t)(32000000))
PLL reference clock frequency value of RC_32MHZ_CLK.
50 of file components/device/silabs/si91x/mcu/drivers/service/clock_manager/inc/sl_si91x_clock_manager.hPLL_REF_CLK_VAL_XTAL#
#define PLL_REF_CLK_VAL_XTALValue:
((uint32_t)(40000000))
PLL reference clock frequency value of XTAL_CLK.
51 of file components/device/silabs/si91x/mcu/drivers/service/clock_manager/inc/sl_si91x_clock_manager.h