Description

Clock management unit (CMU) Peripheral API.

This module contains functions for the CMU peripheral of Silicon Labs 32-bit MCUs and SoCs. The CMU module controls oscillators, clocks gates, clock multiplexers, pre-scalers, calibration modules and wait-states.

Data Structures
struct	CMU_LFXOInit_TypeDef
	LFXO initialization structure.

struct	CMU_HFXOInit_TypeDef
	HFXO initialization structure.

struct	CMU_DPLLInit_TypeDef
	DPLL initialization structure.

Functions
CMU_AUXHFRCOFreq_TypeDef	CMU_AUXHFRCOBandGet (void)
	Get the current AUXHFRCO frequency.

void	CMU_AUXHFRCOBandSet ( CMU_AUXHFRCOFreq_TypeDef setFreq)
	Set AUXHFRCO calibration for the selected target frequency.

uint32_t	CMU_Calibrate (uint32_t HFCycles, CMU_Osc_TypeDef reference)
	Calibrate the clock.

void	CMU_CalibrateConfig (uint32_t downCycles, CMU_Osc_TypeDef downSel, CMU_Osc_TypeDef upSel)
	Configure the clock calibration.

uint32_t	CMU_CalibrateCountGet (void)
	Get the calibration count register.

void	CMU_ClockEnable ( CMU_Clock_TypeDef clock, bool enable)
	Enable/disable a clock.

CMU_ClkDiv_TypeDef	CMU_ClockDivGet ( CMU_Clock_TypeDef clock)
	Get the clock divisor/prescaler.

void	CMU_ClockDivSet ( CMU_Clock_TypeDef clock, CMU_ClkDiv_TypeDef div)
	Set the clock divisor/prescaler.

uint32_t	CMU_ClockFreqGet ( CMU_Clock_TypeDef clock)
	Get the clock frequency for a clock point.

void	CMU_ClockPrescSet ( CMU_Clock_TypeDef clock, CMU_ClkPresc_TypeDef presc)
	Set the clock prescaler.

uint32_t	CMU_ClockPrescGet ( CMU_Clock_TypeDef clock)
	Get the clock prescaler.

void	CMU_ClockSelectSet ( CMU_Clock_TypeDef clock, CMU_Select_TypeDef ref)
	Select the reference clock/oscillator used for a clock branch.

CMU_Select_TypeDef	CMU_ClockSelectGet ( CMU_Clock_TypeDef clock)
	Get the currently selected reference clock used for a clock branch.

uint16_t	CMU_LF_ClockPrecisionGet ( CMU_Clock_TypeDef clock)
	Gets the precision (in PPM) of the specified low frequency clock branch.

bool	CMU_DPLLLock (const CMU_DPLLInit_TypeDef *init)
	Lock the DPLL to a given frequency.

void	CMU_FreezeEnable (bool enable)
	CMU low frequency register synchronization freeze control.

CMU_HFRCOFreq_TypeDef	CMU_HFRCOBandGet (void)
	Get the current HFRCO frequency.

void	CMU_HFRCOBandSet ( CMU_HFRCOFreq_TypeDef setFreq)
	Set the HFRCO calibration for the selected target frequency.

void	CMU_HFXOAutostartEnable (uint32_t userSel, bool enEM0EM1Start, bool enEM0EM1StartSel)
	Enable or disable HFXO autostart.

void	CMU_HFXOInit (const CMU_HFXOInit_TypeDef *hfxoInit)
	Set HFXO control registers.

uint32_t	CMU_LCDClkFDIVGet (void)
	Get the LCD framerate divisor (FDIV) setting.

void	CMU_LCDClkFDIVSet (uint32_t div)
	Set the LCD framerate divisor (FDIV) setting.

void	CMU_LFXOInit (const CMU_LFXOInit_TypeDef *lfxoInit)
	Set LFXO control registers.

void	CMU_LFXOPrecisionSet (uint16_t precision)
	Sets LFXO's crystal precision, in PPM.

void	CMU_OscillatorEnable ( CMU_Osc_TypeDef osc, bool enable, bool wait)
	Enable/disable oscillator.

uint32_t	CMU_OscillatorTuningGet ( CMU_Osc_TypeDef osc)
	Get the oscillator frequency tuning setting.

void	CMU_OscillatorTuningSet ( CMU_Osc_TypeDef osc, uint32_t val)
	Set the oscillator frequency tuning control.

bool	CMU_OscillatorTuningWait ( CMU_Osc_TypeDef osc, CMU_HFXOTuningMode_TypeDef mode)
	Wait for the oscillator tuning optimization.

bool	CMU_OscillatorTuningOptimize ( CMU_Osc_TypeDef osc, CMU_HFXOTuningMode_TypeDef mode, bool wait)
	Start and optionally wait for the oscillator tuning optimization.

void	CMU_PCNTClockExternalSet (unsigned int instance, bool external)
	Select the PCNTn clock.

bool	CMU_PCNTClockExternalGet (unsigned int instance)
	Determine if the currently selected PCNTn clock used is external or LFBCLK.

void	CMU_UpdateWaitStates (uint32_t freq, int vscale)
	Configure various wait states to switch to a certain frequency and a certain voltage scale.

void	CMU_CalibrateCont (bool enable)
	Configure continuous calibration mode.

void	CMU_CalibrateStart (void)
	Start calibration.

void	CMU_CalibrateStop (void)
	Stop the calibration counters.

uint32_t	CMU_DivToLog2 ( CMU_ClkDiv_TypeDef div)
	Convert dividend to logarithmic value.

void	CMU_DPLLUnlock (void)
	Unlock DPLL.

void	CMU_IntClear (uint32_t flags)
	Clear one or more pending CMU interrupts.

void	CMU_IntDisable (uint32_t flags)
	Disable one or more CMU interrupts.

void	CMU_IntEnable (uint32_t flags)
	Enable one or more CMU interrupts.

uint32_t	CMU_IntGet (void)
	Get pending CMU interrupts.

uint32_t	CMU_IntGetEnabled (void)
	Get enabled and pending CMU interrupt flags.

void	CMU_IntSet (uint32_t flags)
	Set one or more pending CMU interrupts.

void	CMU_Lock (void)
	Lock the CMU to protect some of its registers against unintended modification.

uint32_t	CMU_Log2ToDiv (uint32_t log2)
	Convert logarithm of 2 prescaler to division factor.

void	CMU_Unlock (void)
	Unlock the CMU so that writing to locked registers again is possible.

CMU_HFRCOFreq_TypeDef	CMU_HFRCOFreqGet (void)
	Get the current HFRCO frequency.

void	CMU_HFRCOFreqSet ( CMU_HFRCOFreq_TypeDef setFreq)
	Set HFRCO calibration for the selected target frequency.

CMU_AUXHFRCOFreq_TypeDef	CMU_AUXHFRCOFreqGet (void)
	Get the current AUXHFRCO frequency.

void	CMU_AUXHFRCOFreqSet ( CMU_AUXHFRCOFreq_TypeDef setFreq)
	Set AUXHFRCO calibration for the selected target frequency.

uint32_t	CMU_PrescToLog2 (uint32_t presc)
	Convert prescaler dividend to a logarithmic value.

uint32_t	getHfxoTuningMode (void)
	Get the HFXO tuning mode.

void	setHfxoTuningMode (uint32_t mode)
	Set the HFXO tuning mode.

void	syncReg (uint32_t mask)
	Wait for an ongoing sync of register(s) to low-frequency domain to complete.

Macros
#define	cmuClkDiv_1 1
	Clock divisors.

#define	cmuClkDiv_2 2
	Divide clock by 2.

#define	cmuClkDiv_4 4
	Divide clock by 4.

#define	cmuClkDiv_8 8
	Divide clock by 8.

#define	cmuClkDiv_16 16
	Divide clock by 16.

#define	cmuClkDiv_32 32
	Divide clock by 32.

#define	cmuClkDiv_64 64
	Divide clock by 64.

#define	cmuClkDiv_128 128
	Divide clock by 128.

#define	cmuClkDiv_256 256
	Divide clock by 256.

#define	cmuClkDiv_512 512
	Divide clock by 512.

#define	cmuClkDiv_1024 1024
	Divide clock by 1024.

#define	cmuClkDiv_2048 2048
	Divide clock by 2048.

#define	cmuClkDiv_4096 4096
	Divide clock by 4096.

#define	cmuClkDiv_8192 8192
	Divide clock by 8192.

#define	cmuClkDiv_16384 16384
	Divide clock by 16384.

#define	cmuClkDiv_32768 32768
	Divide clock by 32768.

#define	CMU_HFRCO_MIN cmuHFRCOFreq_1M0Hz
	HFRCO minimum frequency.

#define	CMU_HFRCO_MAX cmuHFRCOFreq_38M0Hz
	HFRCO maximum frequency.

#define	CMU_AUXHFRCO_MIN cmuAUXHFRCOFreq_1M0Hz
	AUXHFRCO minimum frequency.

#define	CMU_AUXHFRCO_MAX cmuAUXHFRCOFreq_38M0Hz
	AUXHFRCO maximum frequency.

#define	CMU_LFXOINIT_DEFAULT
	Default LFXO initialization values.

#define	CMU_LFXOINIT_EXTERNAL_CLOCK
	Default LFXO initialization for external clock.

#define	CMU_HFXOINIT_DEFAULT
	Default HFXO initialization values for Platform 2 devices, which contain a separate HFXOCTRL register.

#define	CMU_HFXOINIT_EXTERNAL_CLOCK
	Init of HFXO with external clock.

#define	CMU_DPLL_LFXO_TO_40MHZ
	DPLL initialization values for 39,998,805 Hz using LFXO as reference clock, M=2 and N=3661.

Typedefs
typedef uint32_t	CMU_ClkDiv_TypeDef
	Clock divider configuration.

typedef uint32_t	CMU_ClkPresc_TypeDef
	Clockprescaler configuration.

Enumerations
enum	CMU_HFRCOFreq_TypeDef { cmuHFRCOFreq_1M0Hz = 1000000U, cmuHFRCOFreq_2M0Hz = 2000000U, cmuHFRCOFreq_4M0Hz = 4000000U, cmuHFRCOFreq_7M0Hz = 7000000U, cmuHFRCOFreq_13M0Hz = 13000000U, cmuHFRCOFreq_16M0Hz = 16000000U, cmuHFRCOFreq_19M0Hz = 19000000U, cmuHFRCOFreq_26M0Hz = 26000000U, cmuHFRCOFreq_32M0Hz = 32000000U, cmuHFRCOFreq_38M0Hz = 38000000U, cmuHFRCOFreq_UserDefined = 0 }
	High-frequency system RCO bands.

enum	CMU_AUXHFRCOFreq_TypeDef { cmuAUXHFRCOFreq_1M0Hz = 1000000U, cmuAUXHFRCOFreq_2M0Hz = 2000000U, cmuAUXHFRCOFreq_4M0Hz = 4000000U, cmuAUXHFRCOFreq_7M0Hz = 7000000U, cmuAUXHFRCOFreq_13M0Hz = 13000000U, cmuAUXHFRCOFreq_16M0Hz = 16000000U, cmuAUXHFRCOFreq_19M0Hz = 19000000U, cmuAUXHFRCOFreq_26M0Hz = 26000000U, cmuAUXHFRCOFreq_32M0Hz = 32000000U, cmuAUXHFRCOFreq_38M0Hz = 38000000U, cmuAUXHFRCOFreq_UserDefined = 0 }
	AUX high-frequency RCO bands.

enum	CMU_Clock_TypeDef { cmuClock_HF , cmuClock_DBG , cmuClock_AUX , cmuClock_EXPORT , cmuClock_BUS , cmuClock_CRYPTO , cmuClock_CRYPTO0 , cmuClock_CRYPTO1 , cmuClock_LDMA , cmuClock_GPCRC , cmuClock_GPIO , cmuClock_HFLE , cmuClock_PRS , cmuClock_HFPER , cmuClock_USART0 , cmuClock_USART1 , cmuClock_USART2 , cmuClock_TIMER0 , cmuClock_TIMER1 , cmuClock_WTIMER0 , cmuClock_CRYOTIMER , cmuClock_ACMP0 , cmuClock_ACMP1 , cmuClock_VDAC0 , cmuClock_IDAC0 , cmuClock_ADC0 , cmuClock_I2C0 , cmuClock_I2C1 , cmuClock_CSEN_HF , cmuClock_TRNG0 , cmuClock_CORE , cmuClock_LFA , cmuClock_LETIMER0 , cmuClock_PCNT0 , cmuClock_LESENSE , cmuClock_LFB , cmuClock_LEUART0 , cmuClock_CSEN_LF , cmuClock_SYSTICK , cmuClock_LFE , cmuClock_RTCC , cmuClock_ADC0ASYNC }
	Clock points in CMU.

enum	CMU_Osc_TypeDef { cmuOsc_LFXO , cmuOsc_LFRCO , cmuOsc_HFXO , cmuOsc_HFRCO , cmuOsc_AUXHFRCO , cmuOsc_ULFRCO , cmuOsc_CLKIN0 }
	Oscillator types.

enum	CMU_OscMode_TypeDef { cmuOscMode_Crystal , cmuOscMode_AcCoupled , cmuOscMode_External }
	Oscillator modes.

enum	CMU_Select_TypeDef { cmuSelect_Error , cmuSelect_Disabled , cmuSelect_LFXO , cmuSelect_LFRCO , cmuSelect_HFXO , cmuSelect_HFRCO , cmuSelect_HFCLKLE , cmuSelect_AUXHFRCO , cmuSelect_HFSRCCLK , cmuSelect_HFCLK , cmuSelect_ULFRCO , cmuSelect_HFRCODIV2 , cmuSelect_CLKIN0 }
	Selectable clock sources.

enum	CMU_HFXOTuningMode_TypeDef { cmuHFXOTuningMode_Auto = 0, cmuHFXOTuningMode_PeakDetectCommand = CMU_CMD_HFXOPEAKDETSTART, cmuHFXOTuningMode_ShuntCommand = CMU_CMD_HFXOSHUNTOPTSTART, cmuHFXOTuningMode_PeakShuntCommand }
	HFXO tuning modes.

enum	CMU_DPLLClkSel_TypeDef { cmuDPLLClkSel_Hfxo = _CMU_DPLLCTRL_REFSEL_HFXO, cmuDPLLClkSel_Lfxo = _CMU_DPLLCTRL_REFSEL_LFXO, cmuDPLLClkSel_Clkin0 = _CMU_DPLLCTRL_REFSEL_CLKIN0 }
	DPLL reference clock selector.

enum	CMU_DPLLEdgeSel_TypeDef { cmuDPLLEdgeSel_Fall = _CMU_DPLLCTRL_EDGESEL_FALL, cmuDPLLEdgeSel_Rise = _CMU_DPLLCTRL_EDGESEL_RISE }
	DPLL reference clock edge detect selector.

enum	CMU_DPLLLockMode_TypeDef { cmuDPLLLockMode_Freq = _CMU_DPLLCTRL_MODE_FREQLL, cmuDPLLLockMode_Phase = _CMU_DPLLCTRL_MODE_PHASELL }
	DPLL lock mode selector.

Function Documentation

◆ CMU_AUXHFRCOBandGet()

CMU_AUXHFRCOFreq_TypeDef CMU_AUXHFRCOBandGet ( void )

Get the current AUXHFRCO frequency.

Returns: AUXHFRCO frequency.

◆ CMU_AUXHFRCOBandSet()

void CMU_AUXHFRCOBandSet ( CMU_AUXHFRCOFreq_TypeDef setFreq )

Set AUXHFRCO calibration for the selected target frequency.

Parameters

[in] setFreq AUXHFRCO frequency to set

◆ CMU_Calibrate()

uint32_t CMU_Calibrate	(	uint32_t	`HFCycles,`
		CMU_Osc_TypeDef	`reference`
	)

Calibrate the clock.

Run a calibration for HFCLK against a selectable reference clock. See the reference manual, CMU chapter, for more details.

Note: This function will not return until the calibration measurement is completed.

Parameters

[in]	`HFCycles`	The number of HFCLK cycles to run the calibration. Increasing this number increases precision but the calibration will take more time.
[in]	`reference`	The reference clock used to compare HFCLK.

Returns: The number of ticks the reference clock after HFCycles ticks on the HF clock.

◆ CMU_CalibrateConfig()

void CMU_CalibrateConfig	(	uint32_t	`downCycles,`
		CMU_Osc_TypeDef	`downSel,`
		CMU_Osc_TypeDef	`upSel`
	)

Configure the clock calibration.

Configure a calibration for a selectable clock source against another selectable reference clock. See the reference manual, CMU chapter, for more details.

Note: After configuration, a call to CMU_CalibrateStart() is required and the resulting calibration value can be read out with the CMU_CalibrateCountGet() function call.

Parameters

[in]	`downCycles`	The number of downSel clock cycles to run the calibration. Increasing this number increases precision but the calibration will take more time.
[in]	`downSel`	The clock, which will be counted down downCycles.
[in]	`upSel`	The reference clock; the number of cycles generated by this clock will be counted and added up and the result can be given with the CMU_CalibrateCountGet() function call.

◆ CMU_CalibrateCountGet()

uint32_t CMU_CalibrateCountGet ( void )

Get the calibration count register.

Note: If continuous calibration mode is active, calibration busy will almost always be off and only the value needs to be read. In a normal case, this function call is triggered by the CALRDY interrupt flag.

Returns: The calibration count, the number of UPSEL clocks in the period of DOWNSEL oscillator clock cycles configured by a previous write operation to CMU->CALCNT.

◆ CMU_ClockEnable()

void CMU_ClockEnable	(	CMU_Clock_TypeDef	`clock,`
		bool	`enable`
	)

Enable/disable a clock.

In general, module clocking is disabled after a reset. If a module clock is disabled, the registers of that module are not accessible and reading from such registers may return undefined values. Writing to registers of clock-disabled modules has no effect. Avoid accessing module registers of a module with a disabled clock.

Note: If enabling/disabling an LF clock, synchronization into the low-frequency domain is required. If the same register is modified before a previous update has completed, this function will stall until the previous synchronization has completed. See CMU_FreezeEnable() for a suggestion on how to reduce the stalling time in some use cases.

HFCLKLE prescaler is automatically modified when peripherals with clock domain HFBUSCLK is chosen based on the maximum HFLE frequency allowed.

Parameters

[in]	`clock`	The clock to enable/disable. Notice that not all defined clock points have separate enable/disable control. See the CMU overview in the reference manual.
[in]	`enable`	true - enable specified clock. false - disable specified clock.

◆ CMU_ClockDivGet()

CMU_ClkDiv_TypeDef CMU_ClockDivGet ( CMU_Clock_TypeDef clock )

Get the clock divisor/prescaler.

Parameters

[in] clock A clock point to get the divisor/prescaler for. Notice that not all clock points have a divisor/prescaler. See the CMU overview in the reference manual.

Returns: The current clock point divisor/prescaler. 1 is returned if clock specifies a clock point without a divisor/prescaler.

◆ CMU_ClockDivSet()

void CMU_ClockDivSet	(	CMU_Clock_TypeDef	`clock,`
		CMU_ClkDiv_TypeDef	`div`
	)

Set the clock divisor/prescaler.

Note: If setting an LF clock prescaler, synchronization into the low-frequency domain is required. If the same register is modified before a previous update has completed, this function will stall until the previous synchronization has completed. See CMU_FreezeEnable() for a suggestion on how to reduce the stalling time in some use cases.

HFCLKLE prescaler is automatically modified when peripherals with clock domain HFBUSCLK is chosen based on the maximum HFLE frequency allowed.

Parameters

[in]	`clock`	Clock point to set divisor/prescaler for. Notice that not all clock points have a divisor/prescaler. See the CMU overview in the reference manual.
[in]	`div`	The clock divisor to use (<= cmuClkDiv_512).

◆ CMU_ClockFreqGet()

uint32_t CMU_ClockFreqGet ( CMU_Clock_TypeDef clock )

Get the clock frequency for a clock point.

Parameters

[in] clock A clock point to fetch the frequency for.

Returns: The current frequency in Hz.

◆ CMU_ClockPrescSet()

void CMU_ClockPrescSet	(	CMU_Clock_TypeDef	`clock,`
		CMU_ClkPresc_TypeDef	`presc`
	)

Set the clock prescaler.

Note: If setting an LF clock prescaler, synchronization into the low-frequency domain is required. If the same register is modified before a previous update has completed, this function will stall until the previous synchronization has completed. See CMU_FreezeEnable() for a suggestion on how to reduce the stalling time in some use cases.

HFCLKLE prescaler is automatically modified when peripherals with clock domain HFBUSCLK is chosen based on the maximum HFLE frequency allowed.

Parameters

[in]	`clock`	A clock point to set the prescaler for. Notice that not all clock points have a prescaler. See the CMU overview in the reference manual.
[in]	`presc`	The clock prescaler.

◆ CMU_ClockPrescGet()

uint32_t CMU_ClockPrescGet ( CMU_Clock_TypeDef clock )

Get the clock prescaler.

Parameters

[in] clock A clock point to get the prescaler for. Notice that not all clock points have a prescaler. See the CMU overview in the reference manual.

Returns: The prescaler value of the current clock point. 0 is returned if clock specifies a clock point without a prescaler.

◆ CMU_ClockSelectSet()

void CMU_ClockSelectSet	(	CMU_Clock_TypeDef	`clock,`
		CMU_Select_TypeDef	`ref`
	)

Select the reference clock/oscillator used for a clock branch.

Notice that if a selected reference is not enabled prior to selecting its use, it will be enabled and this function will wait for the selected oscillator to be stable. It will however NOT be disabled if another reference clock is selected later.

This feature is particularly important if selecting a new reference clock for the clock branch clocking the core. Otherwise, the system may halt.

Note: HFCLKLE prescaler is automatically modified when peripherals with clock domain HFBUSCLK is chosen based on the maximum HFLE frequency allowed.

Parameters

[in]	`clock`	A clock branch to select reference clock for. One of: cmuClock_HF cmuClock_LFA cmuClock_LFB cmuClock_DBG
[in]	`ref`	A reference selected for clocking. See the reference manual for details about references available for a specific clock branch. cmuSelect_HFRCO cmuSelect_LFRCO cmuSelect_HFXO cmuSelect_LFXO cmuSelect_HFCLKLE cmuSelect_AUXHFRCO cmuSelect_HFCLK cmuSelect_ULFRCO

◆ CMU_ClockSelectGet()

CMU_Select_TypeDef CMU_ClockSelectGet ( CMU_Clock_TypeDef clock )

Get the currently selected reference clock used for a clock branch.

Parameters

[in]


              clock

Clock branch to fetch selected ref. clock for. One of:

Returns: The reference clock used for clocking the selected branch, cmuSelect_Error if invalid clock provided.

◆ CMU_LF_ClockPrecisionGet()

uint16_t CMU_LF_ClockPrecisionGet ( CMU_Clock_TypeDef clock )

Gets the precision (in PPM) of the specified low frequency clock branch.

Parameters

[in] clock Clock branch.

Returns: Precision, in PPM, of the specified clock branch.

Note: This function is only for internal usage.; The current implementation of this function is used to determine if the clock has a precision <= 500 ppm or not (which is the minimum required for BLE). Future version of this function should provide more accurate precision numbers to allow for further optimizations from the stacks.

◆ CMU_DPLLLock()

bool CMU_DPLLLock ( const CMU_DPLLInit_TypeDef * init )

Lock the DPLL to a given frequency.

The frequency is given by: Fout = Fref * (N+1) / (M+1).

Note: This function does not check if the given N & M values will actually produce the desired target frequency.
N & M limitations:
300 < N <= 4095
0 <= M <= 4095
Any peripheral running off HFRCO should be switched to HFRCODIV2 prior to calling this function to avoid over-clocking.

HFCLKLE prescaler is automatically modified before updating HFRCO based on the maximum HFLE frequency allowed.

Parameters

[in] init DPLL setup parameters.

Returns: Returns false on invalid target frequency or DPLL locking error.

◆ CMU_FreezeEnable()

void CMU_FreezeEnable ( bool enable )

CMU low frequency register synchronization freeze control.

Some CMU registers require synchronization into the low-frequency (LF) domain. The freeze feature allows for several such registers to be modified before passing them to the LF domain simultaneously (which takes place when the freeze mode is disabled).

Another use case for this feature is using an API (such as the CMU API) for modifying several bit fields consecutively in the same register. If freeze mode is enabled during this sequence, stalling can be avoided.

Note: When enabling freeze mode, this function will wait for all current ongoing CMU synchronization to LF domain to complete (normally synchronization will not be in progress.) However, for this reason, when using freeze mode, modifications of registers requiring LF synchronization should be done within one freeze enable/disable block to avoid unnecessary stalling.

Parameters

[in]


              enable

true - enable freeze, modified registers are not propagated to the LF domain
false - disable freeze, modified registers are propagated to the LF domain

◆ CMU_HFRCOBandGet()

CMU_HFRCOFreq_TypeDef CMU_HFRCOBandGet ( void )

Get the current HFRCO frequency.

Returns: HFRCO frequency.

◆ CMU_HFRCOBandSet()

void CMU_HFRCOBandSet ( CMU_HFRCOFreq_TypeDef setFreq )

Set the HFRCO calibration for the selected target frequency.

Note: HFCLKLE prescaler is automatically modified based on the maximum HFLE frequency allowed.

Parameters

[in] setFreq HFRCO frequency to set.

◆ CMU_HFXOAutostartEnable()

void CMU_HFXOAutostartEnable	(	uint32_t	`userSel,`
		bool	`enEM0EM1Start,`
		bool	`enEM0EM1StartSel`
	)

Enable or disable HFXO autostart.

Parameters

[in]	`userSel`	Additional user specified enable bit.
[in]	`enEM0EM1Start`	If true, HFXO is automatically started upon entering EM0/EM1 entry from EM2/EM3. HFXO selection has to be handled by the user. If false, HFXO is not started automatically when entering EM0/EM1.
[in]	`enEM0EM1StartSel`	If true, HFXO is automatically started and immediately selected upon entering EM0/EM1 entry from EM2/EM3. Note that this option stalls the use of HFSRCCLK until HFXO becomes ready. HFCLKLE prescaler is also automatically modified if userSel is specified. If false, HFXO is not started or selected automatically when entering EM0/EM1.

◆ CMU_HFXOInit()

void CMU_HFXOInit ( const CMU_HFXOInit_TypeDef * hfxoInit )

Set HFXO control registers.

Note: HFXO configuration should be obtained from a configuration tool, app note, or xtal data sheet. This function disables the HFXO to ensure a valid state before update.

Parameters

[in] hfxoInit HFXO setup parameters.

◆ CMU_LCDClkFDIVGet()

uint32_t CMU_LCDClkFDIVGet ( void )

Get the LCD framerate divisor (FDIV) setting.

Returns: The LCD framerate divisor.

◆ CMU_LCDClkFDIVSet()

void CMU_LCDClkFDIVSet ( uint32_t div )

Set the LCD framerate divisor (FDIV) setting.

Note: The FDIV field (CMU LCDCTRL register) should only be modified while the LCD module is clock disabled (CMU LFACLKEN0.LCD bit is 0). This function will NOT modify FDIV if the LCD module clock is enabled. See CMU_ClockEnable() for disabling/enabling LCD clock.

Parameters

[in] div The FDIV setting to use.

◆ CMU_LFXOInit()

void CMU_LFXOInit ( const CMU_LFXOInit_TypeDef * lfxoInit )

Set LFXO control registers.

Note: LFXO configuration should be obtained from a configuration tool, app note, or xtal data sheet. This function disables the LFXO when necessary to ensure a valid state before update.

Parameters

[in] lfxoInit LFXO setup parameters.

◆ CMU_LFXOPrecisionSet()

void CMU_LFXOPrecisionSet ( uint16_t precision )

Sets LFXO's crystal precision, in PPM.

Note: LFXO precision should be obtained from a xtal datasheet.

Parameters

[in] precision LFXO's crystal precision, in PPM.

◆ CMU_OscillatorEnable()

void CMU_OscillatorEnable	(	CMU_Osc_TypeDef	`osc,`
		bool	`enable,`
		bool	`wait`
	)

Enable/disable oscillator.

Note: WARNING: When this function is called to disable either cmuOsc_LFXO or cmuOsc_HFXO, the LFXOMODE or HFXOMODE fields of the CMU_CTRL register are reset to the reset value. In other words, if external clock sources are selected in either LFXOMODE or HFXOMODE fields, the configuration will be cleared and needs to be reconfigured if needed later.

Parameters

[in]	`osc`	The oscillator to enable/disable.
[in]	`enable`	true - enable specified oscillator. false - disable specified oscillator.
[in]	`wait`	Only used if `enable` is true. true - wait for oscillator start-up time to timeout before returning. false - do not wait for oscillator start-up time to timeout before returning.

◆ CMU_OscillatorTuningGet()

uint32_t CMU_OscillatorTuningGet ( CMU_Osc_TypeDef osc )

Get the oscillator frequency tuning setting.

Parameters

[in]

osc

An oscillator to get tuning value for, one of the following:

cmuOsc_LFRCO
cmuOsc_HFRCO
cmuOsc_AUXHFRCO
cmuOsc_HFXO if CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE is defined

Returns: The oscillator frequency tuning setting in use.

◆ CMU_OscillatorTuningSet()

void CMU_OscillatorTuningSet	(	CMU_Osc_TypeDef	`osc,`
		uint32_t	`val`
	)

Set the oscillator frequency tuning control.

Note: Oscillator tuning is done during production and the tuning value is automatically loaded after reset. Changing the tuning value from the calibrated value is for more advanced use. Certain oscillators also have build-in tuning optimization.

Parameters

[in]	`osc`	An oscillator to set tuning value for, one of the following: cmuOsc_LFRCO cmuOsc_HFRCO cmuOsc_AUXHFRCO cmuOsc_HFXO if PEAKDETSHUNTOPTMODE is available. Note that CMD mode is set.
[in]	`val`	The oscillator frequency tuning setting to use.

◆ CMU_OscillatorTuningWait()

bool CMU_OscillatorTuningWait	(	CMU_Osc_TypeDef	`osc,`
		CMU_HFXOTuningMode_TypeDef	`mode`
	)

Wait for the oscillator tuning optimization.

Parameters

[in]	`osc`	An oscillator to set tuning value for, one of the following: cmuOsc_HFXO
[in]	`mode`	Tuning optimization mode.

Returns: Returns false on invalid parameters or oscillator error status.

◆ CMU_OscillatorTuningOptimize()

bool CMU_OscillatorTuningOptimize	(	CMU_Osc_TypeDef	`osc,`
		CMU_HFXOTuningMode_TypeDef	`mode,`
		bool	`wait`
	)

Start and optionally wait for the oscillator tuning optimization.

Parameters

[in]	`osc`	An oscillator to set tuning value for, one of the following: cmuOsc_HFXO
[in]	`mode`	Tuning optimization mode.
[in]	`wait`	Wait for tuning optimization to complete. true - wait for tuning optimization to complete. false - return without waiting.

Returns: Returns false on invalid parameters or oscillator error status.

◆ CMU_PCNTClockExternalSet()

void CMU_PCNTClockExternalSet	(	unsigned int	`instance,`
		bool	`external`
	)

Select the PCNTn clock.

Parameters

[in]	`instance`	PCNT instance number to set selected clock source for.
[in]	`external`	Set to true to select the external clock, false to select LFBCLK.

◆ CMU_PCNTClockExternalGet()

bool CMU_PCNTClockExternalGet ( unsigned int instance )

Determine if the currently selected PCNTn clock used is external or LFBCLK.

Parameters

[in] instance PCNT instance number to get currently selected clock source for.

Returns

true - selected clock is external clock.
false - selected clock is LFBCLK.

◆ CMU_UpdateWaitStates()

void CMU_UpdateWaitStates	(	uint32_t	`freq,`
		int	`vscale`
	)

Configure various wait states to switch to a certain frequency and a certain voltage scale.

This function will set up the necessary flash, bus, and RAM wait states. Updating the wait state configuration must be done before increasing the clock frequency and it must be done after decreasing the clock frequency. Updating the wait state configuration must be done before core voltage is decreased and it must be done after a core voltage is increased.

Parameters

[in]	`freq`	The core clock frequency to configure wait-states.
[in]	`vscale`	The voltage scale to configure wait-states. Expected values are 0 or 2, higher number is lower voltage.

0 = 1.2 V (VSCALE2)
2 = 1.0 V (VSCALE0)

◆ CMU_CalibrateCont()

void CMU_CalibrateCont ( bool enable )

inline

Configure continuous calibration mode.

Parameters

[in] enable If true, enables continuous calibration, if false disables continuous calibration.

◆ CMU_CalibrateStart()

void CMU_CalibrateStart ( void )

inline

Start calibration.

Note: This call is usually invoked after CMU_CalibrateConfig() and possibly CMU_CalibrateCont() .

◆ CMU_CalibrateStop()

void CMU_CalibrateStop ( void )

inline

Stop the calibration counters.

◆ CMU_DivToLog2()

uint32_t CMU_DivToLog2 ( CMU_ClkDiv_TypeDef div )

inline

Convert dividend to logarithmic value.

It only works for even numbers equal to 2^n.

Parameters

[in] div An unscaled dividend.

Returns: Logarithm of 2, as used by fixed prescalers.

◆ CMU_DPLLUnlock()

void CMU_DPLLUnlock ( void )

inline

Unlock DPLL.

Note: HFRCO is not turned off.

◆ CMU_IntClear()

void CMU_IntClear ( uint32_t flags )

inline

Clear one or more pending CMU interrupts.

Parameters

[in] flags CMU interrupt sources to clear.

◆ CMU_IntDisable()

void CMU_IntDisable ( uint32_t flags )

inline

Disable one or more CMU interrupts.

Parameters

[in] flags CMU interrupt sources to disable.

◆ CMU_IntEnable()

void CMU_IntEnable ( uint32_t flags )

inline

Enable one or more CMU interrupts.

Note: Depending on use case, a pending interrupt may already be set prior to enabling the interrupt. Consider using CMU_IntClear() prior to enabling if the pending interrupt should be ignored.

Parameters

[in] flags CMU interrupt sources to enable.

◆ CMU_IntGet()

uint32_t CMU_IntGet ( void )

inline

Get pending CMU interrupts.

Returns: CMU interrupt sources pending.

◆ CMU_IntGetEnabled()

uint32_t CMU_IntGetEnabled ( void )

inline

Get enabled and pending CMU interrupt flags.

Useful for handling more interrupt sources in the same interrupt handler.

Note: This function does not clear event bits.

Returns

Pending and enabled CMU interrupt sources. The return value is the bitwise AND of

the enabled interrupt sources in CMU_IEN and
the pending interrupt flags CMU_IF

◆ CMU_IntSet()

void CMU_IntSet ( uint32_t flags )

inline

Set one or more pending CMU interrupts.

Parameters

[in] flags CMU interrupt sources to set to pending.

◆ CMU_Lock()

void CMU_Lock ( void )

inline

Lock the CMU to protect some of its registers against unintended modification.

See the reference manual for CMU registers that will be locked.

Note: If locking the CMU registers, they must be unlocked prior to using any CMU API functions modifying CMU registers protected by the lock.

◆ CMU_Log2ToDiv()

uint32_t CMU_Log2ToDiv ( uint32_t log2 )

inline

Convert logarithm of 2 prescaler to division factor.

Parameters

[in] log2 Logarithm of 2, as used by fixed prescalers.

Returns: Dividend.

◆ CMU_Unlock()

void CMU_Unlock ( void )

inline

Unlock the CMU so that writing to locked registers again is possible.

◆ CMU_HFRCOFreqGet()

CMU_HFRCOFreq_TypeDef CMU_HFRCOFreqGet ( void )

inline

Get the current HFRCO frequency.

Returns: HFRCO frequency.

◆ CMU_HFRCOFreqSet()

void CMU_HFRCOFreqSet ( CMU_HFRCOFreq_TypeDef setFreq )

inline

Set HFRCO calibration for the selected target frequency.

Parameters

[in] setFreq HFRCO frequency to set.

◆ CMU_AUXHFRCOFreqGet()

CMU_AUXHFRCOFreq_TypeDef CMU_AUXHFRCOFreqGet ( void )

inline

Get the current AUXHFRCO frequency.

Returns: AUXHFRCO frequency.

◆ CMU_AUXHFRCOFreqSet()

void CMU_AUXHFRCOFreqSet ( CMU_AUXHFRCOFreq_TypeDef setFreq )

inline

Set AUXHFRCO calibration for the selected target frequency.

Parameters

[in] setFreq AUXHFRCO frequency to set.

◆ CMU_PrescToLog2()

uint32_t CMU_PrescToLog2 ( uint32_t presc )

inline

Convert prescaler dividend to a logarithmic value.

It only works for even numbers equal to 2^n.

Parameters

[in] presc An unscaled dividend (dividend = presc + 1).

Returns: Logarithm of 2, as used by fixed 2^n prescalers.

◆ getHfxoTuningMode()

uint32_t getHfxoTuningMode ( void )

inline

Get the HFXO tuning mode.

Returns: The current HFXO tuning mode from the HFXOCTRL register.

◆ setHfxoTuningMode()

void setHfxoTuningMode ( uint32_t mode )

inline

Set the HFXO tuning mode.

Parameters

[in] mode The new HFXO tuning mode. This can be HFXO_TUNING_MODE_AUTO or HFXO_TUNING_MODE_CMD.

◆ syncReg()

void syncReg ( uint32_t mask )

inline

Wait for an ongoing sync of register(s) to low-frequency domain to complete.

Parameters

[in] mask A bitmask corresponding to SYNCBUSY register defined bits, indicating registers that must complete any ongoing synchronization.

Macro Definition Documentation

◆ cmuClkDiv_1

#define cmuClkDiv_1 1

Clock divisors.

These values are valid for prescalers. Divide clock by 1.

◆ cmuClkDiv_2

#define cmuClkDiv_2 2

Divide clock by 2.

◆ cmuClkDiv_4

#define cmuClkDiv_4 4

Divide clock by 4.

◆ cmuClkDiv_8

#define cmuClkDiv_8 8

Divide clock by 8.

◆ cmuClkDiv_16

#define cmuClkDiv_16 16

Divide clock by 16.

◆ cmuClkDiv_32

#define cmuClkDiv_32 32

Divide clock by 32.

◆ cmuClkDiv_64

#define cmuClkDiv_64 64

Divide clock by 64.

◆ cmuClkDiv_128

#define cmuClkDiv_128 128

Divide clock by 128.

◆ cmuClkDiv_256

#define cmuClkDiv_256 256

Divide clock by 256.

◆ cmuClkDiv_512

#define cmuClkDiv_512 512

Divide clock by 512.

◆ cmuClkDiv_1024

#define cmuClkDiv_1024 1024

Divide clock by 1024.

◆ cmuClkDiv_2048

#define cmuClkDiv_2048 2048

Divide clock by 2048.

◆ cmuClkDiv_4096

#define cmuClkDiv_4096 4096

Divide clock by 4096.

◆ cmuClkDiv_8192

#define cmuClkDiv_8192 8192

Divide clock by 8192.

◆ cmuClkDiv_16384

#define cmuClkDiv_16384 16384

Divide clock by 16384.

◆ cmuClkDiv_32768

#define cmuClkDiv_32768 32768

Divide clock by 32768.

◆ CMU_HFRCO_MIN

#define CMU_HFRCO_MIN cmuHFRCOFreq_1M0Hz

HFRCO minimum frequency.

◆ CMU_HFRCO_MAX

#define CMU_HFRCO_MAX cmuHFRCOFreq_38M0Hz

HFRCO maximum frequency.

◆ CMU_AUXHFRCO_MIN

#define CMU_AUXHFRCO_MIN cmuAUXHFRCOFreq_1M0Hz

AUXHFRCO minimum frequency.

◆ CMU_AUXHFRCO_MAX

#define CMU_AUXHFRCO_MAX cmuAUXHFRCOFreq_38M0Hz

AUXHFRCO maximum frequency.

◆ CMU_LFXOINIT_DEFAULT

#define CMU_LFXOINIT_DEFAULT

Value:

         {                                                                           \
        
         _CMU_LFXOCTRL_TUNING_DEFAULT,
         
          /* Default CTUNE value, 0 */
         
         \
        
         _CMU_LFXOCTRL_GAIN_DEFAULT,
         
          /* Default gain, 2 */
         
         \
        
         _CMU_LFXOCTRL_TIMEOUT_DEFAULT,
         
          /* Default start-up delay, 32 K cycles */
         
         \
        
         cmuOscMode_Crystal,
         
          /* Crystal oscillator */
         
         \
        
         }

Default LFXO initialization values.

◆ CMU_LFXOINIT_EXTERNAL_CLOCK

#define CMU_LFXOINIT_EXTERNAL_CLOCK

Value:

         {                                                                             \
        
         0,
         
          /* No CTUNE value needed */
         
         \
        
         0,
         
          /* No LFXO startup gain */
         
         \
        
         _CMU_LFXOCTRL_TIMEOUT_2CYCLES,
         
          /* Minimal lfxo start-up delay, 2 cycles */
         
         \
        
         cmuOscMode_External,
         
          /* External digital clock */
         
         \
        
         }

Default LFXO initialization for external clock.

◆ CMU_HFXOINIT_DEFAULT

#define CMU_HFXOINIT_DEFAULT

Value:

         {                                                                 \
        
         false,
         
          /* Low-noise mode for EFR32 */
         
         \
        
         false,
         
          /* @deprecated no longer in use */
         
         \
        
         false,
         
          /* @deprecated no longer in use */
         
         \
        
         false,
         
          /* @deprecated no longer in use */
         
         \
        
         _CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT,                             \
        
         _CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT,                         \
        
         0xA,
         
          /* Default Shunt steady-state current */
         
         \
        
         0x20,
         
          /* Matching errata fix in @ref CHIP_Init() */
         
         \
        
         0x7,
         
          /* Recommended steady-state XO core bias current */
         
         \
        
         0x6,
         
          /* Recommended peak detection threshold */
         
         \
        
         0x2,
         
          /* Recommended shunt optimization timeout */
         
         \
        
         0xA,
         
          /* Recommended peak detection timeout  */
         
         \
        
         0x4,
         
          /* Recommended steady timeout */
         
         \
        
         _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT,                    \
        
         cmuOscMode_Crystal,                                             \
        
         }

Default HFXO initialization values for Platform 2 devices, which contain a separate HFXOCTRL register.

◆ CMU_HFXOINIT_EXTERNAL_CLOCK

#define CMU_HFXOINIT_EXTERNAL_CLOCK

Value:

         {                                                                            \
        
         true,
         
          /* Low-power mode */
         
         \
        
         false,
         
          /* @deprecated no longer in use */
         
         \
        
         false,
         
          /* @deprecated no longer in use */
         
         \
        
         false,
         
          /* @deprecated no longer in use */
         
         \
        
         0,
         
          /* Startup CTUNE=0 recommended for external clock */
         
         \
        
         0,
         
          /* Steady  CTUNE=0 recommended for external clock */
         
         \
        
         0xA,
         
          /* Default shunt steady-state current */
         
         \
        
         0,
         
          /* Startup IBTRIMXOCORE=0 recommended for external clock */
         
         \
        
         0,
         
          /* Steady  IBTRIMXOCORE=0 recommended for external clock */
         
         \
        
         0x6,
         
          /* Recommended peak detection threshold */
         
         \
        
         0x2,
         
          /* Recommended shunt optimization timeout */
         
         \
        
         0x0,
         
          /* Peak-detect not recommended for external clock usage */
         
         \
        
         _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES,
         
          /* Minimal steady timeout */
         
         \
        
         _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES,
         
          /* Minimal startup timeout */
         
         \
        
         cmuOscMode_External,                                                       \
        
         }

Init of HFXO with external clock.

◆ CMU_DPLL_LFXO_TO_40MHZ

#define CMU_DPLL_LFXO_TO_40MHZ

Value:

         {                                                                        \
        
         39998805,
         
          /* Target frequency.                  */
         
         \
        
         3661,
         
          /* Factor N.                          */
         
         \
        
         2,
         
          /* Factor M.                          */
         
         \
        
         0,
         
          /* No spread spectrum clocking.       */
         
         \
        
         0,
         
          /* No spread spectrum clocking.       */
         
         \
        
         cmuDPLLClkSel_Lfxo,
         
          /* Select LFXO as reference clock.    */
         
         \
        
         cmuDPLLEdgeSel_Fall,
         
          /* Select falling edge of ref clock.  */
         
         \
        
         cmuDPLLLockMode_Freq,
         
          /* Use frequency lock mode.           */
         
         \
        
         true
         
          /* Enable automatic lock recovery.    */
         
         \
        
         }

DPLL initialization values for 39,998,805 Hz using LFXO as reference clock, M=2 and N=3661.

Typedef Documentation

◆ CMU_ClkDiv_TypeDef

typedef uint32_t CMU_ClkDiv_TypeDef

Clock divider configuration.

◆ CMU_ClkPresc_TypeDef

typedef uint32_t CMU_ClkPresc_TypeDef

Clockprescaler configuration.

Enumeration Type Documentation

◆ CMU_HFRCOFreq_TypeDef

enum CMU_HFRCOFreq_TypeDef

High-frequency system RCO bands.

Enumerator
cmuHFRCOFreq_1M0Hz	1 MHz RC band
cmuHFRCOFreq_2M0Hz	2 MHz RC band
cmuHFRCOFreq_4M0Hz	4 MHz RC band
cmuHFRCOFreq_7M0Hz	7 MHz RC band
cmuHFRCOFreq_13M0Hz	13 MHz RC band
cmuHFRCOFreq_16M0Hz	16 MHz RC band
cmuHFRCOFreq_19M0Hz	19 MHz RC band
cmuHFRCOFreq_26M0Hz	26 MHz RC band
cmuHFRCOFreq_32M0Hz	32 MHz RC band
cmuHFRCOFreq_38M0Hz	38 MHz RC band

◆ CMU_AUXHFRCOFreq_TypeDef

enum CMU_AUXHFRCOFreq_TypeDef

AUX high-frequency RCO bands.

Enumerator
cmuAUXHFRCOFreq_1M0Hz	1 MHz RC band
cmuAUXHFRCOFreq_2M0Hz	2 MHz RC band
cmuAUXHFRCOFreq_4M0Hz	4 MHz RC band
cmuAUXHFRCOFreq_7M0Hz	7 MHz RC band
cmuAUXHFRCOFreq_13M0Hz	13 MHz RC band
cmuAUXHFRCOFreq_16M0Hz	16 MHz RC band
cmuAUXHFRCOFreq_19M0Hz	19 MHz RC band
cmuAUXHFRCOFreq_26M0Hz	26 MHz RC band
cmuAUXHFRCOFreq_32M0Hz	32 MHz RC band
cmuAUXHFRCOFreq_38M0Hz	38 MHz RC band

◆ CMU_Clock_TypeDef

enum CMU_Clock_TypeDef

Clock points in CMU.

See CMU overview in the reference manual.

Enumerator
cmuClock_HF	High-frequency clock.
cmuClock_DBG	Debug clock.
cmuClock_AUX	AUX clock.
cmuClock_EXPORT	Export clock.
cmuClock_BUS	High-frequency bus clock.
cmuClock_CRYPTO	Cryptography accelerator clock.
cmuClock_CRYPTO0	Cryptography accelerator 0 clock.
cmuClock_CRYPTO1	Cryptography accelerator 1 clock.
cmuClock_LDMA	Direct-memory access controller clock.
cmuClock_GPCRC	General-purpose cyclic redundancy checksum clock.
cmuClock_GPIO	General-purpose input/output clock.
cmuClock_HFLE	Low-energy clock divided down from HFCLK.
cmuClock_PRS	Peripheral reflex system clock.
cmuClock_HFPER	High-frequency peripheral clock.
cmuClock_USART0	Universal sync/async receiver/transmitter 0 clock.
cmuClock_USART1	Universal sync/async receiver/transmitter 1 clock.
cmuClock_USART2	Universal sync/async receiver/transmitter 2 clock.
cmuClock_TIMER0	Timer 0 clock.
cmuClock_TIMER1	Timer 1 clock.
cmuClock_WTIMER0	Wide-timer 0 clock.
cmuClock_CRYOTIMER	CRYOtimer clock.
cmuClock_ACMP0	Analog comparator 0 clock.
cmuClock_ACMP1	Analog comparator 1 clock.
cmuClock_VDAC0	Voltage digital-to-analog converter 0 clock.
cmuClock_IDAC0	Current digital-to-analog converter 0 clock.
cmuClock_ADC0	Analog-to-digital converter 0 clock.
cmuClock_I2C0	I2C 0 clock.
cmuClock_I2C1	I2C 1 clock.
cmuClock_CSEN_HF	Capacitive Sense HF clock.
cmuClock_TRNG0	True random number generator clock.
cmuClock_CORE	Core clock.
cmuClock_LFA	Low-frequency A clock.
cmuClock_LETIMER0	Low-energy timer 0 clock.
cmuClock_PCNT0	Pulse counter 0 clock.
cmuClock_LESENSE	LESENSE clock.
cmuClock_LFB	Low-frequency B clock.
cmuClock_LEUART0	Low-energy universal asynchronous receiver/transmitter 0 clock.
cmuClock_CSEN_LF	Capacitive Sense LF clock.
cmuClock_SYSTICK	Cortex SYSTICK LF clock.
cmuClock_LFE	Low-frequency E clock.
cmuClock_RTCC	Real-time counter and calendar clock.
cmuClock_ADC0ASYNC	ADC0 asynchronous clock.

◆ CMU_Osc_TypeDef

enum CMU_Osc_TypeDef

Oscillator types.

Enumerator
cmuOsc_LFXO	Low-frequency crystal oscillator.
cmuOsc_LFRCO	Low-frequency RC oscillator.
cmuOsc_HFXO	High-frequency crystal oscillator.
cmuOsc_HFRCO	High-frequency RC oscillator.
cmuOsc_AUXHFRCO	Auxiliary high-frequency RC oscillator.
cmuOsc_ULFRCO	Ultra low-frequency RC oscillator.
cmuOsc_CLKIN0	External oscillator.

◆ CMU_OscMode_TypeDef

enum CMU_OscMode_TypeDef

Oscillator modes.

Enumerator
cmuOscMode_Crystal	Crystal oscillator.
cmuOscMode_AcCoupled	AC-coupled buffer.
cmuOscMode_External	External digital clock.

◆ CMU_Select_TypeDef

enum CMU_Select_TypeDef

Selectable clock sources.

Enumerator
cmuSelect_Error	Usage error.
cmuSelect_Disabled	Clock selector disabled.
cmuSelect_LFXO	Low-frequency crystal oscillator.
cmuSelect_LFRCO	Low-frequency RC oscillator.
cmuSelect_HFXO	High-frequency crystal oscillator.
cmuSelect_HFRCO	High-frequency RC oscillator.
cmuSelect_HFCLKLE	High-frequency LE clock divided by 2 or 4.
cmuSelect_AUXHFRCO	Auxilliary clock source can be used for debug clock.
cmuSelect_HFSRCCLK	High-frequency source clock.
cmuSelect_HFCLK	Divided HFCLK on Giant for debug clock, undivided on Tiny Gecko and for USBC (not used on Gecko).
cmuSelect_ULFRCO	Ultra low-frequency RC oscillator.
cmuSelect_HFRCODIV2	High-frequency RC oscillator divided by 2.
cmuSelect_CLKIN0	External clock input.

◆ CMU_HFXOTuningMode_TypeDef

enum CMU_HFXOTuningMode_TypeDef

HFXO tuning modes.

Enumerator
cmuHFXOTuningMode_PeakDetectCommand	Run peak detect optimization only.
cmuHFXOTuningMode_ShuntCommand	Run shunt current optimization only.
cmuHFXOTuningMode_PeakShuntCommand	Run peak and shunt current optimization.

◆ CMU_DPLLClkSel_TypeDef

enum CMU_DPLLClkSel_TypeDef

DPLL reference clock selector.

Enumerator
cmuDPLLClkSel_Hfxo	HFXO is DPLL reference clock.
cmuDPLLClkSel_Lfxo	LFXO is DPLL reference clock.
cmuDPLLClkSel_Clkin0	CLKIN0 is DPLL reference clock.

◆ CMU_DPLLEdgeSel_TypeDef

enum CMU_DPLLEdgeSel_TypeDef

DPLL reference clock edge detect selector.

Enumerator
cmuDPLLEdgeSel_Fall	Detect falling edge of reference clock.
cmuDPLLEdgeSel_Rise	Detect rising edge of reference clock.

◆ CMU_DPLLLockMode_TypeDef

enum CMU_DPLLLockMode_TypeDef

DPLL lock mode selector.

Enumerator
cmuDPLLLockMode_Freq	Frequency lock mode.
cmuDPLLLockMode_Phase	Phase lock mode.

CMU - Clock Management Unit

Description

Data Structures

Functions

Macros

Typedefs

Enumerations

Function Documentation

◆ CMU_AUXHFRCOBandGet()

◆ CMU_AUXHFRCOBandSet()

◆ CMU_Calibrate()

◆ CMU_CalibrateConfig()

◆ CMU_CalibrateCountGet()

◆ CMU_ClockEnable()

◆ CMU_ClockDivGet()

◆ CMU_ClockDivSet()

◆ CMU_ClockFreqGet()

◆ CMU_ClockPrescSet()

◆ CMU_ClockPrescGet()

◆ CMU_ClockSelectSet()

◆ CMU_ClockSelectGet()

◆ CMU_LF_ClockPrecisionGet()

◆ CMU_DPLLLock()

◆ CMU_FreezeEnable()

◆ CMU_HFRCOBandGet()

◆ CMU_HFRCOBandSet()

◆ CMU_HFXOAutostartEnable()

◆ CMU_HFXOInit()

◆ CMU_LCDClkFDIVGet()

◆ CMU_LCDClkFDIVSet()

◆ CMU_LFXOInit()

◆ CMU_LFXOPrecisionSet()

◆ CMU_OscillatorEnable()

◆ CMU_OscillatorTuningGet()

◆ CMU_OscillatorTuningSet()

◆ CMU_OscillatorTuningWait()

◆ CMU_OscillatorTuningOptimize()

◆ CMU_PCNTClockExternalSet()

◆ CMU_PCNTClockExternalGet()

◆ CMU_UpdateWaitStates()

◆ CMU_CalibrateCont()

◆ CMU_CalibrateStart()

◆ CMU_CalibrateStop()

◆ CMU_DivToLog2()

◆ CMU_DPLLUnlock()

◆ CMU_IntClear()

◆ CMU_IntDisable()

◆ CMU_IntEnable()

◆ CMU_IntGet()

◆ CMU_IntGetEnabled()

◆ CMU_IntSet()

◆ CMU_Lock()

◆ CMU_Log2ToDiv()

◆ CMU_Unlock()

◆ CMU_HFRCOFreqGet()

◆ CMU_HFRCOFreqSet()

◆ CMU_AUXHFRCOFreqGet()

◆ CMU_AUXHFRCOFreqSet()

◆ CMU_PrescToLog2()

◆ getHfxoTuningMode()

◆ setHfxoTuningMode()

◆ syncReg()

Macro Definition Documentation

◆ cmuClkDiv_1

◆ cmuClkDiv_2

◆ cmuClkDiv_4

◆ cmuClkDiv_8

◆ cmuClkDiv_16

◆ cmuClkDiv_32

◆ cmuClkDiv_64

◆ cmuClkDiv_128

◆ cmuClkDiv_256

◆ cmuClkDiv_512

◆ cmuClkDiv_1024

◆ cmuClkDiv_2048

◆ cmuClkDiv_4096

◆ cmuClkDiv_8192

◆ cmuClkDiv_16384

◆ cmuClkDiv_32768

◆ CMU_HFRCO_MIN