cs_invert#

bool sl_hal_usart_async_init_t::cs_invert

Enable CS invert.

By default, chip select is active low. Set to true to make chip select active high.

auto_cs_enable#

bool sl_hal_usart_async_init_t::auto_cs_enable

Auto CS enabling.

prs_rx_enable#

bool sl_hal_usart_async_init_t::prs_rx_enable

Enable USART Rx via PRS.

prs_rx_channel#

uint8_t sl_hal_usart_async_init_t::prs_rx_channel

Select PRS channel for USART Rx. (Only valid if prs_rx_enable is true).

auto_cs_hold#

uint8_t sl_hal_usart_async_init_t::auto_cs_hold

Auto CS hold time in baud cycles.

auto_cs_setup#

uint8_t sl_hal_usart_async_init_t::auto_cs_setup

Auto CS setup time in baud cycles.

clock_div#

uint32_t sl_hal_usart_async_init_t::clock_div

Clock divider.

oversampling#

sl_hal_usart_ovs_t sl_hal_usart_async_init_t::oversampling

Oversampling used.

data_bits#

sl_hal_usart_data_bits_t sl_hal_usart_async_init_t::data_bits

Number of data bits in frame.

Notice that UART modules only support 8 or 9 data bits.

parity#

sl_hal_usart_parity_t sl_hal_usart_async_init_t::parity

Parity mode to use.

stop_bits#

sl_hal_usart_stop_bits_t sl_hal_usart_async_init_t::stop_bits

Number of stop bits to use.

majority_vote#

sl_hal_usart_majority_vote_t sl_hal_usart_async_init_t::majority_vote

Majority Vote Disable for 16x, 8x and 6x oversampling modes.

hw_flow_control#

sl_hal_usart_hw_flow_control_t sl_hal_usart_async_init_t::hw_flow_control

Hardware flow control mode.