master#

bool sl_hal_usart_sync_init_t::master

Select if to operate in master or slave mode.

msb_first#

bool sl_hal_usart_sync_init_t::msb_first

Select if to send most or least significant bit first.

cs_invert#

bool sl_hal_usart_sync_init_t::cs_invert

Enable CS invert.

By default, chip select is active low. Set to true to make chip select active high.

auto_tx#

bool sl_hal_usart_sync_init_t::auto_tx

Enable AUTOTX mode.

Transmits as long as RX is not full. Generates underflows if TX is empty.

auto_cs_enable#

bool sl_hal_usart_sync_init_t::auto_cs_enable

Auto CS enabling.

prs_rx_enable#

bool sl_hal_usart_sync_init_t::prs_rx_enable

Enable USART Rx via PRS.

prs_rx_channel#

uint8_t sl_hal_usart_sync_init_t::prs_rx_channel

Select PRS channel for USART Rx. (Only valid if prs_rx_enable is true).

auto_cs_hold#

uint8_t sl_hal_usart_sync_init_t::auto_cs_hold

Auto CS hold time in baud cycles.

auto_cs_setup#

uint8_t sl_hal_usart_sync_init_t::auto_cs_setup

Auto CS setup time in baud cycles.

clock_div#

uint32_t sl_hal_usart_sync_init_t::clock_div

Desired baud rate.

data_bits#

sl_hal_usart_data_bits_t sl_hal_usart_sync_init_t::data_bits

Number of data bits in frame.

clock_mode#

sl_hal_usart_clock_mode_t sl_hal_usart_sync_init_t::clock_mode

Clock polarity/phase mode.