SPI Advanced initialization structure.
Public Attributes#
Enable automatic chip select. CS is managed by the peripheral.
If true, data will be sent with most significant bit first.
Enable the automatic wake up from EM2 to EM1 for DMA RX operation.
Enable AUTOTX mode.
Force load the first FIFO value.
Enable EUSART capability to use a PRS channel as an input data line for the receiver.
Enable EUSART capability to use a PRS channel as an input SPI Clock.
PRS Channel used to transmit data from PRS to the EUSART.
Enable EUSART capability to use a PRS channel as an input SPI Clock.
Setup window in bus clock cycles before the sampling edge of SCLK at word-boundary to avoid force load error.
Enable inversion of RX and/or TX signals.
Chip select polarity.
Auto CS setup time (before transmission) in baud cycles.
Auto CS hold time (after transmission) in baud cycles.
Inter-frame time in baud cycles.
Default transmitted data when the TXFIFO is empty.
Interrupt and status level of the Receive FIFO.
Interrupt and status level of the Transmit FIFO.
Public Attribute Documentation#
auto_cs_enable#
bool sl_hal_eusart_spi_advanced_init_t::auto_cs_enable
Enable automatic chip select. CS is managed by the peripheral.
msb_first#
bool sl_hal_eusart_spi_advanced_init_t::msb_first
If true, data will be sent with most significant bit first.
dma_wakeup_on_rx#
bool sl_hal_eusart_spi_advanced_init_t::dma_wakeup_on_rx
Enable the automatic wake up from EM2 to EM1 for DMA RX operation.
Only applicable to EM2 (low frequency) capable EUSART instances.
auto_tx_enable#
bool sl_hal_eusart_spi_advanced_init_t::auto_tx_enable
Enable AUTOTX mode.
Transmits as long as the RX FIFO is not full. Generates underflow interrupt if the TX FIFO is empty.
prs_rx_enable#
bool sl_hal_eusart_spi_advanced_init_t::prs_rx_enable
Enable EUSART capability to use a PRS channel as an input data line for the receiver.
PRS channel and RX GPIO must be configured separately using PRS/GPIO API.
prs_clock_enable#
bool sl_hal_eusart_spi_advanced_init_t::prs_clock_enable
Enable EUSART capability to use a PRS channel as an input SPI Clock.
Slave mode only.
prs_rx_channel#
uint8_t sl_hal_eusart_spi_advanced_init_t::prs_rx_channel
PRS Channel used to transmit data from PRS to the EUSART.
prs_clock_channel#
uint8_t sl_hal_eusart_spi_advanced_init_t::prs_clock_channel
Enable EUSART capability to use a PRS channel as an input SPI Clock.
Slave mode only.
setup_window#
uint8_t sl_hal_eusart_spi_advanced_init_t::setup_window
Setup window in bus clock cycles before the sampling edge of SCLK at word-boundary to avoid force load error.
invert_io#
sl_hal_eusart_invert_io_t sl_hal_eusart_spi_advanced_init_t::invert_io
Enable inversion of RX and/or TX signals.
cs_polarity#
sl_hal_eusart_cs_polarity_t sl_hal_eusart_spi_advanced_init_t::cs_polarity
Chip select polarity.
auto_cs_setup_time#
sl_hal_eusart_cs_time_t sl_hal_eusart_spi_advanced_init_t::auto_cs_setup_time
Auto CS setup time (before transmission) in baud cycles.
auto_cs_hold_time#
sl_hal_eusart_cs_time_t sl_hal_eusart_spi_advanced_init_t::auto_cs_hold_time
Auto CS hold time (after transmission) in baud cycles.
auto_inter_frame_time#
sl_hal_eusart_inter_character_space_t sl_hal_eusart_spi_advanced_init_t::auto_inter_frame_time
Inter-frame time in baud cycles.
default_tx_data#
uint16_t sl_hal_eusart_spi_advanced_init_t::default_tx_data
Default transmitted data when the TXFIFO is empty.
rx_fifo_watermark#
sl_hal_eusart_fifo_interrupt_watermark_t sl_hal_eusart_spi_advanced_init_t::rx_fifo_watermark
Interrupt and status level of the Receive FIFO.
tx_fifo_watermark#
sl_hal_eusart_fifo_interrupt_watermark_t sl_hal_eusart_spi_advanced_init_t::tx_fifo_watermark
Interrupt and status level of the Transmit FIFO.