UART advanced initialization structure.
Public Attributes#
Enable the collision Detection feature.
If true, data will be sent with most significant bit first.
Enable the automatic wake up from EM2 to EM1 for DMA RX operation.
Enable the automatic wake up from EM2 to EM1 for DMA TX operation.
Enable DMA requests blocking while framing or parity errors.
Enable automatic tristating of transmitter output when there is nothing to transmit.
Enable Multiprocessor mode. Address and data filtering using the 9th bit.
Multiprocessor address bit value. If true, 9th bit of address frame must be 1, 0 otherwise.
Enable EUSART capability to use a PRS channel as an input data line for the receiver.
PRS Channel used to transmit data from PRS to the EUSART.
Start frame that will enable RX operation. 0x00 Disable this feature.
Hardware flow control mode.
Enable inversion of RX and/or TX signals.
Auto TX delay before new transfers. Frames sent back-to-back are not delayed.
Interrupt and status level of the Receive FIFO.
Interrupt and status level of the Transmit FIFO.
Public Attribute Documentation#
collision_detect#
bool sl_hal_eusart_uart_advanced_init_t::collision_detect
Enable the collision Detection feature.
Internal (setting loopback_enable) or external loopback must be done to use this feature.
msb_first#
bool sl_hal_eusart_uart_advanced_init_t::msb_first
If true, data will be sent with most significant bit first.
dma_wakeup_on_rx#
bool sl_hal_eusart_uart_advanced_init_t::dma_wakeup_on_rx
Enable the automatic wake up from EM2 to EM1 for DMA RX operation.
dma_wakeup_on_tx#
bool sl_hal_eusart_uart_advanced_init_t::dma_wakeup_on_tx
Enable the automatic wake up from EM2 to EM1 for DMA TX operation.
dma_halt_on_error#
bool sl_hal_eusart_uart_advanced_init_t::dma_halt_on_error
Enable DMA requests blocking while framing or parity errors.
tx_auto_tristate#
bool sl_hal_eusart_uart_advanced_init_t::tx_auto_tristate
Enable automatic tristating of transmitter output when there is nothing to transmit.
multi_processor_enable#
bool sl_hal_eusart_uart_advanced_init_t::multi_processor_enable
Enable Multiprocessor mode. Address and data filtering using the 9th bit.
multi_processor_address_bit_high#
bool sl_hal_eusart_uart_advanced_init_t::multi_processor_address_bit_high
Multiprocessor address bit value. If true, 9th bit of address frame must be 1, 0 otherwise.
prs_rx_enable#
bool sl_hal_eusart_uart_advanced_init_t::prs_rx_enable
Enable EUSART capability to use a PRS channel as an input data line for the receiver.
PRS channel and RX GPIO must be configured separately using PRS/GPIO API.
prs_rx_channel#
uint8_t sl_hal_eusart_uart_advanced_init_t::prs_rx_channel
PRS Channel used to transmit data from PRS to the EUSART.
start_frame#
uint8_t sl_hal_eusart_uart_advanced_init_t::start_frame
Start frame that will enable RX operation. 0x00 Disable this feature.
hw_flow_control_mode#
sl_hal_eusart_hw_flow_control_t sl_hal_eusart_uart_advanced_init_t::hw_flow_control_mode
Hardware flow control mode.
invert_io#
sl_hal_eusart_invert_io_t sl_hal_eusart_uart_advanced_init_t::invert_io
Enable inversion of RX and/or TX signals.
auto_tx_delay#
sl_hal_eusart_auto_tx_delay_t sl_hal_eusart_uart_advanced_init_t::auto_tx_delay
Auto TX delay before new transfers. Frames sent back-to-back are not delayed.
rx_fifo_watermark#
sl_hal_eusart_fifo_interrupt_watermark_t sl_hal_eusart_uart_advanced_init_t::rx_fifo_watermark
Interrupt and status level of the Receive FIFO.
tx_fifo_watermark#
sl_hal_eusart_fifo_interrupt_watermark_t sl_hal_eusart_uart_advanced_init_t::tx_fifo_watermark
Interrupt and status level of the Transmit FIFO.