Define peripheral DMA structure.

Public Attributes#

uint32_t
base

Peripheral base address.

sl_clock_branch_t
clk_branch

Peripheral clock branch.

sl_bus_clock_t
bus_clock

Peripheral bus clock.

uint32_t
dual_destination_map

A bitmap of the channels supporting dual destination.

uint32_t
rule_based_interleaving_map

A bitmap of the channels supporting rule based interleaving.

uint8_t
nbr_channel

Number of channels.

uint8_t
nbr_sync

Number of sync bits.

Public Attribute Documentation#

base#

uint32_t sl_peripheral_dma_val_t::base

Peripheral base address.


clk_branch#

sl_clock_branch_t sl_peripheral_dma_val_t::clk_branch

Peripheral clock branch.


bus_clock#

sl_bus_clock_t sl_peripheral_dma_val_t::bus_clock

Peripheral bus clock.


dual_destination_map#

uint32_t sl_peripheral_dma_val_t::dual_destination_map

A bitmap of the channels supporting dual destination.


rule_based_interleaving_map#

uint32_t sl_peripheral_dma_val_t::rule_based_interleaving_map

A bitmap of the channels supporting rule based interleaving.


nbr_channel#

uint8_t sl_peripheral_dma_val_t::nbr_channel

Number of channels.


nbr_sync#

uint8_t sl_peripheral_dma_val_t::nbr_sync

Number of sync bits.