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Define peripheral TIMER structure.
Public Attributes#
sl_dma_signal_t
Underflow/Overflow DMA channel.
Public Attribute Documentation#
base#
uint32_t sl_peripheral_timer_val_t::base
Peripheral base address.
clk_branch#
sl_clock_branch_t sl_peripheral_timer_val_t::clk_branch
Peripheral clock branch.
bus_clock#
sl_bus_clock_t sl_peripheral_timer_val_t::bus_clock
Peripheral bus clock.
dma_signal_cc0#
sl_dma_signal_t sl_peripheral_timer_val_t::dma_signal_cc0
CC0 DMA channel.
dma_signal_cc1#
sl_dma_signal_t sl_peripheral_timer_val_t::dma_signal_cc1
CC1 DMA channel.
dma_signal_cc2#
sl_dma_signal_t sl_peripheral_timer_val_t::dma_signal_cc2
CC2 DMA channel.
dma_signal_ufof#
sl_dma_signal_t sl_peripheral_timer_val_t::dma_signal_ufof
Underflow/Overflow DMA channel.
dma_signal_cc3#
sl_dma_signal_t sl_peripheral_timer_val_t::dma_signal_cc3
CC3 DMA channel.
dma_signal_cc4#
sl_dma_signal_t sl_peripheral_timer_val_t::dma_signal_cc4
CC4 DMA channel.
dma_signal_cc5#
sl_dma_signal_t sl_peripheral_timer_val_t::dma_signal_cc5
CC5 DMA channel.
dma_signal_cc6#
sl_dma_signal_t sl_peripheral_timer_val_t::dma_signal_cc6
CC6 DMA channel.
