Macros
#define	_EMU_BIASCONF_GMCEM23_DEFAULT 0x00000001UL

#define	_EMU_BIASCONF_GMCEM23_MASK 0x10UL

#define	_EMU_BIASCONF_GMCEM23_SHIFT 4

#define	_EMU_BIASCONF_LPEM01_DEFAULT 0x00000001UL

#define	_EMU_BIASCONF_LPEM01_MASK 0x8UL

#define	_EMU_BIASCONF_LPEM01_SHIFT 3

#define	_EMU_BIASCONF_LPEM23_DEFAULT 0x00000001UL

#define	_EMU_BIASCONF_LPEM23_MASK 0x80UL

#define	_EMU_BIASCONF_LPEM23_SHIFT 7

#define	_EMU_BIASCONF_MASK 0x000000FCUL

#define	_EMU_BIASCONF_NADUTYEM01_DEFAULT 0x00000000UL

#define	_EMU_BIASCONF_NADUTYEM01_MASK 0x4UL

#define	_EMU_BIASCONF_NADUTYEM01_SHIFT 2

#define	_EMU_BIASCONF_NADUTYEM23_DEFAULT 0x00000001UL

#define	_EMU_BIASCONF_NADUTYEM23_MASK 0x40UL

#define	_EMU_BIASCONF_NADUTYEM23_SHIFT 6

#define	_EMU_BIASCONF_RESETVALUE 0x000000F8UL

#define	_EMU_BIASCONF_UADUTYEM23_DEFAULT 0x00000001UL

#define	_EMU_BIASCONF_UADUTYEM23_MASK 0x20UL

#define	_EMU_BIASCONF_UADUTYEM23_SHIFT 5

#define	_EMU_BIASTESTCTRL_BIAS_RIP_RESET_DEFAULT 0x00000000UL

#define	_EMU_BIASTESTCTRL_BIAS_RIP_RESET_MASK 0x8UL

#define	_EMU_BIASTESTCTRL_BIAS_RIP_RESET_SHIFT 3

#define	_EMU_BIASTESTCTRL_MASK 0x00000008UL

#define	_EMU_BIASTESTCTRL_RESETVALUE 0x00000000UL

#define	_EMU_CMD_EM4UNLATCH_DEFAULT 0x00000000UL

#define	_EMU_CMD_EM4UNLATCH_MASK 0x1UL

#define	_EMU_CMD_EM4UNLATCH_SHIFT 0

#define	_EMU_CMD_MASK 0x00000001UL

#define	_EMU_CMD_RESETVALUE 0x00000000UL

#define	_EMU_CTRL_EM2BLOCK_DEFAULT 0x00000000UL

#define	_EMU_CTRL_EM2BLOCK_MASK 0x2UL

#define	_EMU_CTRL_EM2BLOCK_SHIFT 1

#define	_EMU_CTRL_MASK 0x00000002UL

#define	_EMU_CTRL_RESETVALUE 0x00000000UL

#define	_EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT 0x00000001UL

#define	_EMU_DCDCCLIMCTRL_BYPLIMEN_MASK 0x2000UL

#define	_EMU_DCDCCLIMCTRL_BYPLIMEN_SHIFT 13

#define	_EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT 0x00000001UL

#define	_EMU_DCDCCLIMCTRL_CLIMBLANKDLY_MASK 0x300UL

#define	_EMU_DCDCCLIMCTRL_CLIMBLANKDLY_SHIFT 8

#define	_EMU_DCDCCLIMCTRL_MASK 0x00002300UL

#define	_EMU_DCDCCLIMCTRL_RESETVALUE 0x00002100UL

#define	_EMU_DCDCCTRL_DCDCMODE_BYPASS 0x00000000UL

#define	_EMU_DCDCCTRL_DCDCMODE_DEFAULT 0x00000000UL

#define	_EMU_DCDCCTRL_DCDCMODE_LOWNOISE 0x00000001UL

#define	_EMU_DCDCCTRL_DCDCMODE_LOWPOWER 0x00000002UL

#define	_EMU_DCDCCTRL_DCDCMODE_MASK 0x3UL

#define	_EMU_DCDCCTRL_DCDCMODE_OFF 0x00000003UL

#define	_EMU_DCDCCTRL_DCDCMODE_SHIFT 0

#define	_EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT 0x00000001UL

#define	_EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER 0x00000001UL

#define	_EMU_DCDCCTRL_DCDCMODEEM23_EM23SW 0x00000000UL

#define	_EMU_DCDCCTRL_DCDCMODEEM23_MASK 0x10UL

#define	_EMU_DCDCCTRL_DCDCMODEEM23_SHIFT 4

#define	_EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT 0x00000001UL

#define	_EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER 0x00000001UL

#define	_EMU_DCDCCTRL_DCDCMODEEM4_EM4SW 0x00000000UL

#define	_EMU_DCDCCTRL_DCDCMODEEM4_MASK 0x20UL

#define	_EMU_DCDCCTRL_DCDCMODEEM4_SHIFT 5

#define	_EMU_DCDCCTRL_MASK 0x00000033UL

#define	_EMU_DCDCCTRL_RESETVALUE 0x00000030UL

#define	_EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT 0x00000002UL

#define	_EMU_DCDCLNCOMPCTRL_COMPENC1_MASK 0x300000UL

#define	_EMU_DCDCLNCOMPCTRL_COMPENC1_SHIFT 20

#define	_EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT 0x00000007UL

#define	_EMU_DCDCLNCOMPCTRL_COMPENC2_MASK 0x7000000UL

#define	_EMU_DCDCLNCOMPCTRL_COMPENC2_SHIFT 24

#define	_EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT 0x00000005UL

#define	_EMU_DCDCLNCOMPCTRL_COMPENC3_MASK 0xF0000000UL

#define	_EMU_DCDCLNCOMPCTRL_COMPENC3_SHIFT 28

#define	_EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT 0x00000007UL

#define	_EMU_DCDCLNCOMPCTRL_COMPENR1_MASK 0x7UL

#define	_EMU_DCDCLNCOMPCTRL_COMPENR1_SHIFT 0

#define	_EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT 0x00000007UL

#define	_EMU_DCDCLNCOMPCTRL_COMPENR2_MASK 0x1F0UL

#define	_EMU_DCDCLNCOMPCTRL_COMPENR2_SHIFT 4

#define	_EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT 0x00000004UL

#define	_EMU_DCDCLNCOMPCTRL_COMPENR3_MASK 0xF000UL

#define	_EMU_DCDCLNCOMPCTRL_COMPENR3_SHIFT 12

#define	_EMU_DCDCLNCOMPCTRL_MASK 0xF730F1F7UL

#define	_EMU_DCDCLNCOMPCTRL_RESETVALUE 0x57204077UL

#define	_EMU_DCDCLNFREQCTRL_MASK 0x1F000007UL

#define	_EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT 0x00000000UL

#define	_EMU_DCDCLNFREQCTRL_RCOBAND_MASK 0x7UL

#define	_EMU_DCDCLNFREQCTRL_RCOBAND_SHIFT 0

#define	_EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT 0x00000010UL

#define	_EMU_DCDCLNFREQCTRL_RCOTRIM_MASK 0x1F000000UL

#define	_EMU_DCDCLNFREQCTRL_RCOTRIM_SHIFT 24

#define	_EMU_DCDCLNFREQCTRL_RESETVALUE 0x10000000UL

#define	_EMU_DCDCLNVCTRL_LNATT_DEFAULT 0x00000000UL

#define	_EMU_DCDCLNVCTRL_LNATT_DIV3 0x00000000UL

#define	_EMU_DCDCLNVCTRL_LNATT_DIV6 0x00000001UL

#define	_EMU_DCDCLNVCTRL_LNATT_MASK 0x2UL

#define	_EMU_DCDCLNVCTRL_LNATT_SHIFT 1

#define	_EMU_DCDCLNVCTRL_LNVREF_DEFAULT 0x00000071UL

#define	_EMU_DCDCLNVCTRL_LNVREF_MASK 0x7F00UL

#define	_EMU_DCDCLNVCTRL_LNVREF_SHIFT 8

#define	_EMU_DCDCLNVCTRL_MASK 0x00007F02UL

#define	_EMU_DCDCLNVCTRL_RESETVALUE 0x00007100UL

#define	_EMU_DCDCLPCTRL_LPBLANK_DEFAULT 0x00000000UL

#define	_EMU_DCDCLPCTRL_LPBLANK_MASK 0x6000000UL

#define	_EMU_DCDCLPCTRL_LPBLANK_SHIFT 25

#define	_EMU_DCDCLPCTRL_LPCMPHYSSEL_DEFAULT 0x00000007UL

#define	_EMU_DCDCLPCTRL_LPCMPHYSSEL_MASK 0xF000UL

#define	_EMU_DCDCLPCTRL_LPCMPHYSSEL_SHIFT 12

#define	_EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT 0x00000000UL

#define	_EMU_DCDCLPCTRL_LPVREFDUTYEN_MASK 0x1000000UL

#define	_EMU_DCDCLPCTRL_LPVREFDUTYEN_SHIFT 24

#define	_EMU_DCDCLPCTRL_MASK 0x0700F000UL

#define	_EMU_DCDCLPCTRL_RESETVALUE 0x00007000UL

#define	_EMU_DCDCLPVCTRL_LPATT_DEFAULT 0x00000000UL

#define	_EMU_DCDCLPVCTRL_LPATT_DIV4 0x00000000UL

#define	_EMU_DCDCLPVCTRL_LPATT_DIV8 0x00000001UL

#define	_EMU_DCDCLPVCTRL_LPATT_MASK 0x1UL

#define	_EMU_DCDCLPVCTRL_LPATT_SHIFT 0

#define	_EMU_DCDCLPVCTRL_LPVREF_DEFAULT 0x000000B4UL

#define	_EMU_DCDCLPVCTRL_LPVREF_MASK 0x1FEUL

#define	_EMU_DCDCLPVCTRL_LPVREF_SHIFT 1

#define	_EMU_DCDCLPVCTRL_MASK 0x000001FFUL

#define	_EMU_DCDCLPVCTRL_RESETVALUE 0x00000168UL

#define	_EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT 0x00000000UL

#define	_EMU_DCDCMISCCTRL_BYPLIMSEL_MASK 0xF0000UL

#define	_EMU_DCDCMISCCTRL_BYPLIMSEL_SHIFT 16

#define	_EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT 0x00000003UL

#define	_EMU_DCDCMISCCTRL_LNCLIMILIMSEL_MASK 0x7000000UL

#define	_EMU_DCDCMISCCTRL_LNCLIMILIMSEL_SHIFT 24

#define	_EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT 0x00000000UL

#define	_EMU_DCDCMISCCTRL_LNFORCECCM_MASK 0x1UL

#define	_EMU_DCDCMISCCTRL_LNFORCECCM_SHIFT 0

#define	_EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT 0x00000003UL

#define	_EMU_DCDCMISCCTRL_LPCLIMILIMSEL_MASK 0x700000UL

#define	_EMU_DCDCMISCCTRL_LPCLIMILIMSEL_SHIFT 20

#define	_EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS0 0x00000000UL

#define	_EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS1 0x00000001UL

#define	_EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS2 0x00000002UL

#define	_EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS3 0x00000003UL

#define	_EMU_DCDCMISCCTRL_LPCMPBIAS_DEFAULT 0x00000003UL

#define	_EMU_DCDCMISCCTRL_LPCMPBIAS_MASK 0x30000000UL

#define	_EMU_DCDCMISCCTRL_LPCMPBIAS_SHIFT 28

#define	_EMU_DCDCMISCCTRL_MASK 0x377FFF01UL

#define	_EMU_DCDCMISCCTRL_NFETCNT_DEFAULT 0x00000007UL

#define	_EMU_DCDCMISCCTRL_NFETCNT_MASK 0xF000UL

#define	_EMU_DCDCMISCCTRL_NFETCNT_SHIFT 12

#define	_EMU_DCDCMISCCTRL_PFETCNT_DEFAULT 0x00000007UL

#define	_EMU_DCDCMISCCTRL_PFETCNT_MASK 0xF00UL

#define	_EMU_DCDCMISCCTRL_PFETCNT_SHIFT 8

#define	_EMU_DCDCMISCCTRL_RESETVALUE 0x33307700UL

#define	_EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT 0x00000000UL

#define	_EMU_DCDCSYNC_DCDCCTRLBUSY_MASK 0x1UL

#define	_EMU_DCDCSYNC_DCDCCTRLBUSY_SHIFT 0

#define	_EMU_DCDCSYNC_MASK 0x00000001UL

#define	_EMU_DCDCSYNC_RESETVALUE 0x00000000UL

#define	_EMU_DCDCTIMING_BYPWAIT_DEFAULT 0x000000FFUL

#define	_EMU_DCDCTIMING_BYPWAIT_MASK 0xFF00000UL

#define	_EMU_DCDCTIMING_BYPWAIT_SHIFT 20

#define	_EMU_DCDCTIMING_COMPENPRCHGEN_DEFAULT 0x00000001UL

#define	_EMU_DCDCTIMING_COMPENPRCHGEN_MASK 0x800UL

#define	_EMU_DCDCTIMING_COMPENPRCHGEN_SHIFT 11

#define	_EMU_DCDCTIMING_DUTYSCALE_DEFAULT 0x00000000UL

#define	_EMU_DCDCTIMING_DUTYSCALE_MASK 0x60000000UL

#define	_EMU_DCDCTIMING_DUTYSCALE_SHIFT 29

#define	_EMU_DCDCTIMING_LNWAIT_DEFAULT 0x0000001FUL

#define	_EMU_DCDCTIMING_LNWAIT_MASK 0x1F000UL

#define	_EMU_DCDCTIMING_LNWAIT_SHIFT 12

#define	_EMU_DCDCTIMING_LPINITWAIT_DEFAULT 0x000000FFUL

#define	_EMU_DCDCTIMING_LPINITWAIT_MASK 0xFFUL

#define	_EMU_DCDCTIMING_LPINITWAIT_SHIFT 0

#define	_EMU_DCDCTIMING_MASK 0x6FF1F8FFUL

#define	_EMU_DCDCTIMING_RESETVALUE 0x0FF1F8FFUL

#define	_EMU_DCDCZDETCTRL_MASK 0x00000370UL

#define	_EMU_DCDCZDETCTRL_RESETVALUE 0x00000130UL

#define	_EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT 0x00000001UL

#define	_EMU_DCDCZDETCTRL_ZDETBLANKDLY_MASK 0x300UL

#define	_EMU_DCDCZDETCTRL_ZDETBLANKDLY_SHIFT 8

#define	_EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT 0x00000003UL

#define	_EMU_DCDCZDETCTRL_ZDETILIMSEL_MASK 0x70UL

#define	_EMU_DCDCZDETCTRL_ZDETILIMSEL_SHIFT 4

#define	_EMU_EM4CTRL_EM4ENTRY_DEFAULT 0x00000000UL

#define	_EMU_EM4CTRL_EM4ENTRY_MASK 0x30000UL

#define	_EMU_EM4CTRL_EM4ENTRY_SHIFT 16

#define	_EMU_EM4CTRL_EM4IORETMODE_DEFAULT 0x00000000UL

#define	_EMU_EM4CTRL_EM4IORETMODE_DISABLE 0x00000000UL

#define	_EMU_EM4CTRL_EM4IORETMODE_EM4EXIT 0x00000001UL

#define	_EMU_EM4CTRL_EM4IORETMODE_MASK 0x30UL

#define	_EMU_EM4CTRL_EM4IORETMODE_SHIFT 4

#define	_EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH 0x00000002UL

#define	_EMU_EM4CTRL_EM4STATE_DEFAULT 0x00000000UL

#define	_EMU_EM4CTRL_EM4STATE_EM4H 0x00000001UL

#define	_EMU_EM4CTRL_EM4STATE_EM4S 0x00000000UL

#define	_EMU_EM4CTRL_EM4STATE_MASK 0x1UL

#define	_EMU_EM4CTRL_EM4STATE_SHIFT 0

#define	_EMU_EM4CTRL_MASK 0x0003003FUL

#define	_EMU_EM4CTRL_RESETVALUE 0x00000000UL

#define	_EMU_EM4CTRL_RETAINLFRCO_DEFAULT 0x00000000UL

#define	_EMU_EM4CTRL_RETAINLFRCO_MASK 0x2UL

#define	_EMU_EM4CTRL_RETAINLFRCO_SHIFT 1

#define	_EMU_EM4CTRL_RETAINLFXO_DEFAULT 0x00000000UL

#define	_EMU_EM4CTRL_RETAINLFXO_MASK 0x4UL

#define	_EMU_EM4CTRL_RETAINLFXO_SHIFT 2

#define	_EMU_EM4CTRL_RETAINULFRCO_DEFAULT 0x00000000UL

#define	_EMU_EM4CTRL_RETAINULFRCO_MASK 0x8UL

#define	_EMU_EM4CTRL_RETAINULFRCO_SHIFT 3

#define	_EMU_IEN_DCDCINBYPASS_DEFAULT 0x00000000UL

#define	_EMU_IEN_DCDCINBYPASS_MASK 0x100000UL

#define	_EMU_IEN_DCDCINBYPASS_SHIFT 20

#define	_EMU_IEN_DCDCLNRUNNING_DEFAULT 0x00000000UL

#define	_EMU_IEN_DCDCLNRUNNING_MASK 0x80000UL

#define	_EMU_IEN_DCDCLNRUNNING_SHIFT 19

#define	_EMU_IEN_DCDCLPRUNNING_DEFAULT 0x00000000UL

#define	_EMU_IEN_DCDCLPRUNNING_MASK 0x40000UL

#define	_EMU_IEN_DCDCLPRUNNING_SHIFT 18

#define	_EMU_IEN_EM23WAKEUP_DEFAULT 0x00000000UL

#define	_EMU_IEN_EM23WAKEUP_MASK 0x1000000UL

#define	_EMU_IEN_EM23WAKEUP_SHIFT 24

#define	_EMU_IEN_MASK 0xE11FC0FFUL

#define	_EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL

#define	_EMU_IEN_NFETOVERCURRENTLIMIT_MASK 0x20000UL

#define	_EMU_IEN_NFETOVERCURRENTLIMIT_SHIFT 17

#define	_EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL

#define	_EMU_IEN_PFETOVERCURRENTLIMIT_MASK 0x10000UL

#define	_EMU_IEN_PFETOVERCURRENTLIMIT_SHIFT 16

#define	_EMU_IEN_RESETVALUE 0x00000000UL

#define	_EMU_IEN_TEMP_DEFAULT 0x00000000UL

#define	_EMU_IEN_TEMP_MASK 0x20000000UL

#define	_EMU_IEN_TEMP_SHIFT 29

#define	_EMU_IEN_TEMPHIGH_DEFAULT 0x00000000UL

#define	_EMU_IEN_TEMPHIGH_MASK 0x80000000UL

#define	_EMU_IEN_TEMPHIGH_SHIFT 31

#define	_EMU_IEN_TEMPLOW_DEFAULT 0x00000000UL

#define	_EMU_IEN_TEMPLOW_MASK 0x40000000UL

#define	_EMU_IEN_TEMPLOW_SHIFT 30

#define	_EMU_IEN_VMONALTAVDDFALL_DEFAULT 0x00000000UL

#define	_EMU_IEN_VMONALTAVDDFALL_MASK 0x4UL

#define	_EMU_IEN_VMONALTAVDDFALL_SHIFT 2

#define	_EMU_IEN_VMONALTAVDDRISE_DEFAULT 0x00000000UL

#define	_EMU_IEN_VMONALTAVDDRISE_MASK 0x8UL

#define	_EMU_IEN_VMONALTAVDDRISE_SHIFT 3

#define	_EMU_IEN_VMONAVDDFALL_DEFAULT 0x00000000UL

#define	_EMU_IEN_VMONAVDDFALL_MASK 0x1UL

#define	_EMU_IEN_VMONAVDDFALL_SHIFT 0

#define	_EMU_IEN_VMONAVDDRISE_DEFAULT 0x00000000UL

#define	_EMU_IEN_VMONAVDDRISE_MASK 0x2UL

#define	_EMU_IEN_VMONAVDDRISE_SHIFT 1

#define	_EMU_IEN_VMONDVDDFALL_DEFAULT 0x00000000UL

#define	_EMU_IEN_VMONDVDDFALL_MASK 0x10UL

#define	_EMU_IEN_VMONDVDDFALL_SHIFT 4

#define	_EMU_IEN_VMONDVDDRISE_DEFAULT 0x00000000UL

#define	_EMU_IEN_VMONDVDDRISE_MASK 0x20UL

#define	_EMU_IEN_VMONDVDDRISE_SHIFT 5

#define	_EMU_IEN_VMONFVDDFALL_DEFAULT 0x00000000UL

#define	_EMU_IEN_VMONFVDDFALL_MASK 0x4000UL

#define	_EMU_IEN_VMONFVDDFALL_SHIFT 14

#define	_EMU_IEN_VMONFVDDRISE_DEFAULT 0x00000000UL

#define	_EMU_IEN_VMONFVDDRISE_MASK 0x8000UL

#define	_EMU_IEN_VMONFVDDRISE_SHIFT 15

#define	_EMU_IEN_VMONIO0FALL_DEFAULT 0x00000000UL

#define	_EMU_IEN_VMONIO0FALL_MASK 0x40UL

#define	_EMU_IEN_VMONIO0FALL_SHIFT 6

#define	_EMU_IEN_VMONIO0RISE_DEFAULT 0x00000000UL

#define	_EMU_IEN_VMONIO0RISE_MASK 0x80UL

#define	_EMU_IEN_VMONIO0RISE_SHIFT 7

#define	_EMU_IF_DCDCINBYPASS_DEFAULT 0x00000000UL

#define	_EMU_IF_DCDCINBYPASS_MASK 0x100000UL

#define	_EMU_IF_DCDCINBYPASS_SHIFT 20

#define	_EMU_IF_DCDCLNRUNNING_DEFAULT 0x00000000UL

#define	_EMU_IF_DCDCLNRUNNING_MASK 0x80000UL

#define	_EMU_IF_DCDCLNRUNNING_SHIFT 19

#define	_EMU_IF_DCDCLPRUNNING_DEFAULT 0x00000000UL

#define	_EMU_IF_DCDCLPRUNNING_MASK 0x40000UL

#define	_EMU_IF_DCDCLPRUNNING_SHIFT 18

#define	_EMU_IF_EM23WAKEUP_DEFAULT 0x00000000UL

#define	_EMU_IF_EM23WAKEUP_MASK 0x1000000UL

#define	_EMU_IF_EM23WAKEUP_SHIFT 24

#define	_EMU_IF_MASK 0xE11FC0FFUL

#define	_EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL

#define	_EMU_IF_NFETOVERCURRENTLIMIT_MASK 0x20000UL

#define	_EMU_IF_NFETOVERCURRENTLIMIT_SHIFT 17

#define	_EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL

#define	_EMU_IF_PFETOVERCURRENTLIMIT_MASK 0x10000UL

#define	_EMU_IF_PFETOVERCURRENTLIMIT_SHIFT 16

#define	_EMU_IF_RESETVALUE 0x00000000UL

#define	_EMU_IF_TEMP_DEFAULT 0x00000000UL

#define	_EMU_IF_TEMP_MASK 0x20000000UL

#define	_EMU_IF_TEMP_SHIFT 29

#define	_EMU_IF_TEMPHIGH_DEFAULT 0x00000000UL

#define	_EMU_IF_TEMPHIGH_MASK 0x80000000UL

#define	_EMU_IF_TEMPHIGH_SHIFT 31

#define	_EMU_IF_TEMPLOW_DEFAULT 0x00000000UL

#define	_EMU_IF_TEMPLOW_MASK 0x40000000UL

#define	_EMU_IF_TEMPLOW_SHIFT 30

#define	_EMU_IF_VMONALTAVDDFALL_DEFAULT 0x00000000UL

#define	_EMU_IF_VMONALTAVDDFALL_MASK 0x4UL

#define	_EMU_IF_VMONALTAVDDFALL_SHIFT 2

#define	_EMU_IF_VMONALTAVDDRISE_DEFAULT 0x00000000UL

#define	_EMU_IF_VMONALTAVDDRISE_MASK 0x8UL

#define	_EMU_IF_VMONALTAVDDRISE_SHIFT 3

#define	_EMU_IF_VMONAVDDFALL_DEFAULT 0x00000000UL

#define	_EMU_IF_VMONAVDDFALL_MASK 0x1UL

#define	_EMU_IF_VMONAVDDFALL_SHIFT 0

#define	_EMU_IF_VMONAVDDRISE_DEFAULT 0x00000000UL

#define	_EMU_IF_VMONAVDDRISE_MASK 0x2UL

#define	_EMU_IF_VMONAVDDRISE_SHIFT 1

#define	_EMU_IF_VMONDVDDFALL_DEFAULT 0x00000000UL

#define	_EMU_IF_VMONDVDDFALL_MASK 0x10UL

#define	_EMU_IF_VMONDVDDFALL_SHIFT 4

#define	_EMU_IF_VMONDVDDRISE_DEFAULT 0x00000000UL

#define	_EMU_IF_VMONDVDDRISE_MASK 0x20UL

#define	_EMU_IF_VMONDVDDRISE_SHIFT 5

#define	_EMU_IF_VMONFVDDFALL_DEFAULT 0x00000000UL

#define	_EMU_IF_VMONFVDDFALL_MASK 0x4000UL

#define	_EMU_IF_VMONFVDDFALL_SHIFT 14

#define	_EMU_IF_VMONFVDDRISE_DEFAULT 0x00000000UL

#define	_EMU_IF_VMONFVDDRISE_MASK 0x8000UL

#define	_EMU_IF_VMONFVDDRISE_SHIFT 15

#define	_EMU_IF_VMONIO0FALL_DEFAULT 0x00000000UL

#define	_EMU_IF_VMONIO0FALL_MASK 0x40UL

#define	_EMU_IF_VMONIO0FALL_SHIFT 6

#define	_EMU_IF_VMONIO0RISE_DEFAULT 0x00000000UL

#define	_EMU_IF_VMONIO0RISE_MASK 0x80UL

#define	_EMU_IF_VMONIO0RISE_SHIFT 7

#define	_EMU_IFC_DCDCINBYPASS_DEFAULT 0x00000000UL

#define	_EMU_IFC_DCDCINBYPASS_MASK 0x100000UL

#define	_EMU_IFC_DCDCINBYPASS_SHIFT 20

#define	_EMU_IFC_DCDCLNRUNNING_DEFAULT 0x00000000UL

#define	_EMU_IFC_DCDCLNRUNNING_MASK 0x80000UL

#define	_EMU_IFC_DCDCLNRUNNING_SHIFT 19

#define	_EMU_IFC_DCDCLPRUNNING_DEFAULT 0x00000000UL

#define	_EMU_IFC_DCDCLPRUNNING_MASK 0x40000UL

#define	_EMU_IFC_DCDCLPRUNNING_SHIFT 18

#define	_EMU_IFC_EM23WAKEUP_DEFAULT 0x00000000UL

#define	_EMU_IFC_EM23WAKEUP_MASK 0x1000000UL

#define	_EMU_IFC_EM23WAKEUP_SHIFT 24

#define	_EMU_IFC_MASK 0xE11FC0FFUL

#define	_EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL

#define	_EMU_IFC_NFETOVERCURRENTLIMIT_MASK 0x20000UL

#define	_EMU_IFC_NFETOVERCURRENTLIMIT_SHIFT 17

#define	_EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL

#define	_EMU_IFC_PFETOVERCURRENTLIMIT_MASK 0x10000UL

#define	_EMU_IFC_PFETOVERCURRENTLIMIT_SHIFT 16

#define	_EMU_IFC_RESETVALUE 0x00000000UL

#define	_EMU_IFC_TEMP_DEFAULT 0x00000000UL

#define	_EMU_IFC_TEMP_MASK 0x20000000UL

#define	_EMU_IFC_TEMP_SHIFT 29

#define	_EMU_IFC_TEMPHIGH_DEFAULT 0x00000000UL

#define	_EMU_IFC_TEMPHIGH_MASK 0x80000000UL

#define	_EMU_IFC_TEMPHIGH_SHIFT 31

#define	_EMU_IFC_TEMPLOW_DEFAULT 0x00000000UL

#define	_EMU_IFC_TEMPLOW_MASK 0x40000000UL

#define	_EMU_IFC_TEMPLOW_SHIFT 30

#define	_EMU_IFC_VMONALTAVDDFALL_DEFAULT 0x00000000UL

#define	_EMU_IFC_VMONALTAVDDFALL_MASK 0x4UL

#define	_EMU_IFC_VMONALTAVDDFALL_SHIFT 2

#define	_EMU_IFC_VMONALTAVDDRISE_DEFAULT 0x00000000UL

#define	_EMU_IFC_VMONALTAVDDRISE_MASK 0x8UL

#define	_EMU_IFC_VMONALTAVDDRISE_SHIFT 3

#define	_EMU_IFC_VMONAVDDFALL_DEFAULT 0x00000000UL

#define	_EMU_IFC_VMONAVDDFALL_MASK 0x1UL

#define	_EMU_IFC_VMONAVDDFALL_SHIFT 0

#define	_EMU_IFC_VMONAVDDRISE_DEFAULT 0x00000000UL

#define	_EMU_IFC_VMONAVDDRISE_MASK 0x2UL

#define	_EMU_IFC_VMONAVDDRISE_SHIFT 1

#define	_EMU_IFC_VMONDVDDFALL_DEFAULT 0x00000000UL

#define	_EMU_IFC_VMONDVDDFALL_MASK 0x10UL

#define	_EMU_IFC_VMONDVDDFALL_SHIFT 4

#define	_EMU_IFC_VMONDVDDRISE_DEFAULT 0x00000000UL

#define	_EMU_IFC_VMONDVDDRISE_MASK 0x20UL

#define	_EMU_IFC_VMONDVDDRISE_SHIFT 5

#define	_EMU_IFC_VMONFVDDFALL_DEFAULT 0x00000000UL

#define	_EMU_IFC_VMONFVDDFALL_MASK 0x4000UL

#define	_EMU_IFC_VMONFVDDFALL_SHIFT 14

#define	_EMU_IFC_VMONFVDDRISE_DEFAULT 0x00000000UL

#define	_EMU_IFC_VMONFVDDRISE_MASK 0x8000UL

#define	_EMU_IFC_VMONFVDDRISE_SHIFT 15

#define	_EMU_IFC_VMONIO0FALL_DEFAULT 0x00000000UL

#define	_EMU_IFC_VMONIO0FALL_MASK 0x40UL

#define	_EMU_IFC_VMONIO0FALL_SHIFT 6

#define	_EMU_IFC_VMONIO0RISE_DEFAULT 0x00000000UL

#define	_EMU_IFC_VMONIO0RISE_MASK 0x80UL

#define	_EMU_IFC_VMONIO0RISE_SHIFT 7

#define	_EMU_IFS_DCDCINBYPASS_DEFAULT 0x00000000UL

#define	_EMU_IFS_DCDCINBYPASS_MASK 0x100000UL

#define	_EMU_IFS_DCDCINBYPASS_SHIFT 20

#define	_EMU_IFS_DCDCLNRUNNING_DEFAULT 0x00000000UL

#define	_EMU_IFS_DCDCLNRUNNING_MASK 0x80000UL

#define	_EMU_IFS_DCDCLNRUNNING_SHIFT 19

#define	_EMU_IFS_DCDCLPRUNNING_DEFAULT 0x00000000UL

#define	_EMU_IFS_DCDCLPRUNNING_MASK 0x40000UL

#define	_EMU_IFS_DCDCLPRUNNING_SHIFT 18

#define	_EMU_IFS_EM23WAKEUP_DEFAULT 0x00000000UL

#define	_EMU_IFS_EM23WAKEUP_MASK 0x1000000UL

#define	_EMU_IFS_EM23WAKEUP_SHIFT 24

#define	_EMU_IFS_MASK 0xE11FC0FFUL

#define	_EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL

#define	_EMU_IFS_NFETOVERCURRENTLIMIT_MASK 0x20000UL

#define	_EMU_IFS_NFETOVERCURRENTLIMIT_SHIFT 17

#define	_EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL

#define	_EMU_IFS_PFETOVERCURRENTLIMIT_MASK 0x10000UL

#define	_EMU_IFS_PFETOVERCURRENTLIMIT_SHIFT 16

#define	_EMU_IFS_RESETVALUE 0x00000000UL

#define	_EMU_IFS_TEMP_DEFAULT 0x00000000UL

#define	_EMU_IFS_TEMP_MASK 0x20000000UL

#define	_EMU_IFS_TEMP_SHIFT 29

#define	_EMU_IFS_TEMPHIGH_DEFAULT 0x00000000UL

#define	_EMU_IFS_TEMPHIGH_MASK 0x80000000UL

#define	_EMU_IFS_TEMPHIGH_SHIFT 31

#define	_EMU_IFS_TEMPLOW_DEFAULT 0x00000000UL

#define	_EMU_IFS_TEMPLOW_MASK 0x40000000UL

#define	_EMU_IFS_TEMPLOW_SHIFT 30

#define	_EMU_IFS_VMONALTAVDDFALL_DEFAULT 0x00000000UL

#define	_EMU_IFS_VMONALTAVDDFALL_MASK 0x4UL

#define	_EMU_IFS_VMONALTAVDDFALL_SHIFT 2

#define	_EMU_IFS_VMONALTAVDDRISE_DEFAULT 0x00000000UL

#define	_EMU_IFS_VMONALTAVDDRISE_MASK 0x8UL

#define	_EMU_IFS_VMONALTAVDDRISE_SHIFT 3

#define	_EMU_IFS_VMONAVDDFALL_DEFAULT 0x00000000UL

#define	_EMU_IFS_VMONAVDDFALL_MASK 0x1UL

#define	_EMU_IFS_VMONAVDDFALL_SHIFT 0

#define	_EMU_IFS_VMONAVDDRISE_DEFAULT 0x00000000UL

#define	_EMU_IFS_VMONAVDDRISE_MASK 0x2UL

#define	_EMU_IFS_VMONAVDDRISE_SHIFT 1

#define	_EMU_IFS_VMONDVDDFALL_DEFAULT 0x00000000UL

#define	_EMU_IFS_VMONDVDDFALL_MASK 0x10UL

#define	_EMU_IFS_VMONDVDDFALL_SHIFT 4

#define	_EMU_IFS_VMONDVDDRISE_DEFAULT 0x00000000UL

#define	_EMU_IFS_VMONDVDDRISE_MASK 0x20UL

#define	_EMU_IFS_VMONDVDDRISE_SHIFT 5

#define	_EMU_IFS_VMONFVDDFALL_DEFAULT 0x00000000UL

#define	_EMU_IFS_VMONFVDDFALL_MASK 0x4000UL

#define	_EMU_IFS_VMONFVDDFALL_SHIFT 14

#define	_EMU_IFS_VMONFVDDRISE_DEFAULT 0x00000000UL

#define	_EMU_IFS_VMONFVDDRISE_MASK 0x8000UL

#define	_EMU_IFS_VMONFVDDRISE_SHIFT 15

#define	_EMU_IFS_VMONIO0FALL_DEFAULT 0x00000000UL

#define	_EMU_IFS_VMONIO0FALL_MASK 0x40UL

#define	_EMU_IFS_VMONIO0FALL_SHIFT 6

#define	_EMU_IFS_VMONIO0RISE_DEFAULT 0x00000000UL

#define	_EMU_IFS_VMONIO0RISE_MASK 0x80UL

#define	_EMU_IFS_VMONIO0RISE_SHIFT 7

#define	_EMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL

#define	_EMU_LOCK_LOCKKEY_LOCK 0x00000000UL

#define	_EMU_LOCK_LOCKKEY_LOCKED 0x00000001UL

#define	_EMU_LOCK_LOCKKEY_MASK 0xFFFFUL

#define	_EMU_LOCK_LOCKKEY_SHIFT 0

#define	_EMU_LOCK_LOCKKEY_UNLOCK 0x0000ADE8UL

#define	_EMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL

#define	_EMU_LOCK_MASK 0x0000FFFFUL

#define	_EMU_LOCK_RESETVALUE 0x00000000UL

#define	_EMU_PWRCFG_MASK 0x0000000FUL

#define	_EMU_PWRCFG_PWRCFG_DCDCTODVDD 0x00000002UL

#define	_EMU_PWRCFG_PWRCFG_DEFAULT 0x00000000UL

#define	_EMU_PWRCFG_PWRCFG_MASK 0xFUL

#define	_EMU_PWRCFG_PWRCFG_SHIFT 0

#define	_EMU_PWRCFG_PWRCFG_STARTUP 0x00000000UL

#define	_EMU_PWRCFG_RESETVALUE 0x00000000UL

#define	_EMU_PWRCTRL_ANASW_AVDD 0x00000000UL

#define	_EMU_PWRCTRL_ANASW_DEFAULT 0x00000000UL

#define	_EMU_PWRCTRL_ANASW_DVDD 0x00000001UL

#define	_EMU_PWRCTRL_ANASW_MASK 0x20UL

#define	_EMU_PWRCTRL_ANASW_SHIFT 5

#define	_EMU_PWRCTRL_MASK 0x00000020UL

#define	_EMU_PWRCTRL_RESETVALUE 0x00000000UL

#define	_EMU_PWRLOCK_LOCKKEY_DEFAULT 0x00000000UL

#define	_EMU_PWRLOCK_LOCKKEY_LOCK 0x00000000UL

#define	_EMU_PWRLOCK_LOCKKEY_LOCKED 0x00000001UL

#define	_EMU_PWRLOCK_LOCKKEY_MASK 0xFFFFUL

#define	_EMU_PWRLOCK_LOCKKEY_SHIFT 0

#define	_EMU_PWRLOCK_LOCKKEY_UNLOCK 0x0000ADE8UL

#define	_EMU_PWRLOCK_LOCKKEY_UNLOCKED 0x00000000UL

#define	_EMU_PWRLOCK_MASK 0x0000FFFFUL

#define	_EMU_PWRLOCK_RESETVALUE 0x00000000UL

#define	_EMU_RAM0CTRL_MASK 0x0000000FUL

#define	_EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO4 0x0000000FUL

#define	_EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO4 0x0000000EUL

#define	_EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO4 0x0000000CUL

#define	_EMU_RAM0CTRL_RAMPOWERDOWN_BLK4 0x00000008UL

#define	_EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT 0x00000000UL

#define	_EMU_RAM0CTRL_RAMPOWERDOWN_MASK 0xFUL

#define	_EMU_RAM0CTRL_RAMPOWERDOWN_NONE 0x00000000UL

#define	_EMU_RAM0CTRL_RAMPOWERDOWN_SHIFT 0

#define	_EMU_RAM0CTRL_RESETVALUE 0x00000000UL

#define	_EMU_STATUS_EM4IORET_DEFAULT 0x00000000UL

#define	_EMU_STATUS_EM4IORET_DISABLED 0x00000000UL

#define	_EMU_STATUS_EM4IORET_ENABLED 0x00000001UL

#define	_EMU_STATUS_EM4IORET_MASK 0x100000UL

#define	_EMU_STATUS_EM4IORET_SHIFT 20

#define	_EMU_STATUS_MASK 0x0010011FUL

#define	_EMU_STATUS_RESETVALUE 0x00000000UL

#define	_EMU_STATUS_VMONALTAVDD_DEFAULT 0x00000000UL

#define	_EMU_STATUS_VMONALTAVDD_MASK 0x4UL

#define	_EMU_STATUS_VMONALTAVDD_SHIFT 2

#define	_EMU_STATUS_VMONAVDD_DEFAULT 0x00000000UL

#define	_EMU_STATUS_VMONAVDD_MASK 0x2UL

#define	_EMU_STATUS_VMONAVDD_SHIFT 1

#define	_EMU_STATUS_VMONDVDD_DEFAULT 0x00000000UL

#define	_EMU_STATUS_VMONDVDD_MASK 0x8UL

#define	_EMU_STATUS_VMONDVDD_SHIFT 3

#define	_EMU_STATUS_VMONFVDD_DEFAULT 0x00000000UL

#define	_EMU_STATUS_VMONFVDD_MASK 0x100UL

#define	_EMU_STATUS_VMONFVDD_SHIFT 8

#define	_EMU_STATUS_VMONIO0_DEFAULT 0x00000000UL

#define	_EMU_STATUS_VMONIO0_MASK 0x10UL

#define	_EMU_STATUS_VMONIO0_SHIFT 4

#define	_EMU_STATUS_VMONRDY_DEFAULT 0x00000000UL

#define	_EMU_STATUS_VMONRDY_MASK 0x1UL

#define	_EMU_STATUS_VMONRDY_SHIFT 0

#define	_EMU_TEMP_MASK 0x000000FFUL

#define	_EMU_TEMP_RESETVALUE 0x00000000UL

#define	_EMU_TEMP_TEMP_DEFAULT 0x00000000UL

#define	_EMU_TEMP_TEMP_MASK 0xFFUL

#define	_EMU_TEMP_TEMP_SHIFT 0

#define	_EMU_TEMPLIMITS_EM4WUEN_DEFAULT 0x00000000UL

#define	_EMU_TEMPLIMITS_EM4WUEN_MASK 0x10000UL

#define	_EMU_TEMPLIMITS_EM4WUEN_SHIFT 16

#define	_EMU_TEMPLIMITS_MASK 0x0001FFFFUL

#define	_EMU_TEMPLIMITS_RESETVALUE 0x0000FF00UL

#define	_EMU_TEMPLIMITS_TEMPHIGH_DEFAULT 0x000000FFUL

#define	_EMU_TEMPLIMITS_TEMPHIGH_MASK 0xFF00UL

#define	_EMU_TEMPLIMITS_TEMPHIGH_SHIFT 8

#define	_EMU_TEMPLIMITS_TEMPLOW_DEFAULT 0x00000000UL

#define	_EMU_TEMPLIMITS_TEMPLOW_MASK 0xFFUL

#define	_EMU_TEMPLIMITS_TEMPLOW_SHIFT 0

#define	_EMU_TESTLOCK_LOCKKEY_DEFAULT 0x00000000UL

#define	_EMU_TESTLOCK_LOCKKEY_LOCK 0x00000000UL

#define	_EMU_TESTLOCK_LOCKKEY_LOCKED 0x00000001UL

#define	_EMU_TESTLOCK_LOCKKEY_MASK 0xFFFFUL

#define	_EMU_TESTLOCK_LOCKKEY_SHIFT 0

#define	_EMU_TESTLOCK_LOCKKEY_UNLOCK 0x0000ADE8UL

#define	_EMU_TESTLOCK_LOCKKEY_UNLOCKED 0x00000000UL

#define	_EMU_TESTLOCK_MASK 0x0000FFFFUL

#define	_EMU_TESTLOCK_RESETVALUE 0x00000000UL

#define	_EMU_VMONALTAVDDCTRL_EN_DEFAULT 0x00000000UL

#define	_EMU_VMONALTAVDDCTRL_EN_MASK 0x1UL

#define	_EMU_VMONALTAVDDCTRL_EN_SHIFT 0

#define	_EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT 0x00000000UL

#define	_EMU_VMONALTAVDDCTRL_FALLWU_MASK 0x8UL

#define	_EMU_VMONALTAVDDCTRL_FALLWU_SHIFT 3

#define	_EMU_VMONALTAVDDCTRL_MASK 0x0000FF0DUL

#define	_EMU_VMONALTAVDDCTRL_RESETVALUE 0x00000000UL

#define	_EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT 0x00000000UL

#define	_EMU_VMONALTAVDDCTRL_RISEWU_MASK 0x4UL

#define	_EMU_VMONALTAVDDCTRL_RISEWU_SHIFT 2

#define	_EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT 0x00000000UL

#define	_EMU_VMONALTAVDDCTRL_THRESCOARSE_MASK 0xF000UL

#define	_EMU_VMONALTAVDDCTRL_THRESCOARSE_SHIFT 12

#define	_EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT 0x00000000UL

#define	_EMU_VMONALTAVDDCTRL_THRESFINE_MASK 0xF00UL

#define	_EMU_VMONALTAVDDCTRL_THRESFINE_SHIFT 8

#define	_EMU_VMONAVDDCTRL_EN_DEFAULT 0x00000000UL

#define	_EMU_VMONAVDDCTRL_EN_MASK 0x1UL

#define	_EMU_VMONAVDDCTRL_EN_SHIFT 0

#define	_EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT 0x00000000UL

#define	_EMU_VMONAVDDCTRL_FALLTHRESCOARSE_MASK 0xF000UL

#define	_EMU_VMONAVDDCTRL_FALLTHRESCOARSE_SHIFT 12

#define	_EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT 0x00000000UL

#define	_EMU_VMONAVDDCTRL_FALLTHRESFINE_MASK 0xF00UL

#define	_EMU_VMONAVDDCTRL_FALLTHRESFINE_SHIFT 8

#define	_EMU_VMONAVDDCTRL_FALLWU_DEFAULT 0x00000000UL

#define	_EMU_VMONAVDDCTRL_FALLWU_MASK 0x8UL

#define	_EMU_VMONAVDDCTRL_FALLWU_SHIFT 3

#define	_EMU_VMONAVDDCTRL_MASK 0x00FFFF0DUL

#define	_EMU_VMONAVDDCTRL_RESETVALUE 0x00000000UL

#define	_EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT 0x00000000UL

#define	_EMU_VMONAVDDCTRL_RISETHRESCOARSE_MASK 0xF00000UL

#define	_EMU_VMONAVDDCTRL_RISETHRESCOARSE_SHIFT 20

#define	_EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT 0x00000000UL

#define	_EMU_VMONAVDDCTRL_RISETHRESFINE_MASK 0xF0000UL

#define	_EMU_VMONAVDDCTRL_RISETHRESFINE_SHIFT 16

#define	_EMU_VMONAVDDCTRL_RISEWU_DEFAULT 0x00000000UL

#define	_EMU_VMONAVDDCTRL_RISEWU_MASK 0x4UL

#define	_EMU_VMONAVDDCTRL_RISEWU_SHIFT 2

#define	_EMU_VMONDVDDCTRL_EN_DEFAULT 0x00000000UL

#define	_EMU_VMONDVDDCTRL_EN_MASK 0x1UL

#define	_EMU_VMONDVDDCTRL_EN_SHIFT 0

#define	_EMU_VMONDVDDCTRL_FALLWU_DEFAULT 0x00000000UL

#define	_EMU_VMONDVDDCTRL_FALLWU_MASK 0x8UL

#define	_EMU_VMONDVDDCTRL_FALLWU_SHIFT 3

#define	_EMU_VMONDVDDCTRL_MASK 0x0000FF0DUL

#define	_EMU_VMONDVDDCTRL_RESETVALUE 0x00000000UL

#define	_EMU_VMONDVDDCTRL_RISEWU_DEFAULT 0x00000000UL

#define	_EMU_VMONDVDDCTRL_RISEWU_MASK 0x4UL

#define	_EMU_VMONDVDDCTRL_RISEWU_SHIFT 2

#define	_EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT 0x00000000UL

#define	_EMU_VMONDVDDCTRL_THRESCOARSE_MASK 0xF000UL

#define	_EMU_VMONDVDDCTRL_THRESCOARSE_SHIFT 12

#define	_EMU_VMONDVDDCTRL_THRESFINE_DEFAULT 0x00000000UL

#define	_EMU_VMONDVDDCTRL_THRESFINE_MASK 0xF00UL

#define	_EMU_VMONDVDDCTRL_THRESFINE_SHIFT 8

#define	_EMU_VMONIO0CTRL_EN_DEFAULT 0x00000000UL

#define	_EMU_VMONIO0CTRL_EN_MASK 0x1UL

#define	_EMU_VMONIO0CTRL_EN_SHIFT 0

#define	_EMU_VMONIO0CTRL_FALLWU_DEFAULT 0x00000000UL

#define	_EMU_VMONIO0CTRL_FALLWU_MASK 0x8UL

#define	_EMU_VMONIO0CTRL_FALLWU_SHIFT 3

#define	_EMU_VMONIO0CTRL_MASK 0x0000FF1DUL

#define	_EMU_VMONIO0CTRL_RESETVALUE 0x00000000UL

#define	_EMU_VMONIO0CTRL_RETDIS_DEFAULT 0x00000000UL

#define	_EMU_VMONIO0CTRL_RETDIS_MASK 0x10UL

#define	_EMU_VMONIO0CTRL_RETDIS_SHIFT 4

#define	_EMU_VMONIO0CTRL_RISEWU_DEFAULT 0x00000000UL

#define	_EMU_VMONIO0CTRL_RISEWU_MASK 0x4UL

#define	_EMU_VMONIO0CTRL_RISEWU_SHIFT 2

#define	_EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT 0x00000000UL

#define	_EMU_VMONIO0CTRL_THRESCOARSE_MASK 0xF000UL

#define	_EMU_VMONIO0CTRL_THRESCOARSE_SHIFT 12

#define	_EMU_VMONIO0CTRL_THRESFINE_DEFAULT 0x00000000UL

#define	_EMU_VMONIO0CTRL_THRESFINE_MASK 0xF00UL

#define	_EMU_VMONIO0CTRL_THRESFINE_SHIFT 8

#define	EMU_BIASCONF_GMCEM23 (0x1UL << 4)

#define	EMU_BIASCONF_GMCEM23_DEFAULT ( _EMU_BIASCONF_GMCEM23_DEFAULT << 4)

#define	EMU_BIASCONF_LPEM01 (0x1UL << 3)

#define	EMU_BIASCONF_LPEM01_DEFAULT ( _EMU_BIASCONF_LPEM01_DEFAULT << 3)

#define	EMU_BIASCONF_LPEM23 (0x1UL << 7)

#define	EMU_BIASCONF_LPEM23_DEFAULT ( _EMU_BIASCONF_LPEM23_DEFAULT << 7)

#define	EMU_BIASCONF_NADUTYEM01 (0x1UL << 2)

#define	EMU_BIASCONF_NADUTYEM01_DEFAULT ( _EMU_BIASCONF_NADUTYEM01_DEFAULT << 2)

#define	EMU_BIASCONF_NADUTYEM23 (0x1UL << 6)

#define	EMU_BIASCONF_NADUTYEM23_DEFAULT ( _EMU_BIASCONF_NADUTYEM23_DEFAULT << 6)

#define	EMU_BIASCONF_UADUTYEM23 (0x1UL << 5)

#define	EMU_BIASCONF_UADUTYEM23_DEFAULT ( _EMU_BIASCONF_UADUTYEM23_DEFAULT << 5)

#define	EMU_BIASTESTCTRL_BIAS_RIP_RESET (0x1UL << 3)

#define	EMU_BIASTESTCTRL_BIAS_RIP_RESET_DEFAULT ( _EMU_BIASTESTCTRL_BIAS_RIP_RESET_DEFAULT << 3)

#define	EMU_CMD_EM4UNLATCH (0x1UL << 0)

#define	EMU_CMD_EM4UNLATCH_DEFAULT ( _EMU_CMD_EM4UNLATCH_DEFAULT << 0)

#define	EMU_CTRL_EM2BLOCK (0x1UL << 1)

#define	EMU_CTRL_EM2BLOCK_DEFAULT ( _EMU_CTRL_EM2BLOCK_DEFAULT << 1)

#define	EMU_DCDCCLIMCTRL_BYPLIMEN (0x1UL << 13)

#define	EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT ( _EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT << 13)

#define	EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT ( _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT << 8)

#define	EMU_DCDCCTRL_DCDCMODE_BYPASS ( _EMU_DCDCCTRL_DCDCMODE_BYPASS << 0)

#define	EMU_DCDCCTRL_DCDCMODE_DEFAULT ( _EMU_DCDCCTRL_DCDCMODE_DEFAULT << 0)

#define	EMU_DCDCCTRL_DCDCMODE_LOWNOISE ( _EMU_DCDCCTRL_DCDCMODE_LOWNOISE << 0)

#define	EMU_DCDCCTRL_DCDCMODE_LOWPOWER ( _EMU_DCDCCTRL_DCDCMODE_LOWPOWER << 0)

#define	EMU_DCDCCTRL_DCDCMODE_OFF ( _EMU_DCDCCTRL_DCDCMODE_OFF << 0)

#define	EMU_DCDCCTRL_DCDCMODEEM23 (0x1UL << 4)

#define	EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT ( _EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT << 4)

#define	EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER ( _EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER << 4)

#define	EMU_DCDCCTRL_DCDCMODEEM23_EM23SW ( _EMU_DCDCCTRL_DCDCMODEEM23_EM23SW << 4)

#define	EMU_DCDCCTRL_DCDCMODEEM4 (0x1UL << 5)

#define	EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT ( _EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT << 5)

#define	EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER ( _EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER << 5)

#define	EMU_DCDCCTRL_DCDCMODEEM4_EM4SW ( _EMU_DCDCCTRL_DCDCMODEEM4_EM4SW << 5)

#define	EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT ( _EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT << 20)

#define	EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT ( _EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT << 24)

#define	EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT ( _EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT << 28)

#define	EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT ( _EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT << 0)

#define	EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT ( _EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT << 4)

#define	EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT ( _EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT << 12)

#define	EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT ( _EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT << 0)

#define	EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT ( _EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT << 24)

#define	EMU_DCDCLNVCTRL_LNATT (0x1UL << 1)

#define	EMU_DCDCLNVCTRL_LNATT_DEFAULT ( _EMU_DCDCLNVCTRL_LNATT_DEFAULT << 1)

#define	EMU_DCDCLNVCTRL_LNATT_DIV3 ( _EMU_DCDCLNVCTRL_LNATT_DIV3 << 1)

#define	EMU_DCDCLNVCTRL_LNATT_DIV6 ( _EMU_DCDCLNVCTRL_LNATT_DIV6 << 1)

#define	EMU_DCDCLNVCTRL_LNVREF_DEFAULT ( _EMU_DCDCLNVCTRL_LNVREF_DEFAULT << 8)

#define	EMU_DCDCLPCTRL_LPBLANK_DEFAULT ( _EMU_DCDCLPCTRL_LPBLANK_DEFAULT << 25)

#define	EMU_DCDCLPCTRL_LPCMPHYSSEL_DEFAULT ( _EMU_DCDCLPCTRL_LPCMPHYSSEL_DEFAULT << 12)

#define	EMU_DCDCLPCTRL_LPVREFDUTYEN (0x1UL << 24)

#define	EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT ( _EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT << 24)

#define	EMU_DCDCLPVCTRL_LPATT (0x1UL << 0)

#define	EMU_DCDCLPVCTRL_LPATT_DEFAULT ( _EMU_DCDCLPVCTRL_LPATT_DEFAULT << 0)

#define	EMU_DCDCLPVCTRL_LPATT_DIV4 ( _EMU_DCDCLPVCTRL_LPATT_DIV4 << 0)

#define	EMU_DCDCLPVCTRL_LPATT_DIV8 ( _EMU_DCDCLPVCTRL_LPATT_DIV8 << 0)

#define	EMU_DCDCLPVCTRL_LPVREF_DEFAULT ( _EMU_DCDCLPVCTRL_LPVREF_DEFAULT << 1)

#define	EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT ( _EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT << 16)

#define	EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT ( _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT << 24)

#define	EMU_DCDCMISCCTRL_LNFORCECCM (0x1UL << 0)

#define	EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT ( _EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT << 0)

#define	EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT ( _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT << 20)

#define	EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS0 ( _EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS0 << 28)

#define	EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS1 ( _EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS1 << 28)

#define	EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS2 ( _EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS2 << 28)

#define	EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS3 ( _EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS3 << 28)

#define	EMU_DCDCMISCCTRL_LPCMPBIAS_DEFAULT ( _EMU_DCDCMISCCTRL_LPCMPBIAS_DEFAULT << 28)

#define	EMU_DCDCMISCCTRL_NFETCNT_DEFAULT ( _EMU_DCDCMISCCTRL_NFETCNT_DEFAULT << 12)

#define	EMU_DCDCMISCCTRL_PFETCNT_DEFAULT ( _EMU_DCDCMISCCTRL_PFETCNT_DEFAULT << 8)

#define	EMU_DCDCSYNC_DCDCCTRLBUSY (0x1UL << 0)

#define	EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT ( _EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT << 0)

#define	EMU_DCDCTIMING_BYPWAIT_DEFAULT ( _EMU_DCDCTIMING_BYPWAIT_DEFAULT << 20)

#define	EMU_DCDCTIMING_COMPENPRCHGEN (0x1UL << 11)

#define	EMU_DCDCTIMING_COMPENPRCHGEN_DEFAULT ( _EMU_DCDCTIMING_COMPENPRCHGEN_DEFAULT << 11)

#define	EMU_DCDCTIMING_DUTYSCALE_DEFAULT ( _EMU_DCDCTIMING_DUTYSCALE_DEFAULT << 29)

#define	EMU_DCDCTIMING_LNWAIT_DEFAULT ( _EMU_DCDCTIMING_LNWAIT_DEFAULT << 12)

#define	EMU_DCDCTIMING_LPINITWAIT_DEFAULT ( _EMU_DCDCTIMING_LPINITWAIT_DEFAULT << 0)

#define	EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT ( _EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT << 8)

#define	EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT ( _EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT << 4)

#define	EMU_EM4CTRL_EM4ENTRY_DEFAULT ( _EMU_EM4CTRL_EM4ENTRY_DEFAULT << 16)

#define	EMU_EM4CTRL_EM4IORETMODE_DEFAULT ( _EMU_EM4CTRL_EM4IORETMODE_DEFAULT << 4)

#define	EMU_EM4CTRL_EM4IORETMODE_DISABLE ( _EMU_EM4CTRL_EM4IORETMODE_DISABLE << 4)

#define	EMU_EM4CTRL_EM4IORETMODE_EM4EXIT ( _EMU_EM4CTRL_EM4IORETMODE_EM4EXIT << 4)

#define	EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH ( _EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH << 4)

#define	EMU_EM4CTRL_EM4STATE (0x1UL << 0)

#define	EMU_EM4CTRL_EM4STATE_DEFAULT ( _EMU_EM4CTRL_EM4STATE_DEFAULT << 0)

#define	EMU_EM4CTRL_EM4STATE_EM4H ( _EMU_EM4CTRL_EM4STATE_EM4H << 0)

#define	EMU_EM4CTRL_EM4STATE_EM4S ( _EMU_EM4CTRL_EM4STATE_EM4S << 0)

#define	EMU_EM4CTRL_RETAINLFRCO (0x1UL << 1)

#define	EMU_EM4CTRL_RETAINLFRCO_DEFAULT ( _EMU_EM4CTRL_RETAINLFRCO_DEFAULT << 1)

#define	EMU_EM4CTRL_RETAINLFXO (0x1UL << 2)

#define	EMU_EM4CTRL_RETAINLFXO_DEFAULT ( _EMU_EM4CTRL_RETAINLFXO_DEFAULT << 2)

#define	EMU_EM4CTRL_RETAINULFRCO (0x1UL << 3)

#define	EMU_EM4CTRL_RETAINULFRCO_DEFAULT ( _EMU_EM4CTRL_RETAINULFRCO_DEFAULT << 3)

#define	EMU_IEN_DCDCINBYPASS (0x1UL << 20)

#define	EMU_IEN_DCDCINBYPASS_DEFAULT ( _EMU_IEN_DCDCINBYPASS_DEFAULT << 20)

#define	EMU_IEN_DCDCLNRUNNING (0x1UL << 19)

#define	EMU_IEN_DCDCLNRUNNING_DEFAULT ( _EMU_IEN_DCDCLNRUNNING_DEFAULT << 19)

#define	EMU_IEN_DCDCLPRUNNING (0x1UL << 18)

#define	EMU_IEN_DCDCLPRUNNING_DEFAULT ( _EMU_IEN_DCDCLPRUNNING_DEFAULT << 18)

#define	EMU_IEN_EM23WAKEUP (0x1UL << 24)

#define	EMU_IEN_EM23WAKEUP_DEFAULT ( _EMU_IEN_EM23WAKEUP_DEFAULT << 24)

#define	EMU_IEN_NFETOVERCURRENTLIMIT (0x1UL << 17)

#define	EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT ( _EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT << 17)

#define	EMU_IEN_PFETOVERCURRENTLIMIT (0x1UL << 16)

#define	EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT ( _EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT << 16)

#define	EMU_IEN_TEMP (0x1UL << 29)

#define	EMU_IEN_TEMP_DEFAULT ( _EMU_IEN_TEMP_DEFAULT << 29)

#define	EMU_IEN_TEMPHIGH (0x1UL << 31)

#define	EMU_IEN_TEMPHIGH_DEFAULT ( _EMU_IEN_TEMPHIGH_DEFAULT << 31)

#define	EMU_IEN_TEMPLOW (0x1UL << 30)

#define	EMU_IEN_TEMPLOW_DEFAULT ( _EMU_IEN_TEMPLOW_DEFAULT << 30)

#define	EMU_IEN_VMONALTAVDDFALL (0x1UL << 2)

#define	EMU_IEN_VMONALTAVDDFALL_DEFAULT ( _EMU_IEN_VMONALTAVDDFALL_DEFAULT << 2)

#define	EMU_IEN_VMONALTAVDDRISE (0x1UL << 3)

#define	EMU_IEN_VMONALTAVDDRISE_DEFAULT ( _EMU_IEN_VMONALTAVDDRISE_DEFAULT << 3)

#define	EMU_IEN_VMONAVDDFALL (0x1UL << 0)

#define	EMU_IEN_VMONAVDDFALL_DEFAULT ( _EMU_IEN_VMONAVDDFALL_DEFAULT << 0)

#define	EMU_IEN_VMONAVDDRISE (0x1UL << 1)

#define	EMU_IEN_VMONAVDDRISE_DEFAULT ( _EMU_IEN_VMONAVDDRISE_DEFAULT << 1)

#define	EMU_IEN_VMONDVDDFALL (0x1UL << 4)

#define	EMU_IEN_VMONDVDDFALL_DEFAULT ( _EMU_IEN_VMONDVDDFALL_DEFAULT << 4)

#define	EMU_IEN_VMONDVDDRISE (0x1UL << 5)

#define	EMU_IEN_VMONDVDDRISE_DEFAULT ( _EMU_IEN_VMONDVDDRISE_DEFAULT << 5)

#define	EMU_IEN_VMONFVDDFALL (0x1UL << 14)

#define	EMU_IEN_VMONFVDDFALL_DEFAULT ( _EMU_IEN_VMONFVDDFALL_DEFAULT << 14)

#define	EMU_IEN_VMONFVDDRISE (0x1UL << 15)

#define	EMU_IEN_VMONFVDDRISE_DEFAULT ( _EMU_IEN_VMONFVDDRISE_DEFAULT << 15)

#define	EMU_IEN_VMONIO0FALL (0x1UL << 6)

#define	EMU_IEN_VMONIO0FALL_DEFAULT ( _EMU_IEN_VMONIO0FALL_DEFAULT << 6)

#define	EMU_IEN_VMONIO0RISE (0x1UL << 7)

#define	EMU_IEN_VMONIO0RISE_DEFAULT ( _EMU_IEN_VMONIO0RISE_DEFAULT << 7)

#define	EMU_IF_DCDCINBYPASS (0x1UL << 20)

#define	EMU_IF_DCDCINBYPASS_DEFAULT ( _EMU_IF_DCDCINBYPASS_DEFAULT << 20)

#define	EMU_IF_DCDCLNRUNNING (0x1UL << 19)

#define	EMU_IF_DCDCLNRUNNING_DEFAULT ( _EMU_IF_DCDCLNRUNNING_DEFAULT << 19)

#define	EMU_IF_DCDCLPRUNNING (0x1UL << 18)

#define	EMU_IF_DCDCLPRUNNING_DEFAULT ( _EMU_IF_DCDCLPRUNNING_DEFAULT << 18)

#define	EMU_IF_EM23WAKEUP (0x1UL << 24)

#define	EMU_IF_EM23WAKEUP_DEFAULT ( _EMU_IF_EM23WAKEUP_DEFAULT << 24)

#define	EMU_IF_NFETOVERCURRENTLIMIT (0x1UL << 17)

#define	EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT ( _EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT << 17)

#define	EMU_IF_PFETOVERCURRENTLIMIT (0x1UL << 16)

#define	EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT ( _EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT << 16)

#define	EMU_IF_TEMP (0x1UL << 29)

#define	EMU_IF_TEMP_DEFAULT ( _EMU_IF_TEMP_DEFAULT << 29)

#define	EMU_IF_TEMPHIGH (0x1UL << 31)

#define	EMU_IF_TEMPHIGH_DEFAULT ( _EMU_IF_TEMPHIGH_DEFAULT << 31)

#define	EMU_IF_TEMPLOW (0x1UL << 30)

#define	EMU_IF_TEMPLOW_DEFAULT ( _EMU_IF_TEMPLOW_DEFAULT << 30)

#define	EMU_IF_VMONALTAVDDFALL (0x1UL << 2)

#define	EMU_IF_VMONALTAVDDFALL_DEFAULT ( _EMU_IF_VMONALTAVDDFALL_DEFAULT << 2)

#define	EMU_IF_VMONALTAVDDRISE (0x1UL << 3)

#define	EMU_IF_VMONALTAVDDRISE_DEFAULT ( _EMU_IF_VMONALTAVDDRISE_DEFAULT << 3)

#define	EMU_IF_VMONAVDDFALL (0x1UL << 0)

#define	EMU_IF_VMONAVDDFALL_DEFAULT ( _EMU_IF_VMONAVDDFALL_DEFAULT << 0)

#define	EMU_IF_VMONAVDDRISE (0x1UL << 1)

#define	EMU_IF_VMONAVDDRISE_DEFAULT ( _EMU_IF_VMONAVDDRISE_DEFAULT << 1)

#define	EMU_IF_VMONDVDDFALL (0x1UL << 4)

#define	EMU_IF_VMONDVDDFALL_DEFAULT ( _EMU_IF_VMONDVDDFALL_DEFAULT << 4)

#define	EMU_IF_VMONDVDDRISE (0x1UL << 5)

#define	EMU_IF_VMONDVDDRISE_DEFAULT ( _EMU_IF_VMONDVDDRISE_DEFAULT << 5)

#define	EMU_IF_VMONFVDDFALL (0x1UL << 14)

#define	EMU_IF_VMONFVDDFALL_DEFAULT ( _EMU_IF_VMONFVDDFALL_DEFAULT << 14)

#define	EMU_IF_VMONFVDDRISE (0x1UL << 15)

#define	EMU_IF_VMONFVDDRISE_DEFAULT ( _EMU_IF_VMONFVDDRISE_DEFAULT << 15)

#define	EMU_IF_VMONIO0FALL (0x1UL << 6)

#define	EMU_IF_VMONIO0FALL_DEFAULT ( _EMU_IF_VMONIO0FALL_DEFAULT << 6)

#define	EMU_IF_VMONIO0RISE (0x1UL << 7)

#define	EMU_IF_VMONIO0RISE_DEFAULT ( _EMU_IF_VMONIO0RISE_DEFAULT << 7)

#define	EMU_IFC_DCDCINBYPASS (0x1UL << 20)

#define	EMU_IFC_DCDCINBYPASS_DEFAULT ( _EMU_IFC_DCDCINBYPASS_DEFAULT << 20)

#define	EMU_IFC_DCDCLNRUNNING (0x1UL << 19)

#define	EMU_IFC_DCDCLNRUNNING_DEFAULT ( _EMU_IFC_DCDCLNRUNNING_DEFAULT << 19)

#define	EMU_IFC_DCDCLPRUNNING (0x1UL << 18)

#define	EMU_IFC_DCDCLPRUNNING_DEFAULT ( _EMU_IFC_DCDCLPRUNNING_DEFAULT << 18)

#define	EMU_IFC_EM23WAKEUP (0x1UL << 24)

#define	EMU_IFC_EM23WAKEUP_DEFAULT ( _EMU_IFC_EM23WAKEUP_DEFAULT << 24)

#define	EMU_IFC_NFETOVERCURRENTLIMIT (0x1UL << 17)

#define	EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT ( _EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT << 17)

#define	EMU_IFC_PFETOVERCURRENTLIMIT (0x1UL << 16)

#define	EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT ( _EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT << 16)

#define	EMU_IFC_TEMP (0x1UL << 29)

#define	EMU_IFC_TEMP_DEFAULT ( _EMU_IFC_TEMP_DEFAULT << 29)

#define	EMU_IFC_TEMPHIGH (0x1UL << 31)

#define	EMU_IFC_TEMPHIGH_DEFAULT ( _EMU_IFC_TEMPHIGH_DEFAULT << 31)

#define	EMU_IFC_TEMPLOW (0x1UL << 30)

#define	EMU_IFC_TEMPLOW_DEFAULT ( _EMU_IFC_TEMPLOW_DEFAULT << 30)

#define	EMU_IFC_VMONALTAVDDFALL (0x1UL << 2)

#define	EMU_IFC_VMONALTAVDDFALL_DEFAULT ( _EMU_IFC_VMONALTAVDDFALL_DEFAULT << 2)

#define	EMU_IFC_VMONALTAVDDRISE (0x1UL << 3)

#define	EMU_IFC_VMONALTAVDDRISE_DEFAULT ( _EMU_IFC_VMONALTAVDDRISE_DEFAULT << 3)

#define	EMU_IFC_VMONAVDDFALL (0x1UL << 0)

#define	EMU_IFC_VMONAVDDFALL_DEFAULT ( _EMU_IFC_VMONAVDDFALL_DEFAULT << 0)

#define	EMU_IFC_VMONAVDDRISE (0x1UL << 1)

#define	EMU_IFC_VMONAVDDRISE_DEFAULT ( _EMU_IFC_VMONAVDDRISE_DEFAULT << 1)

#define	EMU_IFC_VMONDVDDFALL (0x1UL << 4)

#define	EMU_IFC_VMONDVDDFALL_DEFAULT ( _EMU_IFC_VMONDVDDFALL_DEFAULT << 4)

#define	EMU_IFC_VMONDVDDRISE (0x1UL << 5)

#define	EMU_IFC_VMONDVDDRISE_DEFAULT ( _EMU_IFC_VMONDVDDRISE_DEFAULT << 5)

#define	EMU_IFC_VMONFVDDFALL (0x1UL << 14)

#define	EMU_IFC_VMONFVDDFALL_DEFAULT ( _EMU_IFC_VMONFVDDFALL_DEFAULT << 14)

#define	EMU_IFC_VMONFVDDRISE (0x1UL << 15)

#define	EMU_IFC_VMONFVDDRISE_DEFAULT ( _EMU_IFC_VMONFVDDRISE_DEFAULT << 15)

#define	EMU_IFC_VMONIO0FALL (0x1UL << 6)

#define	EMU_IFC_VMONIO0FALL_DEFAULT ( _EMU_IFC_VMONIO0FALL_DEFAULT << 6)

#define	EMU_IFC_VMONIO0RISE (0x1UL << 7)

#define	EMU_IFC_VMONIO0RISE_DEFAULT ( _EMU_IFC_VMONIO0RISE_DEFAULT << 7)

#define	EMU_IFS_DCDCINBYPASS (0x1UL << 20)

#define	EMU_IFS_DCDCINBYPASS_DEFAULT ( _EMU_IFS_DCDCINBYPASS_DEFAULT << 20)

#define	EMU_IFS_DCDCLNRUNNING (0x1UL << 19)

#define	EMU_IFS_DCDCLNRUNNING_DEFAULT ( _EMU_IFS_DCDCLNRUNNING_DEFAULT << 19)

#define	EMU_IFS_DCDCLPRUNNING (0x1UL << 18)

#define	EMU_IFS_DCDCLPRUNNING_DEFAULT ( _EMU_IFS_DCDCLPRUNNING_DEFAULT << 18)

#define	EMU_IFS_EM23WAKEUP (0x1UL << 24)

#define	EMU_IFS_EM23WAKEUP_DEFAULT ( _EMU_IFS_EM23WAKEUP_DEFAULT << 24)

#define	EMU_IFS_NFETOVERCURRENTLIMIT (0x1UL << 17)

#define	EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT ( _EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT << 17)

#define	EMU_IFS_PFETOVERCURRENTLIMIT (0x1UL << 16)

#define	EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT ( _EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT << 16)

#define	EMU_IFS_TEMP (0x1UL << 29)

#define	EMU_IFS_TEMP_DEFAULT ( _EMU_IFS_TEMP_DEFAULT << 29)

#define	EMU_IFS_TEMPHIGH (0x1UL << 31)

#define	EMU_IFS_TEMPHIGH_DEFAULT ( _EMU_IFS_TEMPHIGH_DEFAULT << 31)

#define	EMU_IFS_TEMPLOW (0x1UL << 30)

#define	EMU_IFS_TEMPLOW_DEFAULT ( _EMU_IFS_TEMPLOW_DEFAULT << 30)

#define	EMU_IFS_VMONALTAVDDFALL (0x1UL << 2)

#define	EMU_IFS_VMONALTAVDDFALL_DEFAULT ( _EMU_IFS_VMONALTAVDDFALL_DEFAULT << 2)

#define	EMU_IFS_VMONALTAVDDRISE (0x1UL << 3)

#define	EMU_IFS_VMONALTAVDDRISE_DEFAULT ( _EMU_IFS_VMONALTAVDDRISE_DEFAULT << 3)

#define	EMU_IFS_VMONAVDDFALL (0x1UL << 0)

#define	EMU_IFS_VMONAVDDFALL_DEFAULT ( _EMU_IFS_VMONAVDDFALL_DEFAULT << 0)

#define	EMU_IFS_VMONAVDDRISE (0x1UL << 1)

#define	EMU_IFS_VMONAVDDRISE_DEFAULT ( _EMU_IFS_VMONAVDDRISE_DEFAULT << 1)

#define	EMU_IFS_VMONDVDDFALL (0x1UL << 4)

#define	EMU_IFS_VMONDVDDFALL_DEFAULT ( _EMU_IFS_VMONDVDDFALL_DEFAULT << 4)

#define	EMU_IFS_VMONDVDDRISE (0x1UL << 5)

#define	EMU_IFS_VMONDVDDRISE_DEFAULT ( _EMU_IFS_VMONDVDDRISE_DEFAULT << 5)

#define	EMU_IFS_VMONFVDDFALL (0x1UL << 14)

#define	EMU_IFS_VMONFVDDFALL_DEFAULT ( _EMU_IFS_VMONFVDDFALL_DEFAULT << 14)

#define	EMU_IFS_VMONFVDDRISE (0x1UL << 15)

#define	EMU_IFS_VMONFVDDRISE_DEFAULT ( _EMU_IFS_VMONFVDDRISE_DEFAULT << 15)

#define	EMU_IFS_VMONIO0FALL (0x1UL << 6)

#define	EMU_IFS_VMONIO0FALL_DEFAULT ( _EMU_IFS_VMONIO0FALL_DEFAULT << 6)

#define	EMU_IFS_VMONIO0RISE (0x1UL << 7)

#define	EMU_IFS_VMONIO0RISE_DEFAULT ( _EMU_IFS_VMONIO0RISE_DEFAULT << 7)

#define	EMU_LOCK_LOCKKEY_DEFAULT ( _EMU_LOCK_LOCKKEY_DEFAULT << 0)

#define	EMU_LOCK_LOCKKEY_LOCK ( _EMU_LOCK_LOCKKEY_LOCK << 0)

#define	EMU_LOCK_LOCKKEY_LOCKED ( _EMU_LOCK_LOCKKEY_LOCKED << 0)

#define	EMU_LOCK_LOCKKEY_UNLOCK ( _EMU_LOCK_LOCKKEY_UNLOCK << 0)

#define	EMU_LOCK_LOCKKEY_UNLOCKED ( _EMU_LOCK_LOCKKEY_UNLOCKED << 0)

#define	EMU_PWRCFG_PWRCFG_DCDCTODVDD ( _EMU_PWRCFG_PWRCFG_DCDCTODVDD << 0)

#define	EMU_PWRCFG_PWRCFG_DEFAULT ( _EMU_PWRCFG_PWRCFG_DEFAULT << 0)

#define	EMU_PWRCFG_PWRCFG_STARTUP ( _EMU_PWRCFG_PWRCFG_STARTUP << 0)

#define	EMU_PWRCTRL_ANASW (0x1UL << 5)

#define	EMU_PWRCTRL_ANASW_AVDD ( _EMU_PWRCTRL_ANASW_AVDD << 5)

#define	EMU_PWRCTRL_ANASW_DEFAULT ( _EMU_PWRCTRL_ANASW_DEFAULT << 5)

#define	EMU_PWRCTRL_ANASW_DVDD ( _EMU_PWRCTRL_ANASW_DVDD << 5)

#define	EMU_PWRLOCK_LOCKKEY_DEFAULT ( _EMU_PWRLOCK_LOCKKEY_DEFAULT << 0)

#define	EMU_PWRLOCK_LOCKKEY_LOCK ( _EMU_PWRLOCK_LOCKKEY_LOCK << 0)

#define	EMU_PWRLOCK_LOCKKEY_LOCKED ( _EMU_PWRLOCK_LOCKKEY_LOCKED << 0)

#define	EMU_PWRLOCK_LOCKKEY_UNLOCK ( _EMU_PWRLOCK_LOCKKEY_UNLOCK << 0)

#define	EMU_PWRLOCK_LOCKKEY_UNLOCKED ( _EMU_PWRLOCK_LOCKKEY_UNLOCKED << 0)

#define	EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO4 ( _EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO4 << 0)

#define	EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO4 ( _EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO4 << 0)

#define	EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO4 ( _EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO4 << 0)

#define	EMU_RAM0CTRL_RAMPOWERDOWN_BLK4 ( _EMU_RAM0CTRL_RAMPOWERDOWN_BLK4 << 0)

#define	EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT ( _EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT << 0)

#define	EMU_RAM0CTRL_RAMPOWERDOWN_NONE ( _EMU_RAM0CTRL_RAMPOWERDOWN_NONE << 0)

#define	EMU_STATUS_EM4IORET (0x1UL << 20)

#define	EMU_STATUS_EM4IORET_DEFAULT ( _EMU_STATUS_EM4IORET_DEFAULT << 20)

#define	EMU_STATUS_EM4IORET_DISABLED ( _EMU_STATUS_EM4IORET_DISABLED << 20)

#define	EMU_STATUS_EM4IORET_ENABLED ( _EMU_STATUS_EM4IORET_ENABLED << 20)

#define	EMU_STATUS_VMONALTAVDD (0x1UL << 2)

#define	EMU_STATUS_VMONALTAVDD_DEFAULT ( _EMU_STATUS_VMONALTAVDD_DEFAULT << 2)

#define	EMU_STATUS_VMONAVDD (0x1UL << 1)

#define	EMU_STATUS_VMONAVDD_DEFAULT ( _EMU_STATUS_VMONAVDD_DEFAULT << 1)

#define	EMU_STATUS_VMONDVDD (0x1UL << 3)

#define	EMU_STATUS_VMONDVDD_DEFAULT ( _EMU_STATUS_VMONDVDD_DEFAULT << 3)

#define	EMU_STATUS_VMONFVDD (0x1UL << 8)

#define	EMU_STATUS_VMONFVDD_DEFAULT ( _EMU_STATUS_VMONFVDD_DEFAULT << 8)

#define	EMU_STATUS_VMONIO0 (0x1UL << 4)

#define	EMU_STATUS_VMONIO0_DEFAULT ( _EMU_STATUS_VMONIO0_DEFAULT << 4)

#define	EMU_STATUS_VMONRDY (0x1UL << 0)

#define	EMU_STATUS_VMONRDY_DEFAULT ( _EMU_STATUS_VMONRDY_DEFAULT << 0)

#define	EMU_TEMP_TEMP_DEFAULT ( _EMU_TEMP_TEMP_DEFAULT << 0)

#define	EMU_TEMPLIMITS_EM4WUEN (0x1UL << 16)

#define	EMU_TEMPLIMITS_EM4WUEN_DEFAULT ( _EMU_TEMPLIMITS_EM4WUEN_DEFAULT << 16)

#define	EMU_TEMPLIMITS_TEMPHIGH_DEFAULT ( _EMU_TEMPLIMITS_TEMPHIGH_DEFAULT << 8)

#define	EMU_TEMPLIMITS_TEMPLOW_DEFAULT ( _EMU_TEMPLIMITS_TEMPLOW_DEFAULT << 0)

#define	EMU_TESTLOCK_LOCKKEY_DEFAULT ( _EMU_TESTLOCK_LOCKKEY_DEFAULT << 0)

#define	EMU_TESTLOCK_LOCKKEY_LOCK ( _EMU_TESTLOCK_LOCKKEY_LOCK << 0)

#define	EMU_TESTLOCK_LOCKKEY_LOCKED ( _EMU_TESTLOCK_LOCKKEY_LOCKED << 0)

#define	EMU_TESTLOCK_LOCKKEY_UNLOCK ( _EMU_TESTLOCK_LOCKKEY_UNLOCK << 0)

#define	EMU_TESTLOCK_LOCKKEY_UNLOCKED ( _EMU_TESTLOCK_LOCKKEY_UNLOCKED << 0)

#define	EMU_VMONALTAVDDCTRL_EN (0x1UL << 0)

#define	EMU_VMONALTAVDDCTRL_EN_DEFAULT ( _EMU_VMONALTAVDDCTRL_EN_DEFAULT << 0)

#define	EMU_VMONALTAVDDCTRL_FALLWU (0x1UL << 3)

#define	EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT ( _EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT << 3)

#define	EMU_VMONALTAVDDCTRL_RISEWU (0x1UL << 2)

#define	EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT ( _EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT << 2)

#define	EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT ( _EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT << 12)

#define	EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT ( _EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT << 8)

#define	EMU_VMONAVDDCTRL_EN (0x1UL << 0)

#define	EMU_VMONAVDDCTRL_EN_DEFAULT ( _EMU_VMONAVDDCTRL_EN_DEFAULT << 0)

#define	EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT ( _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT << 12)

#define	EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT ( _EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT << 8)

#define	EMU_VMONAVDDCTRL_FALLWU (0x1UL << 3)

#define	EMU_VMONAVDDCTRL_FALLWU_DEFAULT ( _EMU_VMONAVDDCTRL_FALLWU_DEFAULT << 3)

#define	EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT ( _EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT << 20)

#define	EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT ( _EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT << 16)

#define	EMU_VMONAVDDCTRL_RISEWU (0x1UL << 2)

#define	EMU_VMONAVDDCTRL_RISEWU_DEFAULT ( _EMU_VMONAVDDCTRL_RISEWU_DEFAULT << 2)

#define	EMU_VMONDVDDCTRL_EN (0x1UL << 0)

#define	EMU_VMONDVDDCTRL_EN_DEFAULT ( _EMU_VMONDVDDCTRL_EN_DEFAULT << 0)

#define	EMU_VMONDVDDCTRL_FALLWU (0x1UL << 3)

#define	EMU_VMONDVDDCTRL_FALLWU_DEFAULT ( _EMU_VMONDVDDCTRL_FALLWU_DEFAULT << 3)

#define	EMU_VMONDVDDCTRL_RISEWU (0x1UL << 2)

#define	EMU_VMONDVDDCTRL_RISEWU_DEFAULT ( _EMU_VMONDVDDCTRL_RISEWU_DEFAULT << 2)

#define	EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT ( _EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT << 12)

#define	EMU_VMONDVDDCTRL_THRESFINE_DEFAULT ( _EMU_VMONDVDDCTRL_THRESFINE_DEFAULT << 8)

#define	EMU_VMONIO0CTRL_EN (0x1UL << 0)

#define	EMU_VMONIO0CTRL_EN_DEFAULT ( _EMU_VMONIO0CTRL_EN_DEFAULT << 0)

#define	EMU_VMONIO0CTRL_FALLWU (0x1UL << 3)

#define	EMU_VMONIO0CTRL_FALLWU_DEFAULT ( _EMU_VMONIO0CTRL_FALLWU_DEFAULT << 3)

#define	EMU_VMONIO0CTRL_RETDIS (0x1UL << 4)

#define	EMU_VMONIO0CTRL_RETDIS_DEFAULT ( _EMU_VMONIO0CTRL_RETDIS_DEFAULT << 4)

#define	EMU_VMONIO0CTRL_RISEWU (0x1UL << 2)

#define	EMU_VMONIO0CTRL_RISEWU_DEFAULT ( _EMU_VMONIO0CTRL_RISEWU_DEFAULT << 2)

#define	EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT ( _EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT << 12)

#define	EMU_VMONIO0CTRL_THRESFINE_DEFAULT ( _EMU_VMONIO0CTRL_THRESFINE_DEFAULT << 8)

Macro Definition Documentation

#define _EMU_BIASCONF_GMCEM23_DEFAULT 0x00000001UL

Mode DEFAULT for EMU_BIASCONF

Definition at line 1069 of file efr32fg1p_emu.h .

#define _EMU_BIASCONF_GMCEM23_MASK 0x10UL

Bit mask for EMU_GMCEM23

Definition at line 1068 of file efr32fg1p_emu.h .

#define _EMU_BIASCONF_GMCEM23_SHIFT 4

Shift value for EMU_GMCEM23

Definition at line 1067 of file efr32fg1p_emu.h .

#define _EMU_BIASCONF_LPEM01_DEFAULT 0x00000001UL

Mode DEFAULT for EMU_BIASCONF

Definition at line 1064 of file efr32fg1p_emu.h .

#define _EMU_BIASCONF_LPEM01_MASK 0x8UL

Bit mask for EMU_LPEM01

Definition at line 1063 of file efr32fg1p_emu.h .

EMU Bit FieldsDevices > EMU

Macros

Macro Definition Documentation