Allows the user to specify direct mode parameters using sl_rail_config_direct_mode().

Public Attributes#

bool
sync_rx

Enable synchronous RX DOUT using DCLK vs.

bool
sync_tx

Enable synchronous TX DIN using DCLK vs.

uint8_t
dout_port

RX Data output (DOUT) GPIO port.

uint8_t
dout_pin

RX Data output (DOUT) GPIO pin.

uint8_t
dclk_port

Data clock (DCLK) GPIO port.

uint8_t
dclk_pin

Data clock (DCLK) GPIO pin.

uint8_t
din_port

TX Data input (DIN) GPIO port.

uint8_t
din_pin

TX Data input (DIN) GPIO pin.

uint8_t
reserved_0

Reserved for future use.

uint8_t
reserved_1

Reserved for future use.

uint8_t
reserved_2

Reserved for future use.

Public Attribute Documentation#

sync_rx#

bool sl_rail_direct_mode_config_t::sync_rx

Enable synchronous RX DOUT using DCLK vs.

asynchronous RX DOUT.


sync_tx#

bool sl_rail_direct_mode_config_t::sync_tx

Enable synchronous TX DIN using DCLK vs.

asynchronous TX DIN.


dout_port#

uint8_t sl_rail_direct_mode_config_t::dout_port

RX Data output (DOUT) GPIO port.


dout_pin#

uint8_t sl_rail_direct_mode_config_t::dout_pin

RX Data output (DOUT) GPIO pin.


dclk_port#

uint8_t sl_rail_direct_mode_config_t::dclk_port

Data clock (DCLK) GPIO port.

Only used in synchronous mode.


dclk_pin#

uint8_t sl_rail_direct_mode_config_t::dclk_pin

Data clock (DCLK) GPIO pin.

Only used in synchronous mode.


din_port#

uint8_t sl_rail_direct_mode_config_t::din_port

TX Data input (DIN) GPIO port.


din_pin#

uint8_t sl_rail_direct_mode_config_t::din_pin

TX Data input (DIN) GPIO pin.


reserved_0#

uint8_t sl_rail_direct_mode_config_t::reserved_0

Reserved for future use.


reserved_1#

uint8_t sl_rail_direct_mode_config_t::reserved_1

Reserved for future use.


reserved_2#

uint8_t sl_rail_direct_mode_config_t::reserved_2

Reserved for future use.