M4 Power Modes#

The SiWG917 M4 supports several M4 power-save states - PS4/PS3/PS2 Active/Standby/Sleep, PS1, Deep-sleep (PS0) - all managed by the Power Manager.

Refer to the M4 Power States section in Low-Power Application Note to understand in detail on the powersave modes of SiWG917 M4.

M4 Sleep#

PS1 is an ultra-low-power state where the CPU is OFF and only limited peripherals remain powered. These peripherals must be configured before entry. See Section 5.5.4.4 PS1 of the SiWG917 data sheet`.
Standby: The CPU is clock-gated; peripheral, General-Purpose Input/Output (GPIO), and Static RAM (SRAM) availability match the respective Active state. Any enabled interrupt can wake the CPU back to Active.
Sleep: The CPU is power-gated; RAM may be retained (size is configurable). Separate Sleep variants exist corresponding to PS4/PS3/PS2.
Deep-Sleep / Shutdown (PS0): The CPU is power-gated, and RAM is not retained.
Entering Low Power: Transitions from Active to Standby/Sleep/PS0 are initiated by software:
- sl_si91x_power_manager_request_ps1_state -> Wait For Interrupt (WFI) for Standby
- sl_si91x_power_manager_sleep() for Sleep
- sl_si91x_power_manager_add_ps_requirement(SL_SI91X_POWER_MANAGER_PS0) for Deep-Sleep
- sl_si91x_power_manager_request_ps1_state() for PS1. This API does not directly transition the system to the PS1 state. After the request is issued, the system transitions to PS1 automatically only from the PS2 state when it becomes idle.

See the API Reference Guide for Power Manager usage and functions information.

M4 Wake-Up#

Transitions from Standby or Sleep to the Active state occur in response to a previously enabled wake-up interrupt — such as a General-Purpose GPIO event, Real-Time Clock (RTC) alarm, or timer trigger. The device returns from PS0 to Active state through a software reset sequence. After wake-up, software restores clocks and returns to the last active state.

See the 4. Power Manager with Tickless Idle section in Power Manager Application Note to understand in detail about the Tickless Idle implementation for the power state transitions.