General-Purpose Input/Output (GPIO) Configuration#

Basic Configuration#

This section describes the process of configuring any General-Purpose Input/Output (GPIO) pin from any power domain to operate in GPIO mode and defining its direction (input or output) using the PORT and PIN identifiers.

GPIO Port and Pin Mapping#

The SiWG917 device uses a structured mapping of GPIO instances to ports and pin numbers as shown below:

GPIO Instance

GPIO Port

GPIO Pin Range

System-on-Chip/High-Performance (SoC/HP) GPIO

SL_GPIO_PORT_A

6–15

SL_GPIO_PORT_B

16–31

SL_GPIO_PORT_C

32–47

SL_GPIO_PORT_D

48–57

Ultra-Low-Power (ULP) GPIO Instance

SL_GPIO_ULP_PORT

0–11

Ultra-Ultra-Low-Power (UULP) GPIO Instance

SL_GPIO_UULP_PORT

0–3

Notes:

  • GPIO pins 0–5 are not available for general-purpose use. They are internally assigned to FLASH or PSRAM interfaces, depending on the Orderable Part Numbers (OPN).

  • All HP instance GPIOs (GPIO 6–57) can also be accessed using port as SL_GPIO_PORT_A and pin same as the GPIO number.

  • All pins shown in the GPIO Pin Range may not be available. See the GPIO Categories section for precise availability.

Example: Basic Configuration#

The following example demonstrates how to configure GPIO 10 as an output pin using the GPIO driver APIs.

#include "sl_si91x_driver_gpio.h"
#include "sl_gpio_board.h"

static sl_si91x_gpio_pin_config_t sl_gpio_pin_config = {
    { SL_SI91X_GPIO_10_PORT, SL_SI91X_GPIO_10_PIN },
    OUTPUT
};  /* Configuration for GPIO 10 */

status = sl_gpio_driver_init();               /* GPIO clock initialization */
status = sl_gpio_set_configuration(sl_gpio_pin_config);  /* Configure GPIO 10 as OUTPUT */

Note:
The sl_gpio_set_configuration() API internally handles PAD selection, resistor enable (REN), and MODE configuration for the specified GPIO pin.

Advanced Configuration#

This section describes how to configure the advanced GPIO features such as pull-up/down states, drive strength, slew rate, and interrupt settings for both HP and ULP domains.
Example API calls are provided to demonstrate typical usage.

Note:
The advanced configurations such as pull-up/down states, drive strength and slew rate are PAD-specific features and are applicable only for HP and ULP GPIOs but not for UULP GPIOs.

Pull-up / Pull-down / Hi-Z / Repeater Configuration#

GPIO pins can be configured with specific default states when disabled or not actively driven. The available options include:

  • Pull-up – Internal pull-up resistor enabled

  • Pull-down – Internal pull-down resistor enabled

  • Hi-Z – High-impedance state (no pull)

  • Repeater – Retains last known logic level

The following APIs are used to configure the default disable state of GPIOs in the HP and ULP domains.

/* Configure GPIO default state as Hi-Z for HP Domain */
status = sl_si91x_gpio_driver_select_pad_driver_disable_state(
             sl_gpio_pin_config.port_pin.pin,
             (sl_si91x_gpio_driver_disable_state_t)GPIO_HZ);

/* Configure GPIO default state as Hi-Z for ULP Domain */
status = sl_si91x_gpio_driver_select_ulp_pad_driver_disable_state(
             sl_gpio_pin_config.port_pin.pin,
             (sl_si91x_gpio_driver_disable_state_t)GPIO_HZ);

Note:
Use the appropriate API depending on the GPIO’s power domain (HP or ULP).

Drive Strength Configuration#

GPIO drive strength determines the maximum current a pin can source or sink.

The SiWG917 supports four configurable drive strengths:
2 mA, 4 mA, 8 mA, and 12 mA.

These options are available for both HP and ULP domain GPIOs.

/* Configure drive strength to 4 mA for HP Domain */
sl_si91x_gpio_driver_select_pad_driver_strength(
    sl_gpio_pin_config.port_pin.pin,
    (sl_si91x_gpio_driver_strength_select_t)GPIO_FOUR_MILLI_AMPS);

/* Configure drive strength to 4 mA for ULP Domain */
sl_si91x_gpio_driver_select_ulp_pad_driver_strength(
    sl_gpio_pin_config.port_pin.pin,
    (sl_si91x_gpio_driver_strength_select_t)GPIO_FOUR_MILLI_AMPS);

Slew Rate Configuration#

The slew rate controls the transition speed of a GPIO signal between logic levels.

Reducing the slew rate helps minimize electromagnetic interference (EMI) and signal ringing, while higher slew rates are beneficial for high-speed digital interfaces.

This feature is supported for both HP and ULP GPIO domains.

/* Configure slew rate as 'Low' for HP Domain */
sl_gpio_driver_set_slew_rate(
    sl_gpio_pin_config.port_pin.port,
    (sl_si91x_gpio_slew_rate_t)GPIO_SR_LOW,
    (sl_si91x_gpio_slew_rate_t)GPIO_SR_LOW);

/* Configure slew rate as 'Low' for ULP Domain */
sl_si91x_gpio_driver_select_ulp_pad_slew_rate(
    sl_gpio_pin_config.port_pin.pin,
    (sl_si91x_gpio_slew_rate_t)GPIO_SR_LOW);

GPIO Interrupt#

This section describes the interrupts supported across the HP, ULP, and UULP GPIO instances in the SiWG917 device.

It includes both pin and group interrupt configurations, along with API usage examples.

HP GPIO#

Pin Interrupts#

  • Number of IRQs: 8 (EGPIO_PIN_0_IRQn to EGPIO_PIN_7_IRQn)

  • Mapping: One GPIO per pin interrupt

  • Supported Trigger Types:

    • Rising Edge

    • Falling Edge

    • Level Low

    • Level High

Example: Configure a GPIO Pin Interrupt (HP Domain)#

status = sl_gpio_driver_configure_interrupt(
             &sl_gpio_pin_config.port_pin,
             INT_CH,
             (sl_gpio_interrupt_flag_t)SL_GPIO_INTERRUPT_RISE_EDGE,
             (sl_gpio_irq_callback_t)&gpio_pin_interrupt0_callback,
             INTR_NO);

Group Interrupts#

  • Number of IRQs: 2 (EGPIO_GROUP_0_IRQn, EGPIO_GROUP_1_IRQn)

  • Group Size: Up to 8 GPIOs per group

  • Features:

    • Supports AND/OR logic per group

    • Level/Edge selection available per group

    • Unique polarity(Level Low/High) configuration for each GPIO

Example: Configure a GPIO Group Interrupt (HP Domain)#

static sl_si91x_gpio_group_interrupt_config_t config_grp_int;
static sl_si91x_gpio_pin_config_t sl_gpio_pin_config[NUMBER_OF_PINS] = {
    { { SL_SI91X_GPIO_8_PORT, GPIO_PIN_NUMBER8 }, GPIO_INPUT },
    { { SL_SI91X_GPIO_9_PORT, GPIO_PIN_NUMBER9 }, GPIO_INPUT },
};

/* Define group parameters */
uint8_t group_pins[PIN_COUNT] = { sl_gpio_pin_config[0].port_pin.pin,
                                  sl_gpio_pin_config[1].port_pin.pin };
uint8_t group_port[PIN_COUNT] = { sl_gpio_pin_config[0].port_pin.port,
                                  sl_gpio_pin_config[1].port_pin.port };
uint8_t group_pol[PIN_COUNT]  = { GPIO_POLARITY_0, GPIO_POLARITY_0 };

/* Configure group interrupt parameters */
config_grp_int.grp_interrupt     = GROUP_INT_1;
config_grp_int.grp_interrupt_cnt = GRP_COUNT;
config_grp_int.and_or            = GPIO_AND;
config_grp_int.level_edge        = GPIO_LEVEL;
memcpy(config_grp_int.grp_interrupt_pin, group_pins, PIN_COUNT);
memcpy(config_grp_int.grp_interrupt_port, group_port, PIN_COUNT);
memcpy(config_grp_int.grp_interrupt_pol, group_pol, PIN_COUNT);

/* Initialize group interrupt */
status = sl_si91x_gpio_driver_configure_group_interrupt(
             &config_grp_int,
             (sl_gpio_irq_callback_t)&gpio_group_interrupt0_callback);

For the example code in Wiseconnect Software Development Kit (SDK), see the SL GPIO GROUP EXAMPLE.

ULP GPIO#

Pin Interrupts#

  • Number of IRQs: 1 (ULP_EGPIO_PIN_IRQn)

  • Mapping: One shared IRQ for up to 8 ULP GPIOs

  • Status Reporting: Provides indication of which pins triggered the interrupt

  • Supported Trigger Types:

    • Rising Edge

    • Falling Edge

    • Level Low

    • Level High

Example: Configure a GPIO Pin Interrupt (ULP Domain)#

status = sl_gpio_driver_configure_interrupt(
             &sl_gpio_pin_config.port_pin,
             ULP_INT_CH,
             (sl_gpio_interrupt_flag_t)SL_GPIO_INTERRUPT_RISE_EDGE,
             (sl_gpio_irq_callback_t)&gpio_pin_interrupt0_callback,
             ULP_INTR_NO);

Group Interrupts#

  • Number of IRQs: 1 (ULP_EGPIO_GROUP_IRQn)

  • Group Size: Up to 8 GPIOs per group

  • Features:

    • Supports AND/OR logic per group

    • Unique polarity option per GPIO

    • Level/Edge selection available per group

Example: Configure a GPIO Group Interrupt (ULP Domain)#

static sl_si91x_gpio_pin_config_t sl_gpio_pin_config[NUMBER_OF_PINS] = {
    { { SL_SI91X_ULP_GPIO_8_PORT, SL_SI91X_ULP_GPIO_8_PIN }, GPIO_INPUT },
    { { SL_SI91X_ULP_GPIO_10_PORT, SL_SI91X_ULP_GPIO_10_PIN }, GPIO_INPUT },
};

static sl_si91x_gpio_group_interrupt_config_t ulp_config_grp_int;

/* Define group parameters */
uint8_t ulp_group_port[PIN_COUNT] = { sl_gpio_pin_config[0].port_pin.port,
                                      sl_gpio_pin_config[1].port_pin.port };
uint8_t ulp_group_pins[PIN_COUNT] = { sl_gpio_pin_config[0].port_pin.pin,
                                      sl_gpio_pin_config[1].port_pin.pin };
uint8_t ulp_group_pol[PIN_COUNT]  = { GPIO_POLARITY_0, GPIO_POLARITY_0 };

/* Configure group interrupt parameters */
ulp_config_grp_int.grp_interrupt     = GROUP_INT_1;
ulp_config_grp_int.grp_interrupt_cnt = GRP_COUNT;
ulp_config_grp_int.and_or            = GPIO_AND;
ulp_config_grp_int.level_edge        = GPIO_LEVEL;
memcpy(ulp_config_grp_int.grp_interrupt_pin, ulp_group_pins, PIN_COUNT);
memcpy(ulp_config_grp_int.grp_interrupt_port, ulp_group_port, PIN_COUNT);
memcpy(ulp_config_grp_int.grp_interrupt_pol, ulp_group_pol, PIN_COUNT);

/* Initialize ULP group interrupt */
status = sl_si91x_gpio_driver_configure_ulp_group_interrupt(
             &ulp_config_grp_int,
             (sl_gpio_irq_callback_t)&gpio_ulp_group_interrupt_callback);

UULP GPIO#

Pin Interrupts#

  • Number of IRQs: 1 (NPSS_TO_MCU_GPIO_INTR_IRQn)

  • Mapping: One shared IRQ for up to 4 UULP GPIOs

  • Status Reporting: Provides indiciation of which pins triggered the interrupt

  • Supported Trigger Types:

    • Rising Edge

    • Falling Edge

    • Level Low

    • Level High

Example: Configure a GPIO Pin Interrupt (UULP Domain)#

status = sl_gpio_driver_configure_interrupt(
             &sl_gpio_pin_config1.port_pin,
             UULP_GPIO_INTR_2,
             (sl_gpio_interrupt_flag_t)SL_GPIO_INTERRUPT_RISE_EDGE,
             (sl_gpio_irq_callback_t)&gpio_uulp_pin_interrupt_callback,
             INTR_NO);

Summary#

The following table summarizes the GPIO interrupt configurations and capabilities across the HP, ULP, and UULP domains of the SiWG917 device.

GPIO Type

Pin IRQs

Group IRQs

Pins per Pin IRQ

Pins per Group IRQ

Logic Options

Trigger Types

Unique Polarity / Level-Edge Config

HP GPIO

8 (EGPIO_PIN_0–7_IRQn)

2 (EGPIO_GROUP_0–1_IRQn)

1

Up to 8

AND / OR

Rise, Fall, Level Low, Level High

Yes

ULP GPIO

1 (ULP_EGPIO_PIN_IRQn)

1 (ULP_EGPIO_GROUP_IRQn)

Up to 8

Up to 8

AND / OR

Rise, Fall, Level Low, Level High

Yes

UULP GPIO

1 (NPSS_TO_MCU_GPIO_INTR_IRQn)

—

Up to 4

—

—

Rise, Fall, Level Low, Level High

—

GPIO Interrupt Handling Flow#

This section explains how GPIO interrupt events are configured, triggered, and serviced within the SiWG917 system.
The interrupt handling flow applies to HP, ULP, and UULP GPIO instances, with domain-specific variations in interrupt sources and handlers.

Overview#

When a GPIO interrupt occurs, the event follows a defined sequence from hardware trigger detection to application-level handling.
The general flow is as follows:

  1. Interrupt Configuration
    Each GPIO pin or group is configured for the desired trigger type (rising, falling, level high, or level low) using the driver APIs.

  2. Event Detection
    When the configured edge or level condition is met, the corresponding interrupt flag is set in the GPIO interrupt controller.

  3. NVIC Invocation
    The Nested Vectored Interrupt Controller (NVIC) receives the interrupt request and invokes the registered ISR (Interrupt Service Routine) or callback.

  4. Callback Execution
    The driver executes the user-defined callback function, allowing application logic to handle the event.

  5. Interrupt Clearance
    The interrupt flag is cleared in hardware to acknowledge and re-enable subsequent events.

Typical Interrupt Handling Sequence#

The following pseudocode illustrates the typical steps involved in configuring and servicing a GPIO interrupt.

/* Step 1: Define GPIO pin configuration */
sl_si91x_gpio_pin_config_t gpio_intr_pin = {
    { SL_SI91X_GPIO_15_PORT, SL_SI91X_GPIO_15_PIN },
    INPUT
};

/* Step 2: Initialize GPIO driver */
status = sl_gpio_driver_init();

/* Step 3: Configure pin as input with interrupt on rising edge */
status = sl_gpio_driver_configure_interrupt(
             &gpio_intr_pin.port_pin,
             INT_CH,
             (sl_gpio_interrupt_flag_t)SL_GPIO_INTERRUPT_RISE_EDGE,
             (sl_gpio_irq_callback_t)&gpio_pin_interrupt_callback,
             INTR_NO);

/* Step 4: Define callback function */
void gpio_pin_interrupt_callback(void)
{
    /* Application-specific interrupt handler logic */
    toggle_led();
    clear_interrupt_flag();
}

Note:
The interrupt handler (gpio_pin_interrupt_callback) executes in interrupt context. Keep it short and non-blocking. For longer tasks, defer processing to a background thread or task scheduler.

Group Interrupt Handling#

When multiple GPIOs are grouped, any pin (or all, depending on the AND/OR configuration) can trigger the group interrupt.
The driver provides a mechanism to check which specific pins caused the interrupt event.

Example: Group Interrupt Callback Implementation#

void gpio_group_interrupt_callback(void)
{
    /* Read interrupt status register */
    uint32_t status = sl_gpio_get_group_interrupt_status(GROUP_INT_1);

    /* Check which pin(s) triggered the event */
    if (status & GPIO_PIN_MASK_8)
        handle_gpio8_event();

    if (status & GPIO_PIN_MASK_9)
        handle_gpio9_event();

    /* Clear group interrupt flags */
    sl_gpio_clear_group_interrupt(GROUP_INT_1);
}

Tip: Use group interrupts to efficiently handle multiple related signals (e.g., sensor interfaces or button arrays) while minimizing CPU wake-ups and ISR overhead.

Interrupt Handling Recommendations#

The following table summarizes the key design recommendations for effective GPIO interrupt handling on the SiWG917 device.

Design Aspect

Recommendation

ISR Duration

Keep ISR execution short; offload complex tasks to threads or queues.

Debouncing

Use hardware or software debounce for mechanical inputs.

Priority

Assign appropriate NVIC priorities to ensure critical GPIOs are serviced promptly.

Power Modes

Use UULP GPIOs for wake-up functionality when the SoC is in sleep.

Clearing Flags

Always clear interrupt status bits at the end of ISR execution.