Special GPIO Use Cases#

In addition to standard general-purpose input/output functionality, certain GPIO pins on the SiWG917 device are dedicated for specialized hardware functions that interface directly with critical subsystems.
These pins should be used with care, as they are essential for RF control, debugging, and system programming.

This section highlights three commonly used special GPIO applications:

1. External RF Switch Control

2. NWP (Network Processor) Debug Prints

3. ISP (In-System Programming) Interface

External RF Switch Control#

Many SiWG917-based designs use an external RF front-end module (RFFE) or RF switch to control the routing of RF signals between transmission paths (e.g., WLAN TX/RX or BLE operation).

To facilitate this, specific GPIOs from the ULP (Ultra-Low Power) domain are dedicated for RF switch control.

The SiWG917 reserves the following GPIOs for this purpose:

Notes:

• These GPIOs are dedicated for RF switch control and should not be repurposed for general I/O or alternate peripheral functions in the application.

• This section is not applicable to ICs with internal switch.

NWP Debug Prints#

The Network Wireless Processor (NWP) subsystem in the SiWG917 provides a UART-based debug interface that outputs runtime diagnostic messages, system logs, and status information. These logs are highly valuable during troubleshooting NWP issues.

Dedicated GPIOs are mapped to serve as UART TX/RX lines for the NWP’s debug output.

Usage#

• Debug print output for NWP is available as part of Extended custom feature bitmap provided during NWP init (sl_net_init). For more information please refer SL_SI91X_EXT_FEAT_UART_SEL_FOR_DEBUG_PRINTS in extended custom feature bitmap and SL_SI91X_ULP_GPIO9_FOR_UART2_TX in config feature bitmap

• When NWP UART debug mode is enabled, the corresponding GPIOs cannot be used for other peripheral or GPIO functions.

ISP (In-System Programming) Interface#

The SiWG917 supports In-System Programming (ISP) for firmware flashing, updates, and system recovery.
During ISP mode, the SoC bootloader communicates with the host via UART, SPI, or SDIO interfaces.

Specific GPIOs are used to implement these communication interfaces and to signal entry into ISP mode.

Note:

• Users should keep GPIO_8 (RX) and GPIO_9 (TX) available for UART ISP functionality, ensuring a reliable fallback method for firmware programming or recovery — especially when security features are enabled or JTAG access is disabled.

• Refer to Datasheet for detailed pin mapping of UART/SPI/SDIO

Typical Use Cases#

• Firmware download or upgrade during production.

• Field recovery for corrupted or failed firmware images.

• Maintenance or recovery access when JTAG is locked by security settings.

ISP Entry and Control#

To enter ISP mode, a dedicated boot configuration GPIO (GPIO_34) is used.
Pulling this pin low during device reset forces the SoC into ISP boot mode.

DEBUG Interface#

The SiWG917 supports both Serial Wire Debug (SWD) and JTAG interfaces for debug and development purposes.
These interfaces allow developers to perform on-chip debugging, firmware programming, and real-time system monitoring.

Both SWD and JTAG provide access to the internal ARM® Cortex®-M4 core for debugging firmware execution and inspecting memory/registers during runtime.
By default, the debug interface is enabled on power-up unless explicitly disabled in firmware or through fuse configuration.

Debug Pin Mapping#

Notes:

• Debug access is lost when the firmware reconfigures SWD or JTAG pins for GPIO functionality.

• To restore debug access, the firmware must reconfigure the pins back to SWD/JTAG mode, or the device must be booted into ISP mode.