General Purpose Input/Output (GPIO) Fundamentals#

Overview#

The SiWG917 device provides a flexible General Purpose Input/Output (GPIO) interface that supports multiple operating domains, drive strengths, and configurable electrical characteristics.

This section outlines GPIO categorization based on power domains and details the electrical features supported by each GPIO type.

GPIO Categories#

GPIOs on the SiWG917 are classified into three categories, depending on the power domain in which they operate.
This classification helps optimize power consumption and maintain functional flexibility across different power states.

SoC / HP GPIO#

These GPIOs belong to the High-Performance (HP) domain and are typically used for high-speed peripheral interfaces and general I/O operations. They remain active when the main System-on-Chip (SoC) power domain is enabled.

  • Count: 30 GPIOs

  • GPIO Range: 6–12, 15, 25–34, 46–57

  • Power Domain: IO_VDD_1 / IO_VDD_2 / IO_VDD_3

Ultra-Low-Power (ULP) GPIO#

The Ultra-Low Power (ULP) GPIOs operate in a reduced-power domain, while minimizing power consumption. These GPIOs are ideal for maintaining low-power wake-up or sensor/peripheral interfaces.

  • Count: 11 GPIOs

  • GPIO Range: 0–2, 4–11

  • Power Domain: ULP_IO_VDD

UULP GPIO#

The Ultra-Ultra-Low Power (UULP) GPIOs operate directly from a lower voltage domain and are available even in the lowest power states. They are designed for essential always-on control functions, such as external interrupt detection or wake-up from deep sleep.

  • Count: 4 GPIOs

  • GPIO Range: 0–3

  • Power Domain: UULP_VBATT_1

GPIO Electrical Characteristics#

Each GPIO pin supports a range of configurable electrical parameters that allow developers to modify the signal characteristics as per system requirements and interface standards.
This is applicable for SoC/HP and ULP GPIOs.

Parameter

Description

Options

Drive Strength

Output current capability

2 mA, 4 mA, 8 mA, 12 mA

Slew Rate

Controls transition speed of output signal

Fast / Slow

Pull States

Configurable internal pull settings

Hi-Z, Pull-up, Pull-down, Repeater

Input Type

Input stage configuration

Schmitt Trigger input for noise immunity

Notes:

  • SoC / HP GPIOs and ULP GPIOs can be shared between the M4 core and the NWP subsystem.

  • The PAD configuration defines specific electrical features and determines which processor owns or controls the pin.