Flash Memory#

A Flash memory is a non-volatile storage device that retains data even after the power is turned off, however, it may need power during the storage process.

Based on the SiWG917 package configuration (OPN), the SiWG917 can have 4 MB or 8 MB of "In-package" or "Stacked" Quad SPI flash. In addition, SiWG917 supports external flash options (up to 16 MB). Quad SPI or QSPI is the interface to access Flash.

Features:

• The first 68 KB is reserved in In-package flash.

• The page size is 256 bytes. Flash program command is executed based on a byte or page (256 bytes).

• Flash erase is executed based on a sector (4 K-byte) or a 32 KB block (32 K-byte), or a whole chip.

SiWG917 Flash Modes:

• Common Flash - Single flash is used for both the NWP and M4 processors

• Dual Flash – Separate flash for NWP and M4 processors

The following are the SiWG917 available OPNs and the possible flash modes.

Note: Refer to UG574: SiWx917 SoC Manufacturing Utility User Guide for steps on how to select common-flash or dual-flash mode in a No Stacked Flash OPN.

Common Flash#

In this flash mode, a single flash memory is shared between M4 and NWP. The two processors access flash memory over dedicated Quad-SPI (QSPI) with an arbiter in between that helps in arbitration for flash accesses.

Though the flash memory is shared between M4 and NWP, only NWP performs low-level flash write operations while M4 supports only flash read operation on the flash memory. For operations such as erasing and writing, M4 requests NWP through a command and sends the data for the write or erase operation.

The available flash options are:

In-Package Flash OPN:

• In-Package Flash (4 MB)

• In-Package Flash (8 MB)

No In-Package Flash OPN:

• External Flash (4 MB)

• External Flash (8 MB)

Access Diagram (In-Package Flash)#

Access Diagram (No In-Package Flash)#

Note: By default, External PSRAM is on Pins: (52 to 57). To configure it to Pins: (46 to 51), refer to the UG574: SiWx917 SoC Manufacturing Utility User Guide.

Memory Map (4 MB)#

Note: In the linker file, the application execution start address 0x8172000 will be mentioned as the ORIGIN address.

Memory Map (8 MB)#

Note: In the linker file, the application execution start address 0x8202000 will be mentioned as the ORIGIN address.

Dual Flash#

In this flash mode, the NWP and the M4 processors have separate flash memory and have dedicated QSPI controllers to access the flash memory. From their respective QSPI interfaces, the processors perform operations such as flash erase, write, and read only.

With an In-package flash device, the in-package flash is dedicated to NWP while the external flash is dedicated to M4.

In the No In-package flash device, one of the external flash is dedicated to NWP while the other external flash is dedicated to M4.

The available flash options are as follows:

In-package Flash OPN

• NWP flash: In-package Flash (4 MB or 8 MB)

• M4 flash: External Flash (8 MB)

No In-package Flash OPN

• NWP Flash: External Flash (4 MB or 8 MB)

• M4 Flash: External Flash (8 MB)

Access Diagram (In-Package Flash)#

Access Diagram (No In-Package Flash)#

Memory Map – NWP (4 MB)#

Memory Map – NWP (8 MB)#

Note:

• The NWP Firmware Image is 1.6 MB, though there is a space of 3.87 MB available in the NWP Memory Map (8 MB).

• The left-over space in the NWP dedicated Flash cannot be used for M4.

Memory Map – M4 (8 MB)#

Note: In the linker file, the application execution start address 0x8012000 will be mentioned as the ORIGIN address.