Structure to hold the port and pin configurations for different events.

This structure defines the configuration parameters for the QEI GPIO's. It includes settings for the port, pin, mux, and pad for DIR, IDX, PHASEA, PHASEB

Public Attributes#

sl_gpio_pin_config_t
dir

DIR GPIO configuration.

sl_gpio_pin_config_t
idx

IDX GPIO configuration.

sl_gpio_pin_config_t
phasea

PHASE_A GPIO configuration.

sl_gpio_pin_config_t
phaseb

PHASE_B GPIO configuration.

Public Attribute Documentation#

dir#

sl_gpio_pin_config_t sl_qei_init_t::dir

DIR GPIO configuration.


idx#

sl_gpio_pin_config_t sl_qei_init_t::idx

IDX GPIO configuration.


phasea#

sl_gpio_pin_config_t sl_qei_init_t::phasea

PHASE_A GPIO configuration.


phaseb#

sl_gpio_pin_config_t sl_qei_init_t::phaseb

PHASE_B GPIO configuration.