Clock Configuration for Series 2#

Zephyr uses the Clock Control driver at runtime to enable clock sources and retrieve clock frequencies. On Silicon Labs Series 2 devices, Clock Control is implemented using the Silicon Labs Clock Manager. Changing clock sources at runtime using the Clock Control API is currently not supported.

The Silicon Labs Clock Manager also handles oscillator initialization and clock tree configuration on boot. In Zephyr, the Clock Manager is configured through Devicetree.

By default, the SoC-level Devicetree configuration for the clock tree configures HFRCODPLL free-running at 19 MHz as the default high-frequency oscillator, and LFRCO at 32,768 Hz as the default low-frequency oscillator. Board-level Devicetree configuration can override this based on the availability of external oscillators.

Most Series 2 devices use a synchronous clock tree, and the radio must be clocked at the HFXO frequency. As a result, most boards enable the HFXO and configure the DPLL to lock to twice the HFXO frequency (for example, 76.8 MHz for a 38.4 MHz HFXO or 78 MHz for a 39 MHz HFXO).

If an LFXO is available on the board, it is typically enabled and selected as the low-frequency oscillator.

Configuring Clock Sources and Divisors#

All nodes in the clock tree are exposed in the Devicetree clocks node, and their clock source and divisors can be configured using Devicetree properties:

/* Configure FSRCO as the clock source for IADC */
&iadcclk {
    clocks = <&fsrco>:
};
/* Configure a /8 divisor for HCLK */
&hclk {
    clock-div = <8>;
};

Configuring Oscillators#

DPLL#

The DPLL is an optional feature of the HFRCODPLL oscillator on Silicon Labs Series 2 devices. It is automatically enabled when a compatible clock source (HFXO, LFXO, or CLKIN0) is configured for the hfrcodpll node in Devicetree using the clocks property.

Configure the DPLL output frequency using the clock-frequency property, and set the M and N divisors using the dpll-m and dpll-n properties.

The formula for DPLL output frequency is fout=fref*(n+1)/(m+1), where:

• n is between 300 and 4095

• m is between 0 and 4095

Higher values for n and m provide lower jitter but longer lock time.

&hfrcodpll {
    clocks = <&hfxo>;
    clock-frequency = <DT_FREQ_M(78)>;
    dpll-n = <3839>;
    dpll-m = <1919>;
    dpll-edge = "fall";
    dpll-lock = "phase";
    dpll-autorecover;
};

See the Devicetree binding for the HFRCODPLL for documentation of all available configuration options.

LFRCO Precision Mode#

Most Series 2 devices support a precision mode for the LFRCO, which periodically synchronizes the low-frequency oscillator to the HFXO. This improves timing accuracy across time and temperature.

Enable precision mode by adding the precision-mode property to the lfrco node in Devicetree:

&lfrco {
    precision-mode;
};

Precision mode enables certain applications that require 500 ppm precision of the low-frequency timer without the use of an external crystal oscillator, such as Bluetooth LE.