Clock Configuration for SiWx91x#

Zephyr uses the Clock Control driver to enable clock sources and retrieve clock frequencies at run time. On Silicon Labs SiWx91x devices, the clock control driver supports core operations such as on, off, get_rate, and set_rate.

By default, the System-on-chip (SoC)–level Devicetree configuration sets the SoC phase-locked loop (PLL) as the core clock source, fixed to 180 MHz. This value is specified in the board DTS files:

&cpu0 {
	clock-frequency = <180000000>;
};

The Interface PLL (INTF PLL) is used as the peripheral clock source. It is fixed at 160 MHz by default and cannot be overridden in the current implementation.

For additional details about the clock system, refer to the Clock Architecture section in the Reference Manual.

Devicetree Clock Binding#

The clock controller is defined using the silabs,siwx91x-clock compatible. Peripherals reference their required clock via:

clocks = <&clock0 SIWX91X_CLK_UART0>;

Each SIWX91X_CLK_* value corresponds to a specific hardware clock gate controlled by the SiWx91x clock subsystem. Peripheral drivers internally manage enabling and disabling these clocks as needed.

Peripheral Clock Usage#

During initialization, peripheral drivers:

  1. Read the clock specifier from Devicetree.

  2. Request clock activation using clock_control_on().

  3. The SiWx91x driver enables the corresponding hardware clock.

This ensures each peripheral receives the correct clock source during operation.