Pin Configuration for SiWx91x#

Pin configuration in Zephyr uses the Pin Control interface. Unlike the distributed approach used in the WiSeConnect SDK, Zephyr centralizes pin configuration. All pinout configuration for digital and analog signals for High-Power (HP) and Ultra-Low-Power (ULP) peripherals is done in the pinctrl0 Devicetree node.

To configure the pinout for a peripheral, create a Devicetree node to represent it:

#include <zephyr/dt-bindings/pinctrl/silabs/siwx91x-pinctrl.h>

&pinctrl0 {
	ulpuart_default: ulpuart_default {
		out {
			pinmux = <ULPUART_TX_ULP11>;
		};

		in {
			pinmux = <ULPUART_RX_ULP9>;
		};
	};
};

The names of pin configurations and groups are arbitrary; however, it is a common convention to name the pin configuration after the peripheral and its pinctrl state (for example, ulpuart and default). Group names typically follow the format group<n>. Groups are useful to apply the same General-Purpose Input/Output (GPIO) properties to multiple pins. The pins property contains a list of the pins and signals to route. Available signals for each device are available from the pinctrl dt-bindings header for the device and generally have the form <peripheral>_<signal>_<pin>.

Device drivers apply pinctrl states associated with the driver as part of initialization or power management resume/suspend:

&ulpuart {
	pinctrl-0 = <&ulpuart_default>;
	pinctrl-names = "default";
};

The pinctrl driver performs the following actions:

• Enables the GPIO pad

• Enables the digital receiver for digital signals

• Configures the GPIO mode to route the signal to the appropriate peripheral

The Devicetree binding header zephyr/dt-bindings/pinctrl/silabs/siwx91x-pinctrl.h defines all valid combinations of signals and pins across HP and ULP GPIO ports.