PCNT - Pulse Counter
Description
Pulse Counter (PCNT) Peripheral API.
This module contains functions to control the PCNT peripheral of Silicon Labs 32-bit MCUs and SoCs. The PCNT decodes incoming pulses. The module has a quadrature mode which may be used to decode the speed and direction of a mechanical shaft.
Data Structures |
|
struct | PCNT_Init_TypeDef |
Initialization structure.
|
|
Functions |
|
uint32_t | PCNT_CounterGet (PCNT_TypeDef *pcnt) |
Default configuration for PCNT initialization structure.
|
|
uint32_t | PCNT_AuxCounterGet (PCNT_TypeDef *pcnt) |
Get auxiliary counter value.
|
|
void | PCNT_CounterReset (PCNT_TypeDef *pcnt) |
Reset PCNT counters and TOP register.
|
|
void | PCNT_CounterTopSet (PCNT_TypeDef *pcnt, uint32_t count, uint32_t top) |
Set the counter and top values.
|
|
void | PCNT_CounterSet (PCNT_TypeDef *pcnt, uint32_t count) |
Set counter value.
|
|
void | PCNT_Enable (PCNT_TypeDef *pcnt, PCNT_Mode_TypeDef mode) |
Set PCNT operational mode.
|
|
bool | PCNT_IsEnabled (PCNT_TypeDef *pcnt) |
Returns if the PCNT module is enabled or not.
|
|
void | PCNT_FreezeEnable (PCNT_TypeDef *pcnt, bool enable) |
PCNT register synchronization freeze control.
|
|
void | PCNT_Init (PCNT_TypeDef *pcnt, const PCNT_Init_TypeDef *init) |
Initialize the pulse counter.
|
|
void | PCNT_PRSInputEnable (PCNT_TypeDef *pcnt, PCNT_PRSInput_TypeDef prsInput, bool enable) |
Enable/disable the selected PRS input of PCNT.
|
|
void | PCNT_IntClear (PCNT_TypeDef *pcnt, uint32_t flags) |
Clear one or more pending PCNT interrupts.
|
|
void | PCNT_IntDisable (PCNT_TypeDef *pcnt, uint32_t flags) |
Disable one or more PCNT interrupts.
|
|
void | PCNT_IntEnable (PCNT_TypeDef *pcnt, uint32_t flags) |
Enable one or more PCNT interrupts.
|
|
uint32_t | PCNT_IntGet (PCNT_TypeDef *pcnt) |
Get pending PCNT interrupt flags.
|
|
uint32_t | PCNT_IntGetEnabled (PCNT_TypeDef *pcnt) |
Get enabled and pending PCNT interrupt flags.
|
|
void | PCNT_IntSet (PCNT_TypeDef *pcnt, uint32_t flags) |
Set one or more pending PCNT interrupts from SW.
|
|
void | PCNT_Reset (PCNT_TypeDef *pcnt) |
Reset PCNT to the same state that it was in after a hardware reset.
|
|
uint32_t | PCNT_TopBufferGet (PCNT_TypeDef *pcnt) |
Get pulse counter top buffer value.
|
|
void | PCNT_TopBufferSet (PCNT_TypeDef *pcnt, uint32_t val) |
Set top buffer value.
|
|
uint32_t | PCNT_TopGet (PCNT_TypeDef *pcnt) |
Get pulse counter top value.
|
|
void | PCNT_TopSet (PCNT_TypeDef *pcnt, uint32_t val) |
Set the top value.
|
|
void | PCNT_Sync (PCNT_TypeDef *pcnt, uint32_t mask) |
Wait for an ongoing sync of register(s) to low-frequency domain to complete.
|
|
Macros |
|
#define | PCNT0_CNT_SIZE (16) /* PCNT0 counter is 16 bits. */ |
PCNT0 Counter register size.
|
|
#define | PCNT1_CNT_SIZE (8) /* PCNT1 counter is 8 bits. */ |
PCNT1 Counter register size.
|
|
#define | PCNT2_CNT_SIZE (8) /* PCNT2 counter is 8 bits. */ |
PCNT2 Counter register size.
|
|
#define | PCNT_MODE_DISABLE 0xFF |
#define | PCNT_CNT_EVEN_NONE 0xFF |
#define | DEFAULT_DEBUG_HALT |
Default configuration for PCNT initialization structure.
|
|
#define | DEFAULT_MODE pcntModeDisable , /* Disabled by default. */ |
#define | DEFAULT_HYST false, /* Hysteresis disabled. */ |
#define | DEFAULT_CDIR true, /* Counter direction is given by CNTDIR. */ |
#define | DEFAULT_CNTEV pcntCntEventUp , /* Regular counter counts up on upcount events. */ |
#define | DEFAULT_AUXCNTEV pcntCntEventNone , /* Auxiliary counter doesn't respond to events. */ |
#define | DEFAULT_PRS_CH pcntPRSCh0 , /* PRS channel 0 selected as S0IN and as S1IN. */ |
#define | PCNT_INIT_DEFAULT |
Enumerations |
|
enum |
PCNT_Mode_TypeDef
{
pcntModeDisable = _PCNT_CTRL_MODE_DISABLE, pcntModeOvsSingle = _PCNT_CTRL_MODE_OVSSINGLE, pcntModeExtSingle = _PCNT_CTRL_MODE_EXTCLKSINGLE, pcntModeExtQuad = _PCNT_CTRL_MODE_EXTCLKQUAD } |
Mode selection.
|
|
enum |
PCNT_CntEvent_TypeDef
{
pcntCntEventBoth = _PCNT_CTRL_CNTEV_BOTH, pcntCntEventUp = _PCNT_CTRL_CNTEV_UP, pcntCntEventDown = _PCNT_CTRL_CNTEV_DOWN, pcntCntEventNone = _PCNT_CTRL_CNTEV_NONE } |
Counter event selection.
|
|
enum |
PCNT_PRSSel_TypeDef
{
pcntPRSCh0 = 0, pcntPRSCh1 = 1, pcntPRSCh2 = 2, pcntPRSCh3 = 3, pcntPRSCh4 = 4, pcntPRSCh5 = 5, pcntPRSCh6 = 6, pcntPRSCh7 = 7, pcntPRSCh8 = 8, pcntPRSCh9 = 9, pcntPRSCh10 = 10, pcntPRSCh11 = 11 } |
PRS sources for
s0PRS
and
s1PRS
.
|
|
enum |
PCNT_PRSInput_TypeDef
{
pcntPRSInputS0 = 0, pcntPRSInputS1 = 1 } |
PRS inputs of PCNT.
|
|
Function Documentation
◆ PCNT_CounterGet()
|
inline |
Default configuration for PCNT initialization structure.
Get pulse counter value.
- Parameters
-
[in] pcnt
Pointer to PCNT peripheral register block.
- Returns
- Current pulse counter value.
◆ PCNT_AuxCounterGet()
|
inline |
Get auxiliary counter value.
- Parameters
-
[in] pcnt
Pointer to PCNT peripheral register block.
- Returns
- Current auxiliary counter value.
◆ PCNT_CounterReset()
void PCNT_CounterReset | ( | PCNT_TypeDef * |
pcnt
|
) |
Reset PCNT counters and TOP register.
- Note
- Notice that special SYNCBUSY handling is not applicable for the RSTEN bit of the control register, so we don't need to wait for it when only modifying RSTEN. (It would mean undefined wait time if clocked by an external clock.) The SYNCBUSY bit will however be set, leading to a synchronization in the LF domain, with, in reality, no changes.
- Parameters
-
[in] pcnt
A pointer to the PCNT peripheral register block.
◆ PCNT_CounterTopSet()
void PCNT_CounterTopSet | ( | PCNT_TypeDef * |
pcnt,
|
uint32_t |
count,
|
||
uint32_t |
top
|
||
) |
Set the counter and top values.
The pulse counter is disabled while changing these values and reenabled (if originally enabled) when values have been set.
- Note
- This function will stall until synchronization to low-frequency domain is completed. For that reason, it should normally not be used when an external clock is used for the PCNT module, since stall time may be undefined. The counter should normally only be set when operating in (or about to enable) pcntModeOvsSingle mode.
- Parameters
-
[in] pcnt
A pointer to the PCNT peripheral register block. [in] count
A value to set in the counter register. [in] top
A value to set in the top register.
◆ PCNT_CounterSet()
|
inline |
Set counter value.
Pulse counter is disabled while changing counter value, and re-enabled (if originally enabled) when counter value has been set.
- Note
- This function will stall until synchronization to low-frequency domain is completed. For that reason, it should normally not be used when using an external clock to clock the PCNT module since stall time may be undefined in that case. The counter should normally only be set when operating in (or about to enable) pcntModeOvsSingle mode.
- Parameters
-
[in] pcnt
Pointer to PCNT peripheral register block. [in] count
Value to set in counter register.
◆ PCNT_Enable()
void PCNT_Enable | ( | PCNT_TypeDef * |
pcnt,
|
PCNT_Mode_TypeDef |
mode
|
||
) |
Set PCNT operational mode.
Notice that this function does not do any configuration. Setting operational mode is normally only required after initialization is done, and if not done as part of initialization or if requiring to disable/reenable pulse counter.
- Note
- This function may stall until synchronization to low-frequency domain is completed. For that reason, it should normally not be used when an external clock is used for the PCNT module, since stall time may be undefined.
- Parameters
-
[in] pcnt
A pointer to the PCNT peripheral register block. [in] mode
An operational mode to use for PCNT.
◆ PCNT_IsEnabled()
bool PCNT_IsEnabled | ( | PCNT_TypeDef * |
pcnt
|
) |
Returns if the PCNT module is enabled or not.
Notice that this function does not do any configuration.
- Parameters
-
[in] pcnt
A pointer to the PCNT peripheral register block. [out] isEnabled
Returns TRUE if the module is enabled.
◆ PCNT_FreezeEnable()
void PCNT_FreezeEnable | ( | PCNT_TypeDef * |
pcnt,
|
bool |
enable
|
||
) |
PCNT register synchronization freeze control.
Some PCNT registers require synchronization into the low-frequency (LF) domain. The freeze feature allows for several registers to be modified before passing them to the LF domain simultaneously, which takes place when the freeze mode is disabled.
- Note
- When enabling freeze mode, this function will wait for all current ongoing PCNT synchronization to the LF domain to complete (normally synchronization will not be in progress). However, for this reason, when using freeze mode, modifications of registers requiring the LF synchronization should be done within one freeze enable/disable block to avoid unnecessary stalling.
- Parameters
-
[in] pcnt
A pointer to the PCNT peripheral register block. [in] enable
- True - enable freeze, modified registers are not propagated to the LF domain.
- False - disables freeze, modified registers are propagated to LF domain.
◆ PCNT_Init()
void PCNT_Init | ( | PCNT_TypeDef * |
pcnt,
|
const PCNT_Init_TypeDef * |
init
|
||
) |
Initialize the pulse counter.
This function will configure the pulse counter. The clock selection is configured as follows, depending on operational mode:
- pcntModeOvsSingle - Use LFACLK.
- pcntModeExtSingle - Use external PCNTn_S0 pin.
- pcntModeExtQuad - Use external PCNTn_S0 pin.
Notice that the LFACLK must be enabled in all modes, since some basic setup is done with this clock even if the external pin clock usage mode is chosen. The pulse counter clock for the selected instance must also be enabled prior to initialization.
Notice that pins used by the PCNT module must be properly configured by the user explicitly through setting the ROUTE register for the PCNT to work as intended.
Writing to CNT will not occur in external clock modes (EXTCLKQUAD and EXTCLKSINGLE) because the external clock rate is unknown. The user should handle it manually depending on the application.
TOPB is written for all modes but in external clock mode it will take 3 external clock cycles to sync to TOP.
- Note
- Initializing requires synchronization into the low-frequency domain. This may cause a delay.
- Parameters
-
[in] pcnt
A pointer to the PCNT peripheral register block. [in] init
A pointer to the initializatio