CMU - Clock Management Unit

Description

Clock management unit (CMU) Peripheral API.

This module contains functions for the CMU peripheral of Silicon Labs 32-bit MCUs and SoCs. The CMU module controls oscillators, clocks gates, clock multiplexers, pre-scalers, calibration modules and wait-states.

Data Structures

struct  CMU_LFXOInit_TypeDef
 LFXO initialization structure.
 
struct  CMU_HFXOInit_TypeDef
 HFXO initialization structure.
 
struct  CMU_BUFOUTLeaderInit_TypeDef
 Crystal sharing leader initialization structure.
 
struct  CMU_CrystalSharingFollowerInit_TypeDef
 Crystal sharing follower initialization structure.
 
struct  CMU_DPLLInit_TypeDef
 DPLL initialization structure.
 

Functions

uint32_t CMU_Calibrate (uint32_t cycles, CMU_Select_TypeDef ref)
 Calibrate an oscillator.
 
void CMU_CalibrateConfig (uint32_t downCycles, CMU_Select_TypeDef downSel, CMU_Select_TypeDef upSel)
 Configure clock calibration.
 
uint32_t CMU_CalibrateCountGet (void)
 Get calibration count value.
 
void CMU_ClkOutPinConfig (uint32_t clkNo, CMU_Select_TypeDef sel, CMU_ClkDiv_TypeDef clkDiv, GPIO_Port_TypeDef port, unsigned int pin)
 Direct a clock to a GPIO pin.
 
CMU_ClkDiv_TypeDef CMU_ClockDivGet (CMU_Clock_TypeDef clock)
 Get clock divisor.
 
void CMU_ClockDivSet (CMU_Clock_TypeDef clock, CMU_ClkDiv_TypeDef div)
 Set clock divisor.
 
void CMU_ClockEnable (CMU_Clock_TypeDef clock, bool enable)
 Enable/disable a clock.
 
uint32_t CMU_ClockFreqGet (CMU_Clock_TypeDef clock)
 Get clock frequency for a clock point.
 
CMU_Select_TypeDef CMU_ClockSelectGet (CMU_Clock_TypeDef clock)
 Get currently selected reference clock used for a clock branch.
 
void CMU_ClockSelectSet (CMU_Clock_TypeDef clock, CMU_Select_TypeDef ref)
 Select reference clock/oscillator used for a clock branch.
 
uint16_t CMU_LF_ClockPrecisionGet (CMU_Clock_TypeDef clock)
 Gets the precision (in PPM) of the specified low frequency clock branch.
 
CMU_HFRCODPLLFreq_TypeDef CMU_HFRCODPLLBandGet (void)
 Get HFRCODPLL band in use.
 
void CMU_HFRCODPLLBandSet (CMU_HFRCODPLLFreq_TypeDef freq)
 Set HFRCODPLL band and the tuning value based on the value in the calibration table made during production.
 
bool CMU_DPLLLock (const CMU_DPLLInit_TypeDef *init)
 Lock the DPLL to a given frequency.
 
void CMU_HFXOInit (const CMU_HFXOInit_TypeDef *hfxoInit)
 Initialize all HFXO control registers.
 
void CMU_HFXOStartCrystalSharingLeader (const CMU_BUFOUTLeaderInit_TypeDef *bufoutInit, GPIO_Port_TypeDef port, unsigned int pin)
 Initialize HFXO Bufout (Crystal sharing) leader control registers.
 
void CMU_HFXOCrystalSharingFollowerInit (CMU_PRS_Status_Output_Select_TypeDef prsStatusSelectOutput, unsigned int prsAsyncCh, GPIO_Port_TypeDef port, unsigned int pin)
 Initialize HFXO Bufout (Crystal sharing) follower control registers.
 
void CMU_HFXOCTuneDeltaSet (int32_t delta)
 Set the HFXO crystal tuning delta.
 
int32_t CMU_HFXOCTuneDeltaGet (void)
 Get the HFXO crystal tuning delta.
 
void CMU_LFXOInit (const CMU_LFXOInit_TypeDef *lfxoInit)
 Initialize LFXO control registers.
 
void CMU_LFXOPrecisionSet (uint16_t precision)
 Sets LFXO's crystal precision, in PPM.
 
uint32_t CMU_OscillatorTuningGet (CMU_Osc_TypeDef osc)
 Get oscillator frequency tuning setting.
 
void CMU_OscillatorTuningSet (CMU_Osc_TypeDef osc, uint32_t val)
 Set the oscillator frequency tuning control.
 
void CMU_UpdateWaitStates (uint32_t freq, int vscale)
 Configure wait state settings necessary to switch to a given core clock frequency at a certain voltage scale level.
 
void CMU_PCNTClockExternalSet (unsigned int instance, bool external)
 Select the PCNTn clock.
 
CMU_HFRCOEM23Freq_TypeDef CMU_HFRCOEM23BandGet (void)
 Get HFRCOEM23 band in use.
 
void CMU_HFRCOEM23BandSet (CMU_HFRCOEM23Freq_TypeDef freq)
 Set HFRCOEM23 band and the tuning value based on the value in the calibration table made during production.
 
void CMU_CalibrateCont (bool enable)
 Configure continuous calibration mode.
 
void CMU_CalibrateStart (void)
 Start calibration.
 
void CMU_CalibrateStop (void)
 Stop calibration counters.
 
void CMU_DPLLUnlock (void)
 Unlock the DPLL.
 
void CMU_IntClear (uint32_t flags)
 Clear one or more pending CMU interrupt flags.
 
void CMU_IntDisable (uint32_t flags)
 Disable one or more CMU interrupt sources.
 
void CMU_IntEnable (uint32_t flags)
 Enable one or more CMU interrupt sources.
 
uint32_t CMU_IntGet (void)
 Get pending CMU interrupt sources.
 
uint32_t CMU_IntGetEnabled (void)
 Get enabled and pending CMU interrupt flags.
 
void CMU_IntSet (uint32_t flags)
 Set one or more pending CMU interrupt sources.
 
void CMU_Lock (void)
 Lock CMU register access in order to protect registers contents against unintended modification.
 
void CMU_OscillatorEnable (CMU_Osc_TypeDef osc, bool enable, bool wait)
 Enable/disable oscillator.
 
void CMU_Unlock (void)
 Unlock CMU register access so that writing to registers is possible.
 
void CMU_WdogLock (void)
 Lock WDOG register access in order to protect registers contents against unintended modification.
 
void CMU_WdogUnlock (void)
 Unlock WDOG register access so that writing to registers is possible.
 
uint32_t CMU_PrescToLog2 (uint32_t presc)
 Convert prescaler dividend to a logarithmic value.
 

Macros

#define CMU_HFRCODPLL_MIN   cmuHFRCODPLLFreq_1M0Hz
 HFRCODPLL maximum frequency.
 
#define CMU_HFRCODPLL_MAX   cmuHFRCODPLLFreq_80M0Hz
 HFRCODPLL minimum frequency.
 
#define CMU_HFRCOEM23_MIN   cmuHFRCOEM23Freq_1M0Hz
 HFRCOEM23 maximum frequency.
 
#define CMU_HFRCOEM23_MAX   cmuHFRCOEM23Freq_40M0Hz
 HFRCOEM23 minimum frequency.
 
#define CMU_LFXOINIT_DEFAULT
 Default LFXO initialization values for XTAL mode.
 
#define CMU_LFXOINIT_EXTERNAL_CLOCK
 Default LFXO initialization values for external clock mode.
 
#define CMU_LFXOINIT_EXTERNAL_SINE
 Default LFXO initialization values for external sine mode.
 
#define CMU_HFXOINIT_CTUNEFIXANA_DEFAULT   cmuHfxoCtuneFixCap_Xo
 Default configuration of fixed tuning capacitance on XI or XO for EFR32XG23.
 
#define CMU_HFXOINIT_DEFAULT
 Default HFXO initialization values for XTAL mode.
 
#define CMU_HFXOINIT_EXTERNAL_SINE
 Default HFXO initialization values for external sine mode.
 
#define CMU_HFXOINIT_EXTERNAL_SINEPKDET
 Default HFXO initialization values for external sine mode with peak detector.
 
#define CMU_HFXO_CRYSTAL_INIT_LEADER_DEFAULT
 Default crystal sharing master initialization values.
 
#define CMU_HFXO_CRYSTAL_INIT_Follower_DEFAULT
 Default crystal sharing follower initialization values.
 
#define CMU_DPLL_LFXO_TO_40MHZ
 DPLL initialization values for 39,998,805 Hz using LFXO as reference clock, M=2 and N=3661.
 
#define CMU_DPLL_HFXO_TO_76_8MHZ
 DPLL initialization values for 76,800,000 Hz using HFXO as reference clock, M = 1919, N = 3839.
 
#define CMU_DPLL_HFXO_TO_80MHZ
 DPLL initialization values for 80,000,000 Hz using HFXO as reference clock, M = 1919, N = 3999.
 
#define CMU_DPLLINIT_DEFAULT
 Default configurations for DPLL initialization.
 

Typedefs

typedef uint32_t CMU_ClkDiv_TypeDef
 Clock divider configuration.
 

Enumerations

enum  CMU_HFRCODPLLFreq_TypeDef {
  cmuHFRCODPLLFreq_1M0Hz = 1000000U,
  cmuHFRCODPLLFreq_2M0Hz = 2000000U,
  cmuHFRCODPLLFreq_4M0Hz = 4000000U,
  cmuHFRCODPLLFreq_7M0Hz = 7000000U,
  cmuHFRCODPLLFreq_13M0Hz = 13000000U,
  cmuHFRCODPLLFreq_16M0Hz = 16000000U,
  cmuHFRCODPLLFreq_19M0Hz = 19000000U,
  cmuHFRCODPLLFreq_26M0Hz = 26000000U,
  cmuHFRCODPLLFreq_32M0Hz = 32000000U,
  cmuHFRCODPLLFreq_38M0Hz = 38000000U,
  cmuHFRCODPLLFreq_48M0Hz = 48000000U,
  cmuHFRCODPLLFreq_56M0Hz = 56000000U,
  cmuHFRCODPLLFreq_64M0Hz = 64000000U,
  cmuHFRCODPLLFreq_80M0Hz = 80000000U,
  cmuHFRCODPLLFreq_UserDefined = 0
}
 HFRCODPLL frequency bands.
 
enum  CMU_HFRCOEM23Freq_TypeDef {
  cmuHFRCOEM23Freq_1M0Hz = 1000000U,
  cmuHFRCOEM23Freq_2M0Hz = 2000000U,
  cmuHFRCOEM23Freq_4M0Hz = 4000000U,
  cmuHFRCOEM23Freq_13M0Hz = 13000000U,
  cmuHFRCOEM23Freq_16M0Hz = 16000000U,
  cmuHFRCOEM23Freq_19M0Hz = 19000000U,
  cmuHFRCOEM23Freq_26M0Hz = 26000000U,
  cmuHFRCOEM23Freq_32M0Hz = 32000000U,
  cmuHFRCOEM23Freq_40M0Hz = 40000000U,
  cmuHFRCOEM23Freq_UserDefined = 0
}
 HFRCOEM23 frequency bands.
 
enum  CMU_Clock_TypeDef {
  cmuClock_SYSCLK = (CMU_SYSCLK_BRANCH << CMU_CLK_BRANCH_POS),
  cmuClock_SYSTICK = (CMU_SYSTICK_BRANCH << CMU_CLK_BRANCH_POS),
  cmuClock_HCLK = (CMU_HCLK_BRANCH << CMU_CLK_BRANCH_POS),
  cmuClock_EXPCLK = (CMU_EXPCLK_BRANCH << CMU_CLK_BRANCH_POS),
  cmuClock_PCLK = (CMU_PCLK_BRANCH << CMU_CLK_BRANCH_POS),
  cmuClock_LSPCLK = (CMU_LSPCLK_BRANCH << CMU_CLK_BRANCH_POS),
  cmuClock_TRACECLK = (CMU_TRACECLK_BRANCH << CMU_CLK_BRANCH_POS),
  cmuClock_EM01GRPACLK = (CMU_EM01GRPACLK_BRANCH << CMU_CLK_BRANCH_POS),
  cmuClock_EM01GRPCCLK = (CMU_EM01GRPCCLK_BRANCH << CMU_CLK_BRANCH_POS),
  cmuClock_EUSART0CLK = (CMU_EUART0CLK_BRANCH << CMU_CLK_BRANCH_POS),
  cmuClock_IADCCLK = (CMU_IADCCLK_BRANCH << CMU_CLK_BRANCH_POS),
  cmuClock_EM23GRPACLK = (CMU_EM23GRPACLK_BRANCH << CMU_CLK_BRANCH_POS),
  cmuClock_WDOG0CLK = (CMU_WDOG0CLK_BRANCH << CMU_CLK_BRANCH_POS),
  cmuClock_WDOG1CLK = (CMU_WDOG1CLK_BRANCH << CMU_CLK_BRANCH_POS),
  cmuClock_SYSRTCCLK = (CMU_SYSRTCCLK_BRANCH << CMU_CLK_BRANCH_POS),
  cmuClock_EM4GRPACLK = (CMU_EM4GRPACLK_BRANCH << CMU_CLK_BRANCH_POS),
  cmuClock_DPLLREFCLK = (CMU_DPLLREFCLK_BRANCH << CMU_CLK_BRANCH_POS),
  cmuClock_LCDCLK = (CMU_LCD_BRANCH << CMU_CLK_BRANCH_POS),
  cmuClock_VDAC0CLK = (CMU_VDAC0_BRANCH << CMU_CLK_BRANCH_POS),
  cmuClock_PCNT0CLK = (CMU_PCNT_BRANCH << CMU_CLK_BRANCH_POS),
  cmuClock_LESENSEHFCLK = (CMU_LESENSEHF_BRANCH << CMU_CLK_BRANCH_POS),
  cmuClock_LESENSECLK = (CMU_LESENSE_BRANCH << CMU_CLK_BRANCH_POS),
  cmuClock_CORE = (CMU_CORE_BRANCH << CMU_CLK_BRANCH_POS),
  cmuClock_LDMA,
  cmuClock_LDMAXBAR,
  cmuClock_RADIOAES,
  cmuClock_GPCRC,
  cmuClock_TIMER0,
  cmuClock_TIMER1,
  cmuClock_TIMER2,
  cmuClock_TIMER3,
  cmuClock_TIMER4,
  cmuClock_USART0,
  cmuClock_IADC0,
  cmuClock_AMUXCP0,
  cmuClock_LETIMER0,
  cmuClock_WDOG0,
  cmuClock_WDOG1,
  cmuClock_I2C0,
  cmuClock_I2C1,
  cmuClock_SYSCFG,
  cmuClock_DPLL0,
  cmuClock_HFRCO0,
  cmuClock_HFRCOEM23,
  cmuClock_HFXO,
  cmuClock_FSRCO,
  cmuClock_LFRCO,
  cmuClock_LFXO,
  cmuClock_ULFRCO,
  cmuClock_GPIO,
  cmuClock_PRS,
  cmuClock_BURAM,
  cmuClock_BURTC,
  cmuClock_DCDC,
  cmuClock_SYSRTC,
  cmuClock_EUSART0,
  cmuClock_EUSART1,
  cmuClock_EUSART2,
  cmuClock_SEMAILBOX,
  cmuClock_SMU,
  cmuClock_ICACHE,
  cmuClock_LESENSE,
  cmuClock_ACMP0,
  cmuClock_ACMP1,
  cmuClock_VDAC0,
  cmuClock_PCNT0,
  cmuClock_DMEM,
  cmuClock_KEYSCAN,
  cmuClock_LCD,
  cmuClock_MSC
}
 Clock points in CMU clock-tree.
 
enum  CMU_Osc_TypeDef {
  cmuOsc_LFXO,
  cmuOsc_LFRCO,
  cmuOsc_FSRCO,
  cmuOsc_HFXO,
  cmuOsc_HFRCODPLL,
  cmuOsc_HFRCOEM23,
  cmuOsc_ULFRCO
}
 Oscillator types.
 
enum  CMU_Select_TypeDef {
  cmuSelect_Error,
  cmuSelect_Disabled,
  cmuSelect_FSRCO,
  cmuSelect_HFXO,
  cmuSelect_HFXORT,
  cmuSelect_HFRCODPLL,
  cmuSelect_HFRCODPLLRT,
  cmuSelect_HFRCOEM23,
  cmuSelect_CLKIN0,
  cmuSelect_LFXO,
  cmuSelect_LFRCO,
  cmuSelect_ULFRCO,
  cmuSelect_HCLK,
  cmuSelect_SYSCLK,
  cmuSelect_HCLKDIV1024,
  cmuSelect_EM01GRPACLK,
  cmuSelect_EM23GRPACLK,
  cmuSelect_EM01GRPCCLK,
  cmuSelect_EXPCLK,
  cmuSelect_PRS,
  cmuSelect_PCNTEXTCLK,
  cmuSelect_TEMPOSC,
  cmuSelect_PFMOSC,
  cmuSelect_BIASOSC
}
 Selectable clock sources.
 
enum  CMU_DPLLEdgeSel_TypeDef {
  cmuDPLLEdgeSel_Fall = 0,
  cmuDPLLEdgeSel_Rise = 1
}
 DPLL reference clock edge detect selector.
 
enum  CMU_DPLLLockMode_TypeDef {
  cmuDPLLLockMode_Freq = _DPLL_CFG_MODE_FLL,
  cmuDPLLLockMode_Phase = _DPLL_CFG_MODE_PLL
}
 DPLL lock mode selector.
 
enum  CMU_LfxoOscMode_TypeDef {
  cmuLfxoOscMode_Crystal = _LFXO_CFG_MODE_XTAL,
  cmuLfxoOscMode_AcCoupledSine = _LFXO_CFG_MODE_BUFEXTCLK,
  cmuLfxoOscMode_External = _LFXO_CFG_MODE_DIGEXTCLK
}
 LFXO oscillator modes.
 
enum  CMU_LfxoStartupDelay_TypeDef {
  cmuLfxoStartupDelay_2Cycles = _LFXO_CFG_TIMEOUT_CYCLES2,
  cmuLfxoStartupDelay_256Cycles = _LFXO_CFG_TIMEOUT_CYCLES256,
  cmuLfxoStartupDelay_1KCycles = _LFXO_CFG_TIMEOUT_CYCLES1K,
  cmuLfxoStartupDelay_2KCycles = _LFXO_CFG_TIMEOUT_CYCLES2K,
  cmuLfxoStartupDelay_4KCycles = _LFXO_CFG_TIMEOUT_CYCLES4K,
  cmuLfxoStartupDelay_8KCycles = _LFXO_CFG_TIMEOUT_CYCLES8K,
  cmuLfxoStartupDelay_16KCycles = _LFXO_CFG_TIMEOUT_CYCLES16K,
  cmuLfxoStartupDelay_32KCycles = _LFXO_CFG_TIMEOUT_CYCLES32K
}
 LFXO start-up timeout delay.
 
enum  CMU_HfxoOscMode_TypeDef {
  cmuHfxoOscMode_Crystal = _HFXO_CFG_MODE_XTAL,
  cmuHfxoOscMode_ExternalSine = _HFXO_CFG_MODE_EXTCLK,
  cmuHfxoOscMode_ExternalSinePkDet = _HFXO_CFG_MODE_EXTCLKPKDET
}
 HFXO oscillator modes.
 
enum  CMU_HfxoCbLsbTimeout_TypeDef {
  cmuHfxoCbLsbTimeout_8us = _HFXO_XTALCFG_TIMEOUTCBLSB_T8US,
  cmuHfxoCbLsbTimeout_20us = _HFXO_XTALCFG_TIMEOUTCBLSB_T20US,
  cmuHfxoCbLsbTimeout_41us = _HFXO_XTALCFG_TIMEOUTCBLSB_T41US,
  cmuHfxoCbLsbTimeout_62us = _HFXO_XTALCFG_TIMEOUTCBLSB_T62US,
  cmuHfxoCbLsbTimeout_83us = _HFXO_XTALCFG_TIMEOUTCBLSB_T83US,
  cmuHfxoCbLsbTimeout_104us = _HFXO_XTALCFG_TIMEOUTCBLSB_T104US,
  cmuHfxoCbLsbTimeout_125us = _HFXO_XTALCFG_TIMEOUTCBLSB_T125US,
  cmuHfxoCbLsbTimeout_166us = _HFXO_XTALCFG_TIMEOUTCBLSB_T166US,
  cmuHfxoCbLsbTimeout_208us = _HFXO_XTALCFG_TIMEOUTCBLSB_T208US,
  cmuHfxoCbLsbTimeout_250us = _HFXO_XTALCFG_TIMEOUTCBLSB_T250US,
  cmuHfxoCbLsbTimeout_333us = _HFXO_XTALCFG_TIMEOUTCBLSB_T333US,
  cmuHfxoCbLsbTimeout_416us = _HFXO_XTALCFG_TIMEOUTCBLSB_T416US,
  cmuHfxoCbLsbTimeout_833us = _HFXO_XTALCFG_TIMEOUTCBLSB_T833US,
  cmuHfxoCbLsbTimeout_1250us = _HFXO_XTALCFG_TIMEOUTCBLSB_T1250US,
  cmuHfxoCbLsbTimeout_2083us = _HFXO_XTALCFG_TIMEOUTCBLSB_T2083US,
  cmuHfxoCbLsbTimeout_3750us = _HFXO_XTALCFG_TIMEOUTCBLSB_T3750US
}
 HFXO core bias LSB change timeout.
 
enum  CMU_HfxoSteadyStateTimeout_TypeDef {
  cmuHfxoSteadyStateTimeout_16us = _HFXO_XTALCFG_TIMEOUTSTEADY_T16US,
  cmuHfxoSteadyStateTimeout_41us = _HFXO_XTALCFG_TIMEOUTSTEADY_T41US,
  cmuHfxoSteadyStateTimeout_83us = _HFXO_XTALCFG_TIMEOUTSTEADY_T83US,
  cmuHfxoSteadyStateTimeout_125us = _HFXO_XTALCFG_TIMEOUTSTEADY_T125US,
  cmuHfxoSteadyStateTimeout_166us = _HFXO_XTALCFG_TIMEOUTSTEADY_T166US,
  cmuHfxoSteadyStateTimeout_208us = _HFXO_XTALCFG_TIMEOUTSTEADY_T208US,
  cmuHfxoSteadyStateTimeout_250us = _HFXO_XTALCFG_TIMEOUTSTEADY_T250US,
  cmuHfxoSteadyStateTimeout_333us = _HFXO_XTALCFG_TIMEOUTSTEADY_T333US,
  cmuHfxoSteadyStateTimeout_416us = _HFXO_XTALCFG_TIMEOUTSTEADY_T416US,
  cmuHfxoSteadyStateTimeout_500us = _HFXO_XTALCFG_TIMEOUTSTEADY_T500US,
  cmuHfxoSteadyStateTimeout_666us = _HFXO_XTALCFG_TIMEOUTSTEADY_T666US,
  cmuHfxoSteadyStateTimeout_833us = _HFXO_XTALCFG_TIMEOUTSTEADY_T833US,
  cmuHfxoSteadyStateTimeout_1666us = _HFXO_XTALCFG_TIMEOUTSTEADY_T1666US,
  cmuHfxoSteadyStateTimeout_2500us = _HFXO_XTALCFG_TIMEOUTSTEADY_T2500US,
  cmuHfxoSteadyStateTimeout_4166us = _HFXO_XTALCFG_TIMEOUTSTEADY_T4166US
}
 HFXO steady state timeout.
 
enum  CMU_HfxoCoreDegen_TypeDef {
  cmuHfxoCoreDegen_None = _HFXO_XTALCTRL_COREDGENANA_NONE,
  cmuHfxoCoreDegen_33 = _HFXO_XTALCTRL_COREDGENANA_DGEN33,
  cmuHfxoCoreDegen_50 = _HFXO_XTALCTRL_COREDGENANA_DGEN50,
  cmuHfxoCoreDegen_100 = _HFXO_XTALCTRL_COREDGENANA_DGEN100
}
 HFXO core degeneration control.
 
enum  CMU_HfxoCtuneFixCap_TypeDef {
  cmuHfxoCtuneFixCap_None = _HFXO_XTALCTRL_CTUNEFIXANA_NONE,
  cmuHfxoCtuneFixCap_Xi = _HFXO_XTALCTRL_CTUNEFIXANA_XI,
  cmuHfxoCtuneFixCap_Xo = _HFXO_XTALCTRL_CTUNEFIXANA_XO,
  cmuHfxoCtuneFixCap_Both = _HFXO_XTALCTRL_CTUNEFIXANA_BOTH
}
 HFXO XI and XO pin fixed capacitor control.
 
enum  CMU_Precision_TypeDef {
  cmuPrecisionDefault,
  cmuPrecisionHigh
}
 Oscillator precision modes.
 
enum  CMU_BufoutTimeoutStartup_TypeDef {
  startupTimeout42Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T42US,
  startupTimeout83Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T83US,
  startupTimeout108Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T108US,
  startupTimeout133Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T133US,
  startupTimeout158Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T158US,
  startupTimeout183Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T183US,
  startupTimeout208Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T208US,
  startupTimeout233Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T233US,
  startupTimeout258Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T258US,
  startupTimeout283Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T283US,
  startupTimeout333Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T333US,
  startupTimeout375Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T375US,
  startupTimeout417Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T417US,
  startupTimeout458Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T458US,
  startupTimeout500Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T500US,
  startupTimeout667Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T667US
}
 Crystal sharing timeout start up timeout.
 
enum  CMU_PRS_Status_Output_Select_TypeDef {
  PRS_Status_select_0,
  PRS_Status_select_1
}
 PRS status select output signal.
 

Function Documentation

◆ CMU_Calibrate()

uint32_t CMU_Calibrate ( uint32_t  cycles,
CMU_Select_TypeDef  ref 
)

Calibrate an oscillator.

Run a calibration of a selectable reference clock againt HCLK. Please refer to the reference manual, CMU chapter, for further details.

Note
This function will not return until calibration measurement is completed.
Parameters
[in]cyclesThe number of HCLK cycles to run calibration. Increasing this number increases precision, but the calibration will take more time.
[in]refThe reference clock used to compare against HCLK.
Returns
The number of ticks the selected reference clock ticked while running cycles ticks of the HCLK clock.

◆ CMU_CalibrateConfig()

void CMU_CalibrateConfig ( uint32_t  downCycles,
CMU_Select_TypeDef  downSel,
CMU_Select_TypeDef  upSel 
)

Configure clock calibration.

Configure a calibration for a selectable clock source against another selectable reference clock. Refer to the reference manual, CMU chapter, for further details.

Note
After configuration, a call to CMU_CalibrateStart() is required, and the resulting calibration value can be read with the CMU_CalibrateCountGet() function call.
Parameters
[in]downCyclesThe number of downSel clock cycles to run calibration. Increasing this number increases precision, but the calibration will take more time.
[in]downSelThe clock which will be counted down downCycles cycles.
[in]upSelThe reference clock, the number of cycles generated by this clock will be counted and added up, the result can be given with the CMU_CalibrateCountGet() function call.

◆ CMU_CalibrateCountGet()

uint32_t CMU_CalibrateCountGet ( void  )

Get calibration count value.

Note
If continuous calibration mode is active, calibration busy will almost always be off, and reading the value will be just needed, where the normal case would be that this function call has been triggered by the CALRDY interrupt flag.
Returns
Calibration count, the number of UPSEL clocks (see CMU_CalibrateConfig()) in the period of DOWNSEL oscillator clock cycles configured by a previous write operation to CMU->CALCNT.

◆ CMU_ClkOutPinConfig()

void CMU_ClkOutPinConfig ( uint32_t  clkNo,
CMU_Select_TypeDef  sel,
CMU_ClkDiv_TypeDef  clkDiv,
GPIO_Port_TypeDef  port,
unsigned int  pin 
)

Direct a clock to a GPIO pin.

Parameters
[in]clkNoSelects between CLKOUT0, CLKOUT1 or CLKOUT2 outputs. Use values 0,1or 2.
[in]selSelect clock source.
[in]clkDivSelect a clock divisor (1..32). Only applicable when cmuSelect_EXPCLK is slexted as clock source.
[in]portGPIO port.
[in]pinGPIO pin.
Note
Refer to the reference manual and the datasheet for details on which GPIO port/pins that are available.

◆ CMU_ClockDivGet()

CMU_ClkDiv_TypeDef CMU_ClockDivGet ( CMU_Clock_TypeDef  clock)

Get clock divisor.

Parameters
[in]clockClock point to get divisor for. Notice that not all clock points have a divisors. Please refer to CMU overview in reference manual.
Returns
The current clock point divisor. 1 is returned if clock specifies a clock point without divisor.

◆ CMU_ClockDivSet()

void CMU_ClockDivSet ( CMU_Clock_TypeDef  clock,
CMU_ClkDiv_TypeDef  div 
)

Set clock divisor.

Parameters
[in]clockClock point to set divisor for. Notice that not all clock points have a divisor, please refer to CMU overview in the reference manual.
[in]divThe clock divisor to use.

◆ CMU_ClockEnable()

void CMU_ClockEnable ( CMU_Clock_TypeDef  clock,
bool  enable 
)

Enable/disable a clock.

Module clocks sre disabled after reset. If a module clock is disabled, the registers of that module are not accessible and accessing such registers will hardfault the Cortex core.

Parameters
[in]clockThe clock to enable/disable.
[in]enable
  • true - enable specified clock.
  • false - disable specified clock.

◆ CMU_ClockFreqGet()

uint32_t CMU_ClockFreqGet ( CMU_Clock_TypeDef  clock)

Get clock frequency for a clock point.

Parameters
[in]clockClock point to fetch frequency for.
Returns
The current frequency in Hz.

◆ CMU_ClockSelectGet()

CMU_Select_TypeDef CMU_ClockSelectGet ( CMU_Clock_TypeDef  clock)

Get currently selected reference clock used for a clock branch.

Parameters
[in]clockClock branch to fetch selected ref. clock for.
Returns
Reference clock used for clocking selected branch, cmuSelect_Error if invalid clock provided.

◆ CMU_ClockSelectSet()

void CMU_ClockSelectSet ( CMU_Clock_TypeDef  clock,
CMU_Select_TypeDef  ref 
)

Select reference clock/oscillator used for a clock branch.

Parameters
[in]clockClock branch to select reference clock for.
[in]refReference selected for clocking, please refer to reference manual for for details on which reference is available for a specific clock branch.

◆ CMU_LF_ClockPrecisionGet()

uint16_t CMU_LF_ClockPrecisionGet ( CMU_Clock_TypeDef  clock)

Gets the precision (in PPM) of the specified low frequency clock branch.

Parameters
[in]clockClock branch.
Returns
Precision, in PPM, of the specified clock branch.
Note
This function is only for internal usage.
The current implementation of this function is used to determine if the clock has a precision <= 500 ppm or not (which is the minimum required for BLE). Future version of this function should provide more accurate precision numbers to allow for further optimizations from the stacks.

◆ CMU_HFRCODPLLBandGet()

CMU_HFRCODPLLFreq_TypeDef CMU_HFRCODPLLBandGet ( void  )

Get HFRCODPLL band in use.

Returns
HFRCODPLL band in use.

◆ CMU_HFRCODPLLBandSet()

void CMU_HFRCODPLLBandSet ( CMU_HFRCODPLLFreq_TypeDef  freq)

Set HFRCODPLL band and the tuning value based on the value in the calibration table made during production.

Parameters
[in]freqHFRCODPLL frequency band to activate.

◆ CMU_DPLLLock()

bool CMU_DPLLLock ( const CMU_DPLLInit_TypeDef init)

Lock the DPLL to a given frequency.

The frequency is given by: Fout = Fref * (N+1) / (M+1).

Note
This function does not check if the given N & M values will actually produce the desired target frequency.
N & M limitations:
300 < N <= 4095
0 <= M <= 4095
Any peripheral running off HFRCODPLL should be switched to a lower frequency clock (if possible) prior to calling this function to avoid over-clocking.
Parameters
[in]initDPLL setup parameter struct.
Returns
Returns false on invalid target frequency or DPLL locking error.

◆ CMU_HFXOInit()

void CMU_HFXOInit ( const CMU_HFXOInit_TypeDef hfxoInit)

Initialize all HFXO control registers.

Note
HFXO configuration should be obtained from a configuration tool, app note or crystal datasheet. This function returns early if HFXO is already selected as SYSCLK.
Parameters
[in]hfxoInitHFXO setup parameters.

◆ CMU_HFXOStartCrystalSharingLeader()

void CMU_HFXOStartCrystalSharingLeader ( const CMU_BUFOUTLeaderInit_TypeDef bufoutInit,
GPIO_Port_TypeDef  port,
unsigned int  pin 
)

Initialize HFXO Bufout (Crystal sharing) leader control registers.

Configure the bufout request input GPIO as a clock request signal to add the crystal sharing follower chip as a source of clock request.

Warning
If EM2 capabilities are needed, a GPIO that fully retains its capabilities while in EM2 must be selected.
Parameters
[in]bufoutInitBufout setup parameters.
[in]portBufout request GPIO port.
[in]pinBufout request GPIO pin.

◆ CMU_HFXOCrystalSharingFollowerInit()

void CMU_HFXOCrystalSharingFollowerInit ( CMU_PRS_Status_Output_Select_TypeDef  prsStatusSelectOutput,
unsigned int  prsAsyncCh,
GPIO_Port_TypeDef  port,
unsigned int  pin 
)

Initialize HFXO Bufout (Crystal sharing) follower control registers.

Configure the clock request signal to a specified GPIO to automatically request the high frequency crystal oscillator sine wave clock. This function must be used in conjunction with CMU_HFXOInit() configured with EXTERNAL_SINE or EXTERNAL_SINEPKDET mode.

Warning
If EM2 capabilities are needed, a GPIO that fully retains its capabilities while in EM2 must be selected.
Note
This function can be emulated on XG21/XG22 chips by controlling the clock request GPIO to ask the crystal sharing leader clock when needed.
Parameters
[in]prsStatusSelectOutputSelected HFXO PRS signal output.
[in]prsAsyncChPRS producer asynchronous signal channel.
[in]portBufout request GPIO port.
[in]pinBufout request GPIO pin.

◆ CMU_HFXOCTuneDeltaSet()

void CMU_HFXOCTuneDeltaSet ( int32_t  delta)

Set the HFXO crystal tuning delta.

Parameters
[in]deltaChip dependent crystal capacitor bank delta between HFXO XI and XO.
Note
The delta between XI and XO is applicable for the series 2 EFR32xG2x devices only.

◆ CMU_HFXOCTuneDeltaGet()

int32_t CMU_HFXOCTuneDeltaGet ( void  )

Get the HFXO crystal tuning delta.

Returns
Chip dependent crystal capacitor bank tuning delta.

◆ CMU_LFXOInit()

void CMU_LFXOInit ( const CMU_LFXOInit_TypeDef lfxoInit)

Initialize LFXO control registers.

Note
LFXO configuration should be obtained from a configuration tool, app note or crystal datasheet. This function disables the LFXO to ensure a valid state before update.
Parameters
[in]lfxoInitLFXO setup parameters

◆ CMU_LFXOPrecisionSet()

void CMU_LFXOPrecisionSet ( uint16_t  precision)

Sets LFXO's crystal precision, in PPM.

Note
LFXO precision should be obtained from a crystal datasheet.
Parameters
[in]precisionLFXO's crystal precision, in PPM.

◆ CMU_OscillatorTuningGet()

uint32_t CMU_OscillatorTuningGet ( CMU_Osc_TypeDef  osc)

Get oscillator frequency tuning setting.

Parameters
[in]oscOscillator to get tuning value for.
Returns
The oscillator frequency tuning setting in use.

◆ CMU_OscillatorTuningSet()

void CMU_OscillatorTuningSet ( CMU_Osc_TypeDef  osc,
uint32_t  val 
)

Set the oscillator frequency tuning control.

Note
Oscillator tuning is done during production, and the tuning value is automatically loaded after a reset. Changing the tuning value from the calibrated value is for more advanced use. Certain oscillators also have build-in tuning optimization.
Parameters
[in]oscOscillator to set tuning value for.
[in]valThe oscillator frequency tuning setting to use.

◆ CMU_UpdateWaitStates()

void CMU_UpdateWaitStates ( uint32_t  freq,
int  vscale 
)

Configure wait state settings necessary to switch to a given core clock frequency at a certain voltage scale level.

This function will set up the necessary flash wait states. Updating the wait state configuration must be done before increasing the clock frequency and it must be done after decreasing the clock frequency. Updating the wait state configuration must be done before core voltage is decreased and it must be done after a core voltage is increased.

Parameters
[in]freqThe core clock frequency to configure wait-states.
[in]vscaleThe voltage scale to configure wait-states. Expected values are 0 or 1, higher number is lower voltage.
  • 0 = 1.1 V (VSCALE2)
  • 1 = 1.0 V (VSCALE1)

◆ CMU_PCNTClockExternalSet()

void CMU_PCNTClockExternalSet ( unsigned int  instance,
bool  external 
)

Select the PCNTn clock.

Parameters
[in]instancePCNT instance number to set selected clock source for.
[in]externalSet to true to select the external clock, false to select EM23GRPACLK.

◆ CMU_HFRCOEM23BandGet()

CMU_HFRCOEM23Freq_TypeDef CMU_HFRCOEM23BandGet ( void  )

Get HFRCOEM23 band in use.

Returns
HFRCOEM23 band in use.

◆ CMU_HFRCOEM23BandSet()

void CMU_HFRCOEM23BandSet ( CMU_HFRCOEM23Freq_TypeDef  freq)

Set HFRCOEM23 band and the tuning value based on the value in the calibration table made during production.

Parameters
[in]freqHFRCOEM23 frequency band to activate.

◆ CMU_CalibrateCont()

void CMU_CalibrateCont ( bool  enable)
inline

Configure continuous calibration mode.

Parameters
[in]enableIf true, enables continuous calibration, if false disables continuous calibration.

◆ CMU_CalibrateStart()

void CMU_CalibrateStart ( void  )
inline

Start calibration.

Note
This call is usually invoked after CMU_CalibrateConfig() and possibly CMU_CalibrateCont().

◆ CMU_CalibrateStop()

void CMU_CalibrateStop ( void  )
inline

Stop calibration counters.

◆ CMU_DPLLUnlock()

void CMU_DPLLUnlock ( void  )
inline

Unlock the DPLL.

Note
The HFRCODPLL oscillator is not turned off.

◆ CMU_IntClear()

void CMU_IntClear ( uint32_t  flags)
inline

Clear one or more pending CMU interrupt flags.

Parameters
[in]flagsCMU interrupt sources to clear.

◆ CMU_IntDisable()

void CMU_IntDisable ( uint32_t  flags)
inline

Disable one or more CMU interrupt sources.

Parameters
[in]flagsCMU interrupt sources to disable.

◆ CMU_IntEnable()

void CMU_IntEnable ( uint32_t  flags)
inline

Enable one or more CMU interrupt sources.

Note
Depending on the use, a pending interrupt may already be set prior to enabling the interrupt. Consider using CMU_IntClear() prior to enabling if such a pending interrupt should be ignored.
Parameters
[in]flagsCMU interrupt sources to enable.

◆ CMU_IntGet()

uint32_t CMU_IntGet ( void  )
inline

Get pending CMU interrupt sources.

Returns
CMU interrupt sources pending.

◆ CMU_IntGetEnabled()

uint32_t CMU_IntGetEnabled ( void  )
inline

Get enabled and pending CMU interrupt flags.

Useful for handling more interrupt sources in the same interrupt handler.

Note
The event bits are not cleared by the use of this function.
Returns
Pending and enabled CMU interrupt sources. The return value is the bitwise AND of
  • the enabled interrupt sources in CMU_IEN and
  • the pending interrupt flags CMU_IF

◆ CMU_IntSet()

void CMU_IntSet ( uint32_t  flags)
inline

Set one or more pending CMU interrupt sources.

Parameters
[in]flagsCMU interrupt sources to set to pending.

◆ CMU_Lock()

void CMU_Lock ( void  )
inline

Lock CMU register access in order to protect registers contents against unintended modification.

See the reference manual for CMU registers that will be locked.

Note
If locking the CMU registers, they must be unlocked prior to using any CMU API functions modifying CMU registers protected by the lock.

◆ CMU_OscillatorEnable()

void CMU_OscillatorEnable ( CMU_Osc_TypeDef  osc,
bool  enable,
bool  wait 
)
inline

Enable/disable oscillator.

Note
This is a dummy function to solve backward compatibility issues.
Parameters
[in]oscThe oscillator to enable/disable.
[in]enable
  • true - enable specified oscillator.
  • false - disable specified oscillator.
[in]waitOnly used if enable is true.
  • true - wait for oscillator start-up time to timeout before returning.
  • false - do not wait for oscillator start-up time to timeout before returning.

◆ CMU_Unlock()

void CMU_Unlock ( void  )
inline

Unlock CMU register access so that writing to registers is possible.

◆ CMU_WdogLock()

void CMU_WdogLock ( void  )
inline

Lock WDOG register access in order to protect registers contents against unintended modification.

Note
If locking the WDOG registers, they must be unlocked prior to using any emlib API functions modifying registers protected by the lock.

◆ CMU_WdogUnlock()

void CMU_WdogUnlock ( void  )
inline

Unlock WDOG register access so that writing to registers is possible.

◆ CMU_PrescToLog2()

uint32_t CMU_PrescToLog2 ( uint32_t  presc)
inline

Convert prescaler dividend to a logarithmic value.

It only works for even numbers equal to 2^n.

Parameters
[in]prescAn unscaled dividend (dividend = presc + 1).
Returns
Logarithm of 2, as used by fixed 2^n prescalers.

Macro Definition Documentation

◆ CMU_HFRCODPLL_MIN

#define CMU_HFRCODPLL_MIN   cmuHFRCODPLLFreq_1M0Hz

HFRCODPLL maximum frequency.

◆ CMU_HFRCODPLL_MAX

#define CMU_HFRCODPLL_MAX   cmuHFRCODPLLFreq_80M0Hz

HFRCODPLL minimum frequency.

◆ CMU_HFRCOEM23_MIN

#define CMU_HFRCOEM23_MIN   cmuHFRCOEM23Freq_1M0Hz

HFRCOEM23 maximum frequency.

◆ CMU_HFRCOEM23_MAX

#define CMU_HFRCOEM23_MAX   cmuHFRCOEM23Freq_40M0Hz

HFRCOEM23 minimum frequency.

◆ CMU_LFXOINIT_DEFAULT

#define CMU_LFXOINIT_DEFAULT
Value:
{ \
1, \
38, \
cmuLfxoStartupDelay_4KCycles, \
cmuLfxoOscMode_Crystal, \
false, /* highAmplitudeEn */ \
true, /* agcEn */ \
false, /* failDetEM4WUEn */ \
false, /* failDetEn */ \
false, /* DisOndemand */ \
false, /* ForceEn */ \
false /* Lock registers */ \
}

Default LFXO initialization values for XTAL mode.

◆ CMU_LFXOINIT_EXTERNAL_CLOCK

#define CMU_LFXOINIT_EXTERNAL_CLOCK
Value:
{ \
0U, \
0U, \
cmuLfxoStartupDelay_2Cycles, \
cmuLfxoOscMode_External, \
false, /* highAmplitudeEn */ \
false, /* agcEn */ \
false, /* failDetEM4WUEn */ \
false, /* failDetEn */ \
false, /* DisOndemand */ \
false, /* ForceEn */ \
false /* Lock registers */ \
}

Default LFXO initialization values for external clock mode.

◆ CMU_LFXOINIT_EXTERNAL_SINE

#define CMU_LFXOINIT_EXTERNAL_SINE
Value:
{ \
0U, \
0U, \
cmuLfxoStartupDelay_2Cycles, \
cmuLfxoOscMode_AcCoupledSine, \
false, /* highAmplitudeEn */ \
false, /* agcEn */ \
false, /* failDetEM4WUEn */ \
false, /* failDetEn */ \
false, /* DisOndemand */ \
false, /* ForceEn */ \
false /* Lock registers */ \
}

Default LFXO initialization values for external sine mode.

◆ CMU_HFXOINIT_CTUNEFIXANA_DEFAULT

#define CMU_HFXOINIT_CTUNEFIXANA_DEFAULT   cmuHfxoCtuneFixCap_Xo

Default configuration of fixed tuning capacitance on XI or XO for EFR32XG23.

◆ CMU_HFXOINIT_DEFAULT

#define CMU_HFXOINIT_DEFAULT
Value:
{ \
cmuHfxoCbLsbTimeout_416us, \
cmuHfxoSteadyStateTimeout_833us, /* First lock */ \
cmuHfxoSteadyStateTimeout_83us, /* Subsequent locks */ \
0U, /* ctuneXoStartup */ \
0U, /* ctuneXiStartup */ \
32U, /* coreBiasStartup */ \
32U, /* imCoreBiasStartup */ \
cmuHfxoCoreDegen_None, \
CMU_HFXOINIT_CTUNEFIXANA_DEFAULT, \
_HFXO_XTALCTRL_CTUNEXOANA_DEFAULT, /* ctuneXoAna */ \
_HFXO_XTALCTRL_CTUNEXIANA_DEFAULT, /* ctuneXiAna */ \
60U, /* coreBiasAna */ \
false, /* enXiDcBiasAna */ \
cmuHfxoOscMode_Crystal, \
false, /* forceXo2GndAna */ \
false, /* forceXi2GndAna */ \
false, /* DisOndemand */ \
false, /* ForceEn */ \
false, /* em23OnDemand */ \
false /* Lock registers */ \
}

Default HFXO initialization values for XTAL mode.

◆ CMU_HFXOINIT_EXTERNAL_SINE

#define CMU_HFXOINIT_EXTERNAL_SINE
Value:
{ \
(CMU_HfxoCbLsbTimeout_TypeDef)0, /* timeoutCbLsb */ \
(CMU_HfxoSteadyStateTimeout_TypeDef)0, /* timeoutSteady, first lock */ \
(CMU_HfxoSteadyStateTimeout_TypeDef)0, /* timeoutSteady, subseq. locks */ \
0U, /* ctuneXoStartup */ \
0U, /* ctuneXiStartup */ \
0U, /* coreBiasStartup */ \
0U, /* imCoreBiasStartup */ \
0U, /* ctuneXoAna */ \
0U, /* ctuneXiAna */ \
0U, /* coreBiasAna */ \
false, /* enXiDcBiasAna, false=DC true=AC coupling of signal */ \
false, /* forceXo2GndAna */ \
false, /* forceXi2GndAna (Never enable in sine mode) */ \
false, /* DisOndemand */ \
false, /* ForceEn */ \
false, /* em23OnDemand */ \
false /* Lock registers */ \
}

Default HFXO initialization values for external sine mode.

◆ CMU_HFXOINIT_EXTERNAL_SINEPKDET

#define CMU_HFXOINIT_EXTERNAL_SINEPKDET
Value:
{ \
(CMU_HfxoCbLsbTimeout_TypeDef)0, /* timeoutCbLsb */ \
(CMU_HfxoSteadyStateTimeout_TypeDef)0, /* timeoutSteady, first lock */ \
(CMU_HfxoSteadyStateTimeout_TypeDef)0, /* timeoutSteady, subseq. locks */ \
0U, /* ctuneXoStartup */ \
0U, /* ctuneXiStartup */ \
0U, /* coreBiasStartup */ \
0U, /* imCoreBiasStartup */ \
0U, /* ctuneXoAna */ \
0U, /* ctuneXiAna */ \
0U, /* coreBiasAna */ \
false, /* enXiDcBiasAna, false=DC true=AC coupling of signal */ \
false, /* forceXo2GndAna */ \
false, /* forceXi2GndAna (Never enable in sine mode) */ \
false, /* DisOndemand */ \
false, /* ForceEn */ \
false, /* em23OnDemand */ \
false /* Lock registers */ \
}

Default HFXO initialization values for external sine mode with peak detector.

◆ CMU_HFXO_CRYSTAL_INIT_LEADER_DEFAULT

#define CMU_HFXO_CRYSTAL_INIT_LEADER_DEFAULT
Value:
{ \
true, /* minimalStartupDelay */ \
startupTimeout208Us, /* timeoutStartup */ \
}

Default crystal sharing master initialization values.

◆ CMU_HFXO_CRYSTAL_INIT_Follower_DEFAULT

#define CMU_HFXO_CRYSTAL_INIT_Follower_DEFAULT
Value:
{ \
PRS_Status_select_0, /* prsStatusSelectOutput */ \
true, /* em23OnDemand */ \
false /* regLock */ \
}

Default crystal sharing follower initialization values.

◆ CMU_DPLL_LFXO_TO_40MHZ

#define CMU_DPLL_LFXO_TO_40MHZ
Value:
{ \
39998805, /* Target frequency. */ \
3661, /* Factor N. */ \
2, /* Factor M. */ \
cmuSelect_LFXO, /* Select LFXO as reference clock. */ \
cmuDPLLEdgeSel_Fall, /* Select falling edge of ref clock. */ \
cmuDPLLLockMode_Freq, /* Use frequency lock mode. */ \
true, /* Enable automatic lock recovery. */ \
false /* Don't enable dither function. */ \
}

DPLL initialization values for 39,998,805 Hz using LFXO as reference clock, M=2 and N=3661.

◆ CMU_DPLL_HFXO_TO_76_8MHZ

#define CMU_DPLL_HFXO_TO_76_8MHZ
Value:
{ \
76800000, /* Target frequency. */ \
3839, /* Factor N. */ \
1919, /* Factor M. */ \
cmuSelect_HFXO, /* Select HFXO as reference clock. */ \
cmuDPLLEdgeSel_Fall, /* Select falling edge of ref clock. */ \
cmuDPLLLockMode_Freq, /* Use frequency lock mode. */ \
true, /* Enable automatic lock recovery. */ \
false /* Don't enable dither function. */ \
}

DPLL initialization values for 76,800,000 Hz using HFXO as reference clock, M = 1919, N = 3839.

◆ CMU_DPLL_HFXO_TO_80MHZ

#define CMU_DPLL_HFXO_TO_80MHZ
Value:
{ \
80000000, /* Target frequency. */ \
(4000 - 1), /* Factor N. */ \
(1920 - 1), /* Factor M. */ \
cmuSelect_HFXO, /* Select HFXO as reference clock. */ \
cmuDPLLEdgeSel_Fall, /* Select falling edge of ref clock. */ \
cmuDPLLLockMode_Freq, /* Use frequency lock mode. */ \
true, /* Enable automatic lock recovery. */ \
false /* Don't enable dither function. */ \
}

DPLL initialization values for 80,000,000 Hz using HFXO as reference clock, M = 1919, N = 3999.

◆ CMU_DPLLINIT_DEFAULT

#define CMU_DPLLINIT_DEFAULT
Value:
{ \
80000000, /* Target frequency. */ \
(4000 - 1), /* Factor N. */ \
(1920 - 1), /* Factor M. */ \
cmuSelect_HFXO, /* Select HFXO as reference clock. */ \
cmuDPLLEdgeSel_Fall, /* Select falling edge of ref clock. */ \
cmuDPLLLockMode_Freq, /* Use frequency lock mode. */ \
true, /* Enable automatic lock recovery. */ \
false /* Don't enable dither function. */ \
}

Default configurations for DPLL initialization.

When using this macro you need to modify the N and M factor and the desired frequency to match the components placed on the board.

Typedef Documentation

◆ CMU_ClkDiv_TypeDef

typedef uint32_t CMU_ClkDiv_TypeDef

Clock divider configuration.

Enumeration Type Documentation

◆ CMU_HFRCODPLLFreq_TypeDef

HFRCODPLL frequency bands.

Enumerator
cmuHFRCODPLLFreq_1M0Hz 

1MHz RC band.


cmuHFRCODPLLFreq_2M0Hz 

2MHz RC band.


cmuHFRCODPLLFreq_4M0Hz 

4MHz RC band.


cmuHFRCODPLLFreq_7M0Hz 

7MHz RC band.


cmuHFRCODPLLFreq_13M0Hz 

13MHz RC band.

cmuHFRCODPLLFreq_16M0Hz 

16MHz RC band.

cmuHFRCODPLLFreq_19M0Hz 

19MHz RC band.

cmuHFRCODPLLFreq_26M0Hz 

26MHz RC band.

cmuHFRCODPLLFreq_32M0Hz 

32MHz RC band.

cmuHFRCODPLLFreq_38M0Hz 

38MHz RC band.

cmuHFRCODPLLFreq_48M0Hz 

48MHz RC band.

cmuHFRCODPLLFreq_56M0Hz 

56MHz RC band.

cmuHFRCODPLLFreq_64M0Hz 

64MHz RC band.

cmuHFRCODPLLFreq_80M0Hz 

80MHz RC band.

◆ CMU_HFRCOEM23Freq_TypeDef

HFRCOEM23 frequency bands.

Enumerator
cmuHFRCOEM23Freq_1M0Hz 

1MHz RC band.


cmuHFRCOEM23Freq_2M0Hz 

2MHz RC band.


cmuHFRCOEM23Freq_4M0Hz 

4MHz RC band.


cmuHFRCOEM23Freq_13M0Hz 

13MHz RC band.

cmuHFRCOEM23Freq_16M0Hz 

16MHz RC band.

cmuHFRCOEM23Freq_19M0Hz 

19MHz RC band.

cmuHFRCOEM23Freq_26M0Hz 

26MHz RC band.

cmuHFRCOEM23Freq_32M0Hz 

32MHz RC band.

cmuHFRCOEM23Freq_40M0Hz 

40MHz RC band.

◆ CMU_Clock_TypeDef

Clock points in CMU clock-tree.

Enumerator
cmuClock_SYSCLK 

SYSTEM clock.

cmuClock_SYSTICK 

SYSTICK clock.

cmuClock_HCLK 

Core and AHB bus interface clock.

cmuClock_EXPCLK 

Export clock.

cmuClock_PCLK 

Peripheral APB bus interface clock.

cmuClock_LSPCLK 

Low speed peripheral APB bus interface clock.

cmuClock_TRACECLK 

Debug trace.

cmuClock_EM01GRPACLK 

EM01GRPA clock.

cmuClock_EM01GRPCCLK 

EM01GRPC clock.

cmuClock_EUSART0CLK 

EUSART0 clock.

cmuClock_IADCCLK 

IADC clock.

cmuClock_EM23GRPACLK 

EM23GRPA clock.

cmuClock_WDOG0CLK 

WDOG0 clock.

cmuClock_WDOG1CLK 

WDOG1 clock.

cmuClock_SYSRTCCLK 

SYSRTC clock.

cmuClock_EM4GRPACLK 

EM4GRPA clock.

cmuClock_DPLLREFCLK 

DPLLREF clock.

cmuClock_LCDCLK 

LCD clock.

cmuClock_VDAC0CLK 

VDAC0 clock.

cmuClock_PCNT0CLK 

PCNT0 clock.