SPI Advanced initialization structure.

Public Attributes#

EUSART_InvertIO_TypeDef
invertIO

Enable inversion of RX and/or TX signals.

bool
autoCsEnable

Enable automatic chip select. CS is managed by the peripheral.

bool
msbFirst

If true, data will be send with most significant bit first.

uint8_t
autoCsSetupTime

Auto CS setup time (before transmission) in baud cycles. Acceptable value ( 0 to 7 baud cycle).

uint8_t
autoCsHoldTime

Auto CS hold time (after transmission) in baud cycles. Acceptable value ( 0 to 7 baud cycle).

uint8_t
autoInterFrameTime

Inter-frame time in baud cycles. Acceptable value ( 0 to 7 baud cycle).

bool
autoTxEnable

Enable AUTOTX mode.

uint16_t
defaultTxData

Default transmitted data when the TXFIFO is empty.

bool
dmaWakeUpOnRx

Enable the automatic wake up from EM2 to EM1 for DMA RX operation.

bool
prsRxEnable

Enable EUSART capability to use a PRS channel as an input data line for the receiver.

EUSART_PrsChannel_TypeDef
prsRxChannel

PRS Channel used to transmit data from PRS to the EUSART.

bool
prsClockEnable

Enable EUSART capability to use a PRS channel as an input SPI Clock.

EUSART_PrsChannel_TypeDef
prsClockChannel

PRS Channel used to transmit SCLK from PRS to the EUSART.

EUSART_RxFifoWatermark_TypeDef
RxFifoWatermark

Interrupt and status level of the Receive FIFO.

EUSART_TxFifoWatermark_TypeDef
TxFifoWatermark

Interrupt and status level of the Receive FIFO.

bool
forceLoad

Force load the first FIFO value.

uint8_t
setupWindow

Setup window in bus clock cycles before the sampling edge of SCLK at word-boundary to avoid force load error.

Public Attribute Documentation#

csPolarity#

EUSART_CsPolarity_TypeDef EUSART_SpiAdvancedInit_TypeDef::csPolarity

Chip select polarity.


Definition at line 581 of file platform/emlib/inc/em_eusart.h

invertIO#

EUSART_InvertIO_TypeDef EUSART_SpiAdvancedInit_TypeDef::invertIO

Enable inversion of RX and/or TX signals.


Definition at line 584 of file platform/emlib/inc/em_eusart.h

autoCsEnable#

bool EUSART_SpiAdvancedInit_TypeDef::autoCsEnable

Enable automatic chip select. CS is managed by the peripheral.


Definition at line 587 of file platform/emlib/inc/em_eusart.h

msbFirst#

bool EUSART_SpiAdvancedInit_TypeDef::msbFirst

If true, data will be send with most significant bit first.


Definition at line 590 of file platform/emlib/inc/em_eusart.h

autoCsSetupTime#

uint8_t EUSART_SpiAdvancedInit_TypeDef::autoCsSetupTime

Auto CS setup time (before transmission) in baud cycles. Acceptable value ( 0 to 7 baud cycle).


Definition at line 593 of file platform/emlib/inc/em_eusart.h

autoCsHoldTime#

uint8_t EUSART_SpiAdvancedInit_TypeDef::autoCsHoldTime

Auto CS hold time (after transmission) in baud cycles. Acceptable value ( 0 to 7 baud cycle).


Definition at line 596 of file platform/emlib/inc/em_eusart.h

autoInterFrameTime#

uint8_t EUSART_SpiAdvancedInit_TypeDef::autoInterFrameTime

Inter-frame time in baud cycles. Acceptable value ( 0 to 7 baud cycle).


Definition at line 599 of file platform/emlib/inc/em_eusart.h

autoTxEnable#

bool EUSART_SpiAdvancedInit_TypeDef::autoTxEnable

Enable AUTOTX mode.

Transmits as long as the RX FIFO is not full. Generates underflow interrupt if the TX FIFO is empty.


Definition at line 603 of file platform/emlib/inc/em_eusart.h

defaultTxData#

uint16_t EUSART_SpiAdvancedInit_TypeDef::defaultTxData

Default transmitted data when the TXFIFO is empty.


Definition at line 606 of file platform/emlib/inc/em_eusart.h

dmaWakeUpOnRx#

bool EUSART_SpiAdvancedInit_TypeDef::dmaWakeUpOnRx

Enable the automatic wake up from EM2 to EM1 for DMA RX operation.

Only applicable to EM2 (low frequency) capable EUSART instances.


Definition at line 610 of file platform/emlib/inc/em_eusart.h

prsRxEnable#

bool EUSART_SpiAdvancedInit_TypeDef::prsRxEnable

Enable EUSART capability to use a PRS channel as an input data line for the receiver.

The configured RX GPIO signal won't be routed to the EUSART receiver.


Definition at line 614 of file platform/emlib/inc/em_eusart.h

prsRxChannel#

EUSART_PrsChannel_TypeDef EUSART_SpiAdvancedInit_TypeDef::prsRxChannel

PRS Channel used to transmit data from PRS to the EUSART.


Definition at line 617 of file platform/emlib/inc/em_eusart.h

prsClockEnable#

bool EUSART_SpiAdvancedInit_TypeDef::prsClockEnable

Enable EUSART capability to use a PRS channel as an input SPI Clock.

Slave mode only.


Definition at line 621 of file platform/emlib/inc/em_eusart.h

prsClockChannel#

EUSART_PrsChannel_TypeDef EUSART_SpiAdvancedInit_TypeDef::prsClockChannel

PRS Channel used to transmit SCLK from PRS to the EUSART.


Definition at line 624 of file platform/emlib/inc/em_eusart.h

RxFifoWatermark#

EUSART_RxFifoWatermark_TypeDef EUSART_SpiAdvancedInit_TypeDef::RxFifoWatermark

Interrupt and status level of the Receive FIFO.


Definition at line 627 of file platform/emlib/inc/em_eusart.h

TxFifoWatermark#

EUSART_TxFifoWatermark_TypeDef EUSART_SpiAdvancedInit_TypeDef::TxFifoWatermark

Interrupt and status level of the Receive FIFO.


Definition at line 630 of file platform/emlib/inc/em_eusart.h

forceLoad#

bool EUSART_SpiAdvancedInit_TypeDef::forceLoad

Force load the first FIFO value.


Definition at line 633 of file platform/emlib/inc/em_eusart.h

setupWindow#

uint8_t EUSART_SpiAdvancedInit_TypeDef::setupWindow

Setup window in bus clock cycles before the sampling edge of SCLK at word-boundary to avoid force load error.


Definition at line 636 of file platform/emlib/inc/em_eusart.h