|
#define
|
_CMU_ADCCTRL_ADC0CLKINV_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_ADCCTRL_ADC0CLKINV_MASK
0x100UL
|
|
#define
|
_CMU_ADCCTRL_ADC0CLKINV_SHIFT
8
|
|
#define
|
_CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO
0x00000001UL
|
|
#define
|
_CMU_ADCCTRL_ADC0CLKSEL_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_ADCCTRL_ADC0CLKSEL_DISABLED
0x00000000UL
|
|
#define
|
_CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK
0x00000003UL
|
|
#define
|
_CMU_ADCCTRL_ADC0CLKSEL_HFXO
0x00000002UL
|
|
#define
|
_CMU_ADCCTRL_ADC0CLKSEL_MASK
0x30UL
|
|
#define
|
_CMU_ADCCTRL_ADC0CLKSEL_SHIFT
4
|
|
#define
|
_CMU_ADCCTRL_MASK
0x00000130UL
|
|
#define
|
_CMU_ADCCTRL_RESETVALUE
0x00000000UL
|
|
#define
|
_CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_AUXHFRCOCTRL_CLKDIV_DIV1
0x00000000UL
|
|
#define
|
_CMU_AUXHFRCOCTRL_CLKDIV_DIV2
0x00000001UL
|
|
#define
|
_CMU_AUXHFRCOCTRL_CLKDIV_DIV4
0x00000002UL
|
|
#define
|
_CMU_AUXHFRCOCTRL_CLKDIV_MASK
0x6000000UL
|
|
#define
|
_CMU_AUXHFRCOCTRL_CLKDIV_SHIFT
25
|
|
#define
|
_CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT
0x00000002UL
|
|
#define
|
_CMU_AUXHFRCOCTRL_CMPBIAS_MASK
0xE00000UL
|
|
#define
|
_CMU_AUXHFRCOCTRL_CMPBIAS_SHIFT
21
|
|
#define
|
_CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT
0x0000001FUL
|
|
#define
|
_CMU_AUXHFRCOCTRL_FINETUNING_MASK
0x3F00UL
|
|
#define
|
_CMU_AUXHFRCOCTRL_FINETUNING_SHIFT
8
|
|
#define
|
_CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_AUXHFRCOCTRL_FINETUNINGEN_MASK
0x8000000UL
|
|
#define
|
_CMU_AUXHFRCOCTRL_FINETUNINGEN_SHIFT
27
|
|
#define
|
_CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT
0x00000008UL
|
|
#define
|
_CMU_AUXHFRCOCTRL_FREQRANGE_MASK
0x1F0000UL
|
|
#define
|
_CMU_AUXHFRCOCTRL_FREQRANGE_SHIFT
16
|
|
#define
|
_CMU_AUXHFRCOCTRL_LDOHP_DEFAULT
0x00000001UL
|
|
#define
|
_CMU_AUXHFRCOCTRL_LDOHP_MASK
0x1000000UL
|
|
#define
|
_CMU_AUXHFRCOCTRL_LDOHP_SHIFT
24
|
|
#define
|
_CMU_AUXHFRCOCTRL_MASK
0xFFFF3F7FUL
|
|
#define
|
_CMU_AUXHFRCOCTRL_RESETVALUE
0xB1481F7FUL
|
|
#define
|
_CMU_AUXHFRCOCTRL_TUNING_DEFAULT
0x0000007FUL
|
|
#define
|
_CMU_AUXHFRCOCTRL_TUNING_MASK
0x7FUL
|
|
#define
|
_CMU_AUXHFRCOCTRL_TUNING_SHIFT
0
|
|
#define
|
_CMU_AUXHFRCOCTRL_VREFTC_DEFAULT
0x0000000BUL
|
|
#define
|
_CMU_AUXHFRCOCTRL_VREFTC_MASK
0xF0000000UL
|
|
#define
|
_CMU_AUXHFRCOCTRL_VREFTC_SHIFT
28
|
|
#define
|
_CMU_CALCNT_CALCNT_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_CALCNT_CALCNT_MASK
0xFFFFFUL
|
|
#define
|
_CMU_CALCNT_CALCNT_SHIFT
0
|
|
#define
|
_CMU_CALCNT_MASK
0x000FFFFFUL
|
|
#define
|
_CMU_CALCNT_RESETVALUE
0x00000000UL
|
|
#define
|
_CMU_CALCTRL_CONT_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_CALCTRL_CONT_MASK
0x100UL
|
|
#define
|
_CMU_CALCTRL_CONT_SHIFT
8
|
|
#define
|
_CMU_CALCTRL_DOWNSEL_AUXHFRCO
0x00000005UL
|
|
#define
|
_CMU_CALCTRL_DOWNSEL_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_CALCTRL_DOWNSEL_HFCLK
0x00000000UL
|
|
#define
|
_CMU_CALCTRL_DOWNSEL_HFRCO
0x00000003UL
|
|
#define
|
_CMU_CALCTRL_DOWNSEL_HFXO
0x00000001UL
|
|
#define
|
_CMU_CALCTRL_DOWNSEL_LFRCO
0x00000004UL
|
|
#define
|
_CMU_CALCTRL_DOWNSEL_LFXO
0x00000002UL
|
|
#define
|
_CMU_CALCTRL_DOWNSEL_MASK
0xF0UL
|
|
#define
|
_CMU_CALCTRL_DOWNSEL_PRS
0x00000006UL
|
|
#define
|
_CMU_CALCTRL_DOWNSEL_SHIFT
4
|
|
#define
|
_CMU_CALCTRL_MASK
0x0F0F01FFUL
|
|
#define
|
_CMU_CALCTRL_PRSDOWNSEL_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_CALCTRL_PRSDOWNSEL_MASK
0xF000000UL
|
|
#define
|
_CMU_CALCTRL_PRSDOWNSEL_PRSCH0
0x00000000UL
|
|
#define
|
_CMU_CALCTRL_PRSDOWNSEL_PRSCH1
0x00000001UL
|
|
#define
|
_CMU_CALCTRL_PRSDOWNSEL_PRSCH10
0x0000000AUL
|
|
#define
|
_CMU_CALCTRL_PRSDOWNSEL_PRSCH11
0x0000000BUL
|
|
#define
|
_CMU_CALCTRL_PRSDOWNSEL_PRSCH2
0x00000002UL
|
|
#define
|
_CMU_CALCTRL_PRSDOWNSEL_PRSCH3
0x00000003UL
|
|
#define
|
_CMU_CALCTRL_PRSDOWNSEL_PRSCH4
0x00000004UL
|
|
#define
|
_CMU_CALCTRL_PRSDOWNSEL_PRSCH5
0x00000005UL
|
|
#define
|
_CMU_CALCTRL_PRSDOWNSEL_PRSCH6
0x00000006UL
|
|
#define
|
_CMU_CALCTRL_PRSDOWNSEL_PRSCH7
0x00000007UL
|
|
#define
|
_CMU_CALCTRL_PRSDOWNSEL_PRSCH8
0x00000008UL
|
|
#define
|
_CMU_CALCTRL_PRSDOWNSEL_PRSCH9
0x00000009UL
|
|
#define
|
_CMU_CALCTRL_PRSDOWNSEL_SHIFT
24
|
|
#define
|
_CMU_CALCTRL_PRSUPSEL_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_CALCTRL_PRSUPSEL_MASK
0xF0000UL
|
|
#define
|
_CMU_CALCTRL_PRSUPSEL_PRSCH0
0x00000000UL
|
|
#define
|
_CMU_CALCTRL_PRSUPSEL_PRSCH1
0x00000001UL
|
|
#define
|
_CMU_CALCTRL_PRSUPSEL_PRSCH10
0x0000000AUL
|
|
#define
|
_CMU_CALCTRL_PRSUPSEL_PRSCH11
0x0000000BUL
|
|
#define
|
_CMU_CALCTRL_PRSUPSEL_PRSCH2
0x00000002UL
|
|
#define
|
_CMU_CALCTRL_PRSUPSEL_PRSCH3
0x00000003UL
|
|
#define
|
_CMU_CALCTRL_PRSUPSEL_PRSCH4
0x00000004UL
|
|
#define
|
_CMU_CALCTRL_PRSUPSEL_PRSCH5
0x00000005UL
|
|
#define
|
_CMU_CALCTRL_PRSUPSEL_PRSCH6
0x00000006UL
|
|
#define
|
_CMU_CALCTRL_PRSUPSEL_PRSCH7
0x00000007UL
|
|
#define
|
_CMU_CALCTRL_PRSUPSEL_PRSCH8
0x00000008UL
|
|
#define
|
_CMU_CALCTRL_PRSUPSEL_PRSCH9
0x00000009UL
|
|
#define
|
_CMU_CALCTRL_PRSUPSEL_SHIFT
16
|
|
#define
|
_CMU_CALCTRL_RESETVALUE
0x00000000UL
|
|
#define
|
_CMU_CALCTRL_UPSEL_AUXHFRCO
0x00000004UL
|
|
#define
|
_CMU_CALCTRL_UPSEL_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_CALCTRL_UPSEL_HFRCO
0x00000002UL
|
|
#define
|
_CMU_CALCTRL_UPSEL_HFXO
0x00000000UL
|
|
#define
|
_CMU_CALCTRL_UPSEL_LFRCO
0x00000003UL
|
|
#define
|
_CMU_CALCTRL_UPSEL_LFXO
0x00000001UL
|
|
#define
|
_CMU_CALCTRL_UPSEL_MASK
0xFUL
|
|
#define
|
_CMU_CALCTRL_UPSEL_PRS
0x00000005UL
|
|
#define
|
_CMU_CALCTRL_UPSEL_SHIFT
0
|
|
#define
|
_CMU_CMD_CALSTART_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_CMD_CALSTART_MASK
0x1UL
|
|
#define
|
_CMU_CMD_CALSTART_SHIFT
0
|
|
#define
|
_CMU_CMD_CALSTOP_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_CMD_CALSTOP_MASK
0x2UL
|
|
#define
|
_CMU_CMD_CALSTOP_SHIFT
1
|
|
#define
|
_CMU_CMD_HFXOPEAKDETSTART_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_CMD_HFXOPEAKDETSTART_MASK
0x10UL
|
|
#define
|
_CMU_CMD_HFXOPEAKDETSTART_SHIFT
4
|
|
#define
|
_CMU_CMD_HFXOSHUNTOPTSTART_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_CMD_HFXOSHUNTOPTSTART_MASK
0x20UL
|
|
#define
|
_CMU_CMD_HFXOSHUNTOPTSTART_SHIFT
5
|
|
#define
|
_CMU_CMD_MASK
0x00000033UL
|
|
#define
|
_CMU_CMD_RESETVALUE
0x00000000UL
|
|
#define
|
_CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ
0x0000000DUL
|
|
#define
|
_CMU_CTRL_CLKOUTSEL0_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_CTRL_CLKOUTSEL0_DISABLED
0x00000000UL
|
|
#define
|
_CMU_CTRL_CLKOUTSEL0_HFEXPCLK
0x00000007UL
|
|
#define
|
_CMU_CTRL_CLKOUTSEL0_HFRCOQ
0x0000000CUL
|
|
#define
|
_CMU_CTRL_CLKOUTSEL0_HFSRCCLK
0x0000000FUL
|
|
#define
|
_CMU_CTRL_CLKOUTSEL0_HFXO
0x00000006UL
|
|
#define
|
_CMU_CTRL_CLKOUTSEL0_HFXOQ
0x0000000EUL
|
|
#define
|
_CMU_CTRL_CLKOUTSEL0_LFRCO
0x00000002UL
|
|
#define
|
_CMU_CTRL_CLKOUTSEL0_LFRCOQ
0x0000000AUL
|
|
#define
|
_CMU_CTRL_CLKOUTSEL0_LFXO
0x00000003UL
|
|
#define
|
_CMU_CTRL_CLKOUTSEL0_LFXOQ
0x0000000BUL
|
|
#define
|
_CMU_CTRL_CLKOUTSEL0_MASK
0x1FUL
|
|
#define
|
_CMU_CTRL_CLKOUTSEL0_SHIFT
0
|
|
#define
|
_CMU_CTRL_CLKOUTSEL0_ULFRCO
0x00000001UL
|
|
#define
|
_CMU_CTRL_CLKOUTSEL0_ULFRCOQ
0x00000009UL
|
|
#define
|
_CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ
0x0000000DUL
|
|
#define
|
_CMU_CTRL_CLKOUTSEL1_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_CTRL_CLKOUTSEL1_DISABLED
0x00000000UL
|
|
#define
|
_CMU_CTRL_CLKOUTSEL1_HFEXPCLK
0x00000007UL
|
|
#define
|
_CMU_CTRL_CLKOUTSEL1_HFRCOQ
0x0000000CUL
|
|
#define
|
_CMU_CTRL_CLKOUTSEL1_HFSRCCLK
0x0000000FUL
|
|
#define
|
_CMU_CTRL_CLKOUTSEL1_HFXO
0x00000006UL
|
|
#define
|
_CMU_CTRL_CLKOUTSEL1_HFXOQ
0x0000000EUL
|
|
#define
|
_CMU_CTRL_CLKOUTSEL1_LFRCO
0x00000002UL
|
|
#define
|
_CMU_CTRL_CLKOUTSEL1_LFRCOQ
0x0000000AUL
|
|
#define
|
_CMU_CTRL_CLKOUTSEL1_LFXO
0x00000003UL
|
|
#define
|
_CMU_CTRL_CLKOUTSEL1_LFXOQ
0x0000000BUL
|
|
#define
|
_CMU_CTRL_CLKOUTSEL1_MASK
0x3E0UL
|
|
#define
|
_CMU_CTRL_CLKOUTSEL1_SHIFT
5
|
|
#define
|
_CMU_CTRL_CLKOUTSEL1_ULFRCO
0x00000001UL
|
|
#define
|
_CMU_CTRL_CLKOUTSEL1_ULFRCOQ
0x00000009UL
|
|
#define
|
_CMU_CTRL_HFPERCLKEN_DEFAULT
0x00000001UL
|
|
#define
|
_CMU_CTRL_HFPERCLKEN_MASK
0x100000UL
|
|
#define
|
_CMU_CTRL_HFPERCLKEN_SHIFT
20
|
|
#define
|
_CMU_CTRL_MASK
0x001103FFUL
|
|
#define
|
_CMU_CTRL_RESETVALUE
0x00300000UL
|
|
#define
|
_CMU_CTRL_WSHFLE_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_CTRL_WSHFLE_MASK
0x10000UL
|
|
#define
|
_CMU_CTRL_WSHFLE_SHIFT
16
|
|
#define
|
_CMU_DBGCLKSEL_DBG_AUXHFRCO
0x00000000UL
|
|
#define
|
_CMU_DBGCLKSEL_DBG_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_DBGCLKSEL_DBG_HFCLK
0x00000001UL
|
|
#define
|
_CMU_DBGCLKSEL_DBG_MASK
0x1UL
|
|
#define
|
_CMU_DBGCLKSEL_DBG_SHIFT
0
|
|
#define
|
_CMU_DBGCLKSEL_MASK
0x00000001UL
|
|
#define
|
_CMU_DBGCLKSEL_RESETVALUE
0x00000000UL
|
|
#define
|
_CMU_DPLLCTRL1_M_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_DPLLCTRL1_M_MASK
0xFFFUL
|
|
#define
|
_CMU_DPLLCTRL1_M_SHIFT
0
|
|
#define
|
_CMU_DPLLCTRL1_MASK
0x0FFF0FFFUL
|
|
#define
|
_CMU_DPLLCTRL1_N_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_DPLLCTRL1_N_MASK
0xFFF0000UL
|
|
#define
|
_CMU_DPLLCTRL1_N_SHIFT
16
|
|
#define
|
_CMU_DPLLCTRL1_RESETVALUE
0x00000000UL
|
|
#define
|
_CMU_DPLLCTRL_AUTORECOVER_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_DPLLCTRL_AUTORECOVER_MASK
0x4UL
|
|
#define
|
_CMU_DPLLCTRL_AUTORECOVER_SHIFT
2
|
|
#define
|
_CMU_DPLLCTRL_DITHEN_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_DPLLCTRL_DITHEN_MASK
0x40UL
|
|
#define
|
_CMU_DPLLCTRL_DITHEN_SHIFT
6
|
|
#define
|
_CMU_DPLLCTRL_EDGESEL_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_DPLLCTRL_EDGESEL_FALL
0x00000000UL
|
|
#define
|
_CMU_DPLLCTRL_EDGESEL_MASK
0x2UL
|
|
#define
|
_CMU_DPLLCTRL_EDGESEL_RISE
0x00000001UL
|
|
#define
|
_CMU_DPLLCTRL_EDGESEL_SHIFT
1
|
|
#define
|
_CMU_DPLLCTRL_MASK
0x0000005FUL
|
|
#define
|
_CMU_DPLLCTRL_MODE_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_DPLLCTRL_MODE_FREQLL
0x00000000UL
|
|
#define
|
_CMU_DPLLCTRL_MODE_MASK
0x1UL
|
|
#define
|
_CMU_DPLLCTRL_MODE_PHASELL
0x00000001UL
|
|
#define
|
_CMU_DPLLCTRL_MODE_SHIFT
0
|
|
#define
|
_CMU_DPLLCTRL_REFSEL_CLKIN0
0x00000003UL
|
|
#define
|
_CMU_DPLLCTRL_REFSEL_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_DPLLCTRL_REFSEL_HFXO
0x00000000UL
|
|
#define
|
_CMU_DPLLCTRL_REFSEL_LFXO
0x00000001UL
|
|
#define
|
_CMU_DPLLCTRL_REFSEL_MASK
0x18UL
|
|
#define
|
_CMU_DPLLCTRL_REFSEL_SHIFT
3
|
|
#define
|
_CMU_DPLLCTRL_RESETVALUE
0x00000000UL
|
|
#define
|
_CMU_FREEZE_MASK
0x00000001UL
|
|
#define
|
_CMU_FREEZE_REGFREEZE_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_FREEZE_REGFREEZE_FREEZE
0x00000001UL
|
|
#define
|
_CMU_FREEZE_REGFREEZE_MASK
0x1UL
|
|
#define
|
_CMU_FREEZE_REGFREEZE_SHIFT
0
|
|
#define
|
_CMU_FREEZE_REGFREEZE_UPDATE
0x00000000UL
|
|
#define
|
_CMU_FREEZE_RESETVALUE
0x00000000UL
|
|
#define
|
_CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_HFBUSCLKEN0_CRYPTO0_MASK
0x2UL
|
|
#define
|
_CMU_HFBUSCLKEN0_CRYPTO0_SHIFT
1
|
|
#define
|
_CMU_HFBUSCLKEN0_CRYPTO_DEFAULT
_CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT
|
|
#define
|
_CMU_HFBUSCLKEN0_CRYPTO_MASK
_CMU_HFBUSCLKEN0_CRYPTO0_MASK
|
|
#define
|
_CMU_HFBUSCLKEN0_CRYPTO_SHIFT
_CMU_HFBUSCLKEN0_CRYPTO0_SHIFT
|
|
#define
|
_CMU_HFBUSCLKEN0_GPCRC_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_HFBUSCLKEN0_GPCRC_MASK
0x20UL
|
|
#define
|
_CMU_HFBUSCLKEN0_GPCRC_SHIFT
5
|
|
#define
|
_CMU_HFBUSCLKEN0_GPIO_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_HFBUSCLKEN0_GPIO_MASK
0x4UL
|
|
#define
|
_CMU_HFBUSCLKEN0_GPIO_SHIFT
2
|
|
#define
|
_CMU_HFBUSCLKEN0_LDMA_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_HFBUSCLKEN0_LDMA_MASK
0x10UL
|
|
#define
|
_CMU_HFBUSCLKEN0_LDMA_SHIFT
4
|
|
#define
|
_CMU_HFBUSCLKEN0_LE_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_HFBUSCLKEN0_LE_MASK
0x1UL
|
|
#define
|
_CMU_HFBUSCLKEN0_LE_SHIFT
0
|
|
#define
|
_CMU_HFBUSCLKEN0_MASK
0x0000003FUL
|
|
#define
|
_CMU_HFBUSCLKEN0_PRS_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_HFBUSCLKEN0_PRS_MASK
0x8UL
|
|
#define
|
_CMU_HFBUSCLKEN0_PRS_SHIFT
3
|
|
#define
|
_CMU_HFBUSCLKEN0_RESETVALUE
0x00000000UL
|
|
#define
|
_CMU_HFCLKSEL_HF_CLKIN0
0x00000007UL
|
|
#define
|
_CMU_HFCLKSEL_HF_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_HFCLKSEL_HF_HFRCO
0x00000001UL
|
|
#define
|
_CMU_HFCLKSEL_HF_HFRCODIV2
0x00000005UL
|
|
#define
|
_CMU_HFCLKSEL_HF_HFXO
0x00000002UL
|
|
#define
|
_CMU_HFCLKSEL_HF_LFRCO
0x00000003UL
|
|
#define
|
_CMU_HFCLKSEL_HF_LFXO
0x00000004UL
|
|
#define
|
_CMU_HFCLKSEL_HF_MASK
0x7UL
|
|
#define
|
_CMU_HFCLKSEL_HF_SHIFT
0
|
|
#define
|
_CMU_HFCLKSEL_MASK
0x00000007UL
|
|
#define
|
_CMU_HFCLKSEL_RESETVALUE
0x00000000UL
|
|
#define
|
_CMU_HFCLKSTATUS_MASK
0x00000007UL
|
|
#define
|
_CMU_HFCLKSTATUS_RESETVALUE
0x00000001UL
|
|
#define
|
_CMU_HFCLKSTATUS_SELECTED_CLKIN0
0x00000007UL
|
|
#define
|
_CMU_HFCLKSTATUS_SELECTED_DEFAULT
0x00000001UL
|
|
#define
|
_CMU_HFCLKSTATUS_SELECTED_HFRCO
0x00000001UL
|
|
#define
|
_CMU_HFCLKSTATUS_SELECTED_HFRCODIV2
0x00000005UL
|
|
#define
|
_CMU_HFCLKSTATUS_SELECTED_HFXO
0x00000002UL
|
|
#define
|
_CMU_HFCLKSTATUS_SELECTED_LFRCO
0x00000003UL
|
|
#define
|
_CMU_HFCLKSTATUS_SELECTED_LFXO
0x00000004UL
|
|
#define
|
_CMU_HFCLKSTATUS_SELECTED_MASK
0x7UL
|
|
#define
|
_CMU_HFCLKSTATUS_SELECTED_SHIFT
0
|
|
#define
|
_CMU_HFCOREPRESC_MASK
0x0001FF00UL
|
|
#define
|
_CMU_HFCOREPRESC_PRESC_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_HFCOREPRESC_PRESC_MASK
0x1FF00UL
|
|
#define
|
_CMU_HFCOREPRESC_PRESC_NODIVISION
0x00000000UL
|
|
#define
|
_CMU_HFCOREPRESC_PRESC_SHIFT
8
|
|
#define
|
_CMU_HFCOREPRESC_RESETVALUE
0x00000000UL
|
|
#define
|
_CMU_HFEXPPRESC_MASK
0x00001F00UL
|
|
#define
|
_CMU_HFEXPPRESC_PRESC_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_HFEXPPRESC_PRESC_MASK
0x1F00UL
|
|
#define
|
_CMU_HFEXPPRESC_PRESC_NODIVISION
0x00000000UL
|
|
#define
|
_CMU_HFEXPPRESC_PRESC_SHIFT
8
|
|
#define
|
_CMU_HFEXPPRESC_RESETVALUE
0x00000000UL
|
|
#define
|
_CMU_HFPERCLKEN0_ACMP0_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_HFPERCLKEN0_ACMP0_MASK
0x20UL
|
|
#define
|
_CMU_HFPERCLKEN0_ACMP0_SHIFT
5
|
|
#define
|
_CMU_HFPERCLKEN0_ACMP1_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_HFPERCLKEN0_ACMP1_MASK
0x40UL
|
|
#define
|
_CMU_HFPERCLKEN0_ACMP1_SHIFT
6
|
|
#define
|
_CMU_HFPERCLKEN0_ADC0_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_HFPERCLKEN0_ADC0_MASK
0x200UL
|
|
#define
|
_CMU_HFPERCLKEN0_ADC0_SHIFT
9
|
|
#define
|
_CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_HFPERCLKEN0_CRYOTIMER_MASK
0x80UL
|
|
#define
|
_CMU_HFPERCLKEN0_CRYOTIMER_SHIFT
7
|
|
#define
|
_CMU_HFPERCLKEN0_I2C0_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_HFPERCLKEN0_I2C0_MASK
0x100UL
|
|
#define
|
_CMU_HFPERCLKEN0_I2C0_SHIFT
8
|
|
#define
|
_CMU_HFPERCLKEN0_IDAC0_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_HFPERCLKEN0_IDAC0_MASK
0x800UL
|
|
#define
|
_CMU_HFPERCLKEN0_IDAC0_SHIFT
11
|
|
#define
|
_CMU_HFPERCLKEN0_MASK
0x00001FFFUL
|
|
#define
|
_CMU_HFPERCLKEN0_RESETVALUE
0x00000000UL
|
|
#define
|
_CMU_HFPERCLKEN0_TIMER0_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_HFPERCLKEN0_TIMER0_MASK
0x1UL
|
|
#define
|
_CMU_HFPERCLKEN0_TIMER0_SHIFT
0
|
|
#define
|
_CMU_HFPERCLKEN0_TIMER1_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_HFPERCLKEN0_TIMER1_MASK
0x2UL
|
|
#define
|
_CMU_HFPERCLKEN0_TIMER1_SHIFT
1
|
|
#define
|
_CMU_HFPERCLKEN0_TRNG0_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_HFPERCLKEN0_TRNG0_MASK
0x1000UL
|
|
#define
|
_CMU_HFPERCLKEN0_TRNG0_SHIFT
12
|
|
#define
|
_CMU_HFPERCLKEN0_USART0_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_HFPERCLKEN0_USART0_MASK
0x8UL
|
|
#define
|
_CMU_HFPERCLKEN0_USART0_SHIFT
3
|
|
#define
|
_CMU_HFPERCLKEN0_USART1_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_HFPERCLKEN0_USART1_MASK
0x10UL
|
|
#define
|
_CMU_HFPERCLKEN0_USART1_SHIFT
4
|
|
#define
|
_CMU_HFPERCLKEN0_VDAC0_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_HFPERCLKEN0_VDAC0_MASK
0x400UL
|
|
#define
|
_CMU_HFPERCLKEN0_VDAC0_SHIFT
10
|
|
#define
|
_CMU_HFPERCLKEN0_WTIMER0_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_HFPERCLKEN0_WTIMER0_MASK
0x4UL
|
|
#define
|
_CMU_HFPERCLKEN0_WTIMER0_SHIFT
2
|
|
#define
|
_CMU_HFPERPRESC_MASK
0x0001FF00UL
|
|
#define
|
_CMU_HFPERPRESC_PRESC_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_HFPERPRESC_PRESC_MASK
0x1FF00UL
|
|
#define
|
_CMU_HFPERPRESC_PRESC_NODIVISION
0x00000000UL
|
|
#define
|
_CMU_HFPERPRESC_PRESC_SHIFT
8
|
|
#define
|
_CMU_HFPERPRESC_RESETVALUE
0x00000000UL
|
|
#define
|
_CMU_HFPRESC_HFCLKLEPRESC_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_HFPRESC_HFCLKLEPRESC_DIV2
0x00000000UL
|
|
#define
|
_CMU_HFPRESC_HFCLKLEPRESC_DIV4
0x00000001UL
|
|
#define
|
_CMU_HFPRESC_HFCLKLEPRESC_MASK
0x1000000UL
|
|
#define
|
_CMU_HFPRESC_HFCLKLEPRESC_SHIFT
24
|
|
#define
|
_CMU_HFPRESC_MASK
0x01001F00UL
|
|
#define
|
_CMU_HFPRESC_PRESC_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_HFPRESC_PRESC_MASK
0x1F00UL
|
|
#define
|
_CMU_HFPRESC_PRESC_NODIVISION
0x00000000UL
|
|
#define
|
_CMU_HFPRESC_PRESC_SHIFT
8
|
|
#define
|
_CMU_HFPRESC_RESETVALUE
0x00000000UL
|
|
#define
|
_CMU_HFRCOCTRL_CLKDIV_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_HFRCOCTRL_CLKDIV_DIV1
0x00000000UL
|
|
#define
|
_CMU_HFRCOCTRL_CLKDIV_DIV2
0x00000001UL
|
|
#define
|
_CMU_HFRCOCTRL_CLKDIV_DIV4
0x00000002UL
|
|
#define
|
_CMU_HFRCOCTRL_CLKDIV_MASK
0x6000000UL
|
|
#define
|
_CMU_HFRCOCTRL_CLKDIV_SHIFT
25
|
|
#define
|
_CMU_HFRCOCTRL_CMPBIAS_DEFAULT
0x00000002UL
|
|
#define
|
_CMU_HFRCOCTRL_CMPBIAS_MASK
0xE00000UL
|
|
#define
|
_CMU_HFRCOCTRL_CMPBIAS_SHIFT
21
|
|
#define
|
_CMU_HFRCOCTRL_FINETUNING_DEFAULT
0x0000001FUL
|
|
#define
|
_CMU_HFRCOCTRL_FINETUNING_MASK
0x3F00UL
|
|
#define
|
_CMU_HFRCOCTRL_FINETUNING_SHIFT
8
|
|
#define
|
_CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_HFRCOCTRL_FINETUNINGEN_MASK
0x8000000UL
|
|
#define
|
_CMU_HFRCOCTRL_FINETUNINGEN_SHIFT
27
|
|
#define
|
_CMU_HFRCOCTRL_FREQRANGE_DEFAULT
0x00000008UL
|
|
#define
|
_CMU_HFRCOCTRL_FREQRANGE_MASK
0x1F0000UL
|
|
#define
|
_CMU_HFRCOCTRL_FREQRANGE_SHIFT
16
|
|
#define
|
_CMU_HFRCOCTRL_LDOHP_DEFAULT
0x00000001UL
|
|
#define
|
_CMU_HFRCOCTRL_LDOHP_MASK
0x1000000UL
|
|
#define
|
_CMU_HFRCOCTRL_LDOHP_SHIFT
24
|
|
#define
|
_CMU_HFRCOCTRL_MASK
0xFFFF3F7FUL
|
|
#define
|
_CMU_HFRCOCTRL_RESETVALUE
0xB1481F7FUL
|
|
#define
|
_CMU_HFRCOCTRL_TUNING_DEFAULT
0x0000007FUL
|
|
#define
|
_CMU_HFRCOCTRL_TUNING_MASK
0x7FUL
|
|
#define
|
_CMU_HFRCOCTRL_TUNING_SHIFT
0
|
|
#define
|
_CMU_HFRCOCTRL_VREFTC_DEFAULT
0x0000000BUL
|
|
#define
|
_CMU_HFRCOCTRL_VREFTC_MASK
0xF0000000UL
|
|
#define
|
_CMU_HFRCOCTRL_VREFTC_SHIFT
28
|
|
#define
|
_CMU_HFRCOSS_MASK
0x00001F07UL
|
|
#define
|
_CMU_HFRCOSS_RESETVALUE
0x00000000UL
|
|
#define
|
_CMU_HFRCOSS_SSAMP_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_HFRCOSS_SSAMP_MASK
0x7UL
|
|
#define
|
_CMU_HFRCOSS_SSAMP_SHIFT
0
|
|
#define
|
_CMU_HFRCOSS_SSINV_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_HFRCOSS_SSINV_MASK
0x1F00UL
|
|
#define
|
_CMU_HFRCOSS_SSINV_SHIFT
8
|
|
#define
|
_CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_HFXOCTRL_AUTOSTARTEM0EM1_MASK
0x10000000UL
|
|
#define
|
_CMU_HFXOCTRL_AUTOSTARTEM0EM1_SHIFT
28
|
|
#define
|
_CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_MASK
0x20000000UL
|
|
#define
|
_CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_SHIFT
29
|
|
#define
|
_CMU_HFXOCTRL_LFTIMEOUT_0CYCLES
0x00000000UL
|
|
#define
|
_CMU_HFXOCTRL_LFTIMEOUT_16CYCLES
0x00000003UL
|
|
#define
|
_CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES
0x00000006UL
|
|
#define
|
_CMU_HFXOCTRL_LFTIMEOUT_2CYCLES
0x00000001UL
|
|
#define
|
_CMU_HFXOCTRL_LFTIMEOUT_32CYCLES
0x00000004UL
|
|
#define
|
_CMU_HFXOCTRL_LFTIMEOUT_4CYCLES
0x00000002UL
|
|
#define
|
_CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES
0x00000007UL
|
|
#define
|
_CMU_HFXOCTRL_LFTIMEOUT_64CYCLES
0x00000005UL
|
|
#define
|
_CMU_HFXOCTRL_LFTIMEOUT_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_HFXOCTRL_LFTIMEOUT_MASK
0x7000000UL
|
|
#define
|
_CMU_HFXOCTRL_LFTIMEOUT_SHIFT
24
|
|
#define
|
_CMU_HFXOCTRL_LOWPOWER_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_HFXOCTRL_LOWPOWER_MASK
0x100UL
|
|
#define
|
_CMU_HFXOCTRL_LOWPOWER_SHIFT
8
|
|
#define
|
_CMU_HFXOCTRL_MASK
0x37000731UL
|
|
#define
|
_CMU_HFXOCTRL_MODE_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_HFXOCTRL_MODE_EXTCLK
0x00000001UL
|
|
#define
|
_CMU_HFXOCTRL_MODE_MASK
0x1UL
|
|
#define
|
_CMU_HFXOCTRL_MODE_SHIFT
0
|
|
#define
|
_CMU_HFXOCTRL_MODE_XTAL
0x00000000UL
|
|
#define
|
_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_AUTOCMD
0x00000000UL
|
|
#define
|
_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_CMD
0x00000001UL
|
|
#define
|
_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MANUAL
0x00000002UL
|
|
#define
|
_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK
0x30UL
|
|
#define
|
_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_SHIFT
4
|
|
#define
|
_CMU_HFXOCTRL_RESETVALUE
0x00000000UL
|
|
#define
|
_CMU_HFXOCTRL_XTI2GND_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_HFXOCTRL_XTI2GND_MASK
0x200UL
|
|
#define
|
_CMU_HFXOCTRL_XTI2GND_SHIFT
9
|
|
#define
|
_CMU_HFXOCTRL_XTO2GND_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_HFXOCTRL_XTO2GND_MASK
0x400UL
|
|
#define
|
_CMU_HFXOCTRL_XTO2GND_SHIFT
10
|
|
#define
|
_CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT
0x000000A0UL
|
|
#define
|
_CMU_HFXOSTARTUPCTRL_CTUNE_MASK
0xFF800UL
|
|
#define
|
_CMU_HFXOSTARTUPCTRL_CTUNE_SHIFT
11
|
|
#define
|
_CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT
0x00000020UL
|
|
#define
|
_CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_MASK
0x7FUL
|
|
#define
|
_CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_SHIFT
0
|
|
#define
|
_CMU_HFXOSTARTUPCTRL_MASK
0x000FF87FUL
|
|
#define
|
_CMU_HFXOSTARTUPCTRL_RESETVALUE
0x00050020UL
|
|
#define
|
_CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT
0x00000168UL
|
|
#define
|
_CMU_HFXOSTEADYSTATECTRL_CTUNE_MASK
0xFF800UL
|
|
#define
|
_CMU_HFXOSTEADYSTATECTRL_CTUNE_SHIFT
11
|
|
#define
|
_CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT
0x00000007UL
|
|
#define
|
_CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_MASK
0x7FUL
|
|
#define
|
_CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_SHIFT
0
|
|
#define
|
_CMU_HFXOSTEADYSTATECTRL_MASK
0xF70FFFFFUL
|
|
#define
|
_CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT
0x00000000UL
|
|
#define
|
_CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_MASK
0x4000000UL
|
|
#define
|
_CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_SHIFT
26
|
|
#define
|
_CMU_HFXOSTEADYSTATECTRL_REGISH_DEFAULT
0x0000000AUL
|
|
#define
|
_CMU_HFXOSTEADYSTATECTRL_REGISH_MASK
0x780UL
|
|
#define
|
_CMU_HFXOSTEADYSTATECTRL_REGISH_SHIFT
7
|
|
#define
|
_CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_DEFAULT
0x0000000AUL
|
|
#define
|
_CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_MASK
0xF0000000UL
|
|
#define
|
_CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_SHIFT
28
|
|
#define
|
_CMU_HFXOSTEADYSTATECTRL_REGSELILOW_DEFAULT
0x00000003UL
|
|
#define
|
_CMU_HFXOSTEADYSTATECTRL_REGSELILOW_MASK
0x3000000UL
|
|
#define
|
_CMU_HFXOSTEADYSTATECTRL_REGSELILOW_SHIFT
24
|
|
#define
|
_CMU_HFXOSTEADYSTATECTRL_RESETVALUE
0xA30B4507UL
|
|
#define
|
_CMU_HFXOTIMEOUTCTRL_MASK
0x000FF0FFUL
|
|
#define
|
_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES
0x00000002UL
|
|
#define
|
_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES
0x00000009UL
|
|
#define
|
_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES
0x00000005UL
|
|
#define
|
_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES
0x00000004UL
|
|
#define
|
_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES
0x00000000UL
|
|
#define
|
_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES
0x00000006UL
|
|
#define
|
_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES
0x00000003UL
|
|
#define
|
_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES
0x0000000AUL
|
|
#define
|
_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES
0x00000001UL
|
|
#define
|
_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES
0x00000007UL
|
|
#define
|
_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES
0x00000008UL
|
|
#define
|
_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT
0x0000000AUL
|
|
#define
|
_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_MASK
0xF000UL
|
|
#define
|
_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_SHIFT
12
|
|
#define
|
_CMU_HFXOTIMEOUTCTRL_RESETVALUE
0x0002A067UL
|
|
#define
|
_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_16CYCLES
0x00000002UL
|
|
#define
|
_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_16KCYCLES
0x00000009UL
|
|
#define
|
_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_1KCYCLES
0x00000005UL
|
|
#define
|
_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_256CYCLES
0x00000004UL
|
|
#define
|
_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_2CYCLES
0x00000000UL
|
|
#define
|
_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_2KCYCLES
0x00000006UL
|
|
#define
|
_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_32CYCLES
0x00000003UL
|
|
#define
|
_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_32KCYCLES
0x0000000AUL
|
|
#define
|
_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_4CYCLES
0x00000001UL
|
|
#define
|
_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_4KCYCLES
0x00000007UL
|