|
#define
|
_EMU_CMD_EM01VSCALE0_DEFAULT
0x00000000UL
|
|
#define
|
_EMU_CMD_EM01VSCALE0_MASK
0x10UL
|
|
#define
|
_EMU_CMD_EM01VSCALE0_SHIFT
4
|
|
#define
|
_EMU_CMD_EM01VSCALE2_DEFAULT
0x00000000UL
|
|
#define
|
_EMU_CMD_EM01VSCALE2_MASK
0x40UL
|
|
#define
|
_EMU_CMD_EM01VSCALE2_SHIFT
6
|
|
#define
|
_EMU_CMD_EM4UNLATCH_DEFAULT
0x00000000UL
|
|
#define
|
_EMU_CMD_EM4UNLATCH_MASK
0x1UL
|
|
#define
|
_EMU_CMD_EM4UNLATCH_SHIFT
0
|
|
#define
|
_EMU_CMD_MASK
0x00000051UL
|
|
#define
|
_EMU_CMD_RESETVALUE
0x00000000UL
|
|
#define
|
_EMU_CTRL_EM01LD_DEFAULT
0x00000000UL
|
|
#define
|
_EMU_CTRL_EM01LD_MASK
0x8UL
|
|
#define
|
_EMU_CTRL_EM01LD_SHIFT
3
|
|
#define
|
_EMU_CTRL_EM23VSCALE_DEFAULT
0x00000000UL
|
|
#define
|
_EMU_CTRL_EM23VSCALE_MASK
0x300UL
|
|
#define
|
_EMU_CTRL_EM23VSCALE_RESV
0x00000003UL
|
|
#define
|
_EMU_CTRL_EM23VSCALE_SHIFT
8
|
|
#define
|
_EMU_CTRL_EM23VSCALE_VSCALE0
0x00000002UL
|
|
#define
|
_EMU_CTRL_EM23VSCALE_VSCALE2
0x00000000UL
|
|
#define
|
_EMU_CTRL_EM23VSCALEAUTOWSEN_DEFAULT
0x00000000UL
|
|
#define
|
_EMU_CTRL_EM23VSCALEAUTOWSEN_MASK
0x10UL
|
|
#define
|
_EMU_CTRL_EM23VSCALEAUTOWSEN_SHIFT
4
|
|
#define
|
_EMU_CTRL_EM2BLOCK_DEFAULT
0x00000000UL
|
|
#define
|
_EMU_CTRL_EM2BLOCK_MASK
0x2UL
|
|
#define
|
_EMU_CTRL_EM2BLOCK_SHIFT
1
|
|
#define
|
_EMU_CTRL_EM2BODDIS_DEFAULT
0x00000000UL
|
|
#define
|
_EMU_CTRL_EM2BODDIS_MASK
0x4UL
|
|
#define
|
_EMU_CTRL_EM2BODDIS_SHIFT
2
|
|
#define
|
_EMU_CTRL_EM4HVSCALE_DEFAULT
0x00000000UL
|
|
#define
|
_EMU_CTRL_EM4HVSCALE_MASK
0x30000UL
|
|
#define
|
_EMU_CTRL_EM4HVSCALE_RESV
0x00000003UL
|
|
#define
|
_EMU_CTRL_EM4HVSCALE_SHIFT
16
|
|
#define
|
_EMU_CTRL_EM4HVSCALE_VSCALE0
0x00000002UL
|
|
#define
|
_EMU_CTRL_EM4HVSCALE_VSCALE2
0x00000000UL
|
|
#define
|
_EMU_CTRL_MASK
0x0003031EUL
|
|
#define
|
_EMU_CTRL_RESETVALUE
0x00000000UL
|
|
#define
|
_EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT
0x00000000UL
|
|
#define
|
_EMU_DCDCCLIMCTRL_BYPLIMEN_MASK
0x2000UL
|
|
#define
|
_EMU_DCDCCLIMCTRL_BYPLIMEN_SHIFT
13
|
|
#define
|
_EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT
0x00000001UL
|
|
#define
|
_EMU_DCDCCLIMCTRL_CLIMBLANKDLY_MASK
0x300UL
|
|
#define
|
_EMU_DCDCCLIMCTRL_CLIMBLANKDLY_SHIFT
8
|
|
#define
|
_EMU_DCDCCLIMCTRL_MASK
0x00002300UL
|
|
#define
|
_EMU_DCDCCLIMCTRL_RESETVALUE
0x00000100UL
|
|
#define
|
_EMU_DCDCCTRL_DCDCMODE_BYPASS
0x00000000UL
|
|
#define
|
_EMU_DCDCCTRL_DCDCMODE_DEFAULT
0x00000003UL
|
|
#define
|
_EMU_DCDCCTRL_DCDCMODE_LOWNOISE
0x00000001UL
|
|
#define
|
_EMU_DCDCCTRL_DCDCMODE_LOWPOWER
0x00000002UL
|
|
#define
|
_EMU_DCDCCTRL_DCDCMODE_MASK
0x3UL
|
|
#define
|
_EMU_DCDCCTRL_DCDCMODE_OFF
0x00000003UL
|
|
#define
|
_EMU_DCDCCTRL_DCDCMODE_SHIFT
0
|
|
#define
|
_EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT
0x00000001UL
|
|
#define
|
_EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER
0x00000001UL
|
|
#define
|
_EMU_DCDCCTRL_DCDCMODEEM23_EM23SW
0x00000000UL
|
|
#define
|
_EMU_DCDCCTRL_DCDCMODEEM23_MASK
0x10UL
|
|
#define
|
_EMU_DCDCCTRL_DCDCMODEEM23_SHIFT
4
|
|
#define
|
_EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT
0x00000001UL
|
|
#define
|
_EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER
0x00000001UL
|
|
#define
|
_EMU_DCDCCTRL_DCDCMODEEM4_EM4SW
0x00000000UL
|
|
#define
|
_EMU_DCDCCTRL_DCDCMODEEM4_MASK
0x20UL
|
|
#define
|
_EMU_DCDCCTRL_DCDCMODEEM4_SHIFT
5
|
|
#define
|
_EMU_DCDCCTRL_MASK
0x00000033UL
|
|
#define
|
_EMU_DCDCCTRL_RESETVALUE
0x00000033UL
|
|
#define
|
_EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT
0x00000002UL
|
|
#define
|
_EMU_DCDCLNCOMPCTRL_COMPENC1_MASK
0x300000UL
|
|
#define
|
_EMU_DCDCLNCOMPCTRL_COMPENC1_SHIFT
20
|
|
#define
|
_EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT
0x00000007UL
|
|
#define
|
_EMU_DCDCLNCOMPCTRL_COMPENC2_MASK
0x7000000UL
|
|
#define
|
_EMU_DCDCLNCOMPCTRL_COMPENC2_SHIFT
24
|
|
#define
|
_EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT
0x00000005UL
|
|
#define
|
_EMU_DCDCLNCOMPCTRL_COMPENC3_MASK
0xF0000000UL
|
|
#define
|
_EMU_DCDCLNCOMPCTRL_COMPENC3_SHIFT
28
|
|
#define
|
_EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT
0x00000007UL
|
|
#define
|
_EMU_DCDCLNCOMPCTRL_COMPENR1_MASK
0x7UL
|
|
#define
|
_EMU_DCDCLNCOMPCTRL_COMPENR1_SHIFT
0
|
|
#define
|
_EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT
0x00000007UL
|
|
#define
|
_EMU_DCDCLNCOMPCTRL_COMPENR2_MASK
0x1F0UL
|
|
#define
|
_EMU_DCDCLNCOMPCTRL_COMPENR2_SHIFT
4
|
|
#define
|
_EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT
0x00000004UL
|
|
#define
|
_EMU_DCDCLNCOMPCTRL_COMPENR3_MASK
0xF000UL
|
|
#define
|
_EMU_DCDCLNCOMPCTRL_COMPENR3_SHIFT
12
|
|
#define
|
_EMU_DCDCLNCOMPCTRL_MASK
0xF730F1F7UL
|
|
#define
|
_EMU_DCDCLNCOMPCTRL_RESETVALUE
0x57204077UL
|
|
#define
|
_EMU_DCDCLNFREQCTRL_MASK
0x1F000007UL
|
|
#define
|
_EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT
0x00000000UL
|
|
#define
|
_EMU_DCDCLNFREQCTRL_RCOBAND_MASK
0x7UL
|
|
#define
|
_EMU_DCDCLNFREQCTRL_RCOBAND_SHIFT
0
|
|
#define
|
_EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT
0x00000010UL
|
|
#define
|
_EMU_DCDCLNFREQCTRL_RCOTRIM_MASK
0x1F000000UL
|
|
#define
|
_EMU_DCDCLNFREQCTRL_RCOTRIM_SHIFT
24
|
|
#define
|
_EMU_DCDCLNFREQCTRL_RESETVALUE
0x10000000UL
|
|
#define
|
_EMU_DCDCLNVCTRL_LNATT_DEFAULT
0x00000000UL
|
|
#define
|
_EMU_DCDCLNVCTRL_LNATT_DIV3
0x00000000UL
|
|
#define
|
_EMU_DCDCLNVCTRL_LNATT_DIV6
0x00000001UL
|
|
#define
|
_EMU_DCDCLNVCTRL_LNATT_MASK
0x2UL
|
|
#define
|
_EMU_DCDCLNVCTRL_LNATT_SHIFT
1
|
|
#define
|
_EMU_DCDCLNVCTRL_LNVREF_DEFAULT
0x00000071UL
|
|
#define
|
_EMU_DCDCLNVCTRL_LNVREF_MASK
0x7F00UL
|
|
#define
|
_EMU_DCDCLNVCTRL_LNVREF_SHIFT
8
|
|
#define
|
_EMU_DCDCLNVCTRL_MASK
0x00007F02UL
|
|
#define
|
_EMU_DCDCLNVCTRL_RESETVALUE
0x00007100UL
|
|
#define
|
_EMU_DCDCLPCTRL_LPBLANK_DEFAULT
0x00000001UL
|
|
#define
|
_EMU_DCDCLPCTRL_LPBLANK_MASK
0x6000000UL
|
|
#define
|
_EMU_DCDCLPCTRL_LPBLANK_SHIFT
25
|
|
#define
|
_EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_DEFAULT
0x00000000UL
|
|
#define
|
_EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_MASK
0xF000UL
|
|
#define
|
_EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_SHIFT
12
|
|
#define
|
_EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT
0x00000001UL
|
|
#define
|
_EMU_DCDCLPCTRL_LPVREFDUTYEN_MASK
0x1000000UL
|
|
#define
|
_EMU_DCDCLPCTRL_LPVREFDUTYEN_SHIFT
24
|
|
#define
|
_EMU_DCDCLPCTRL_MASK
0x0700F000UL
|
|
#define
|
_EMU_DCDCLPCTRL_RESETVALUE
0x03000000UL
|
|
#define
|
_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS0
0x00000000UL
|
|
#define
|
_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS1
0x00000001UL
|
|
#define
|
_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS2
0x00000002UL
|
|
#define
|
_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3
0x00000003UL
|
|
#define
|
_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_DEFAULT
0x00000003UL
|
|
#define
|
_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK
0x300UL
|
|
#define
|
_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_SHIFT
8
|
|
#define
|
_EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_DEFAULT
0x00000000UL
|
|
#define
|
_EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_MASK
0xF000UL
|
|
#define
|
_EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_SHIFT
12
|
|
#define
|
_EMU_DCDCLPEM01CFG_MASK
0x0000F300UL
|
|
#define
|
_EMU_DCDCLPEM01CFG_RESETVALUE
0x00000300UL
|
|
#define
|
_EMU_DCDCLPVCTRL_LPATT_DEFAULT
0x00000000UL
|
|
#define
|
_EMU_DCDCLPVCTRL_LPATT_DIV4
0x00000000UL
|
|
#define
|
_EMU_DCDCLPVCTRL_LPATT_DIV8
0x00000001UL
|
|
#define
|
_EMU_DCDCLPVCTRL_LPATT_MASK
0x1UL
|
|
#define
|
_EMU_DCDCLPVCTRL_LPATT_SHIFT
0
|
|
#define
|
_EMU_DCDCLPVCTRL_LPVREF_DEFAULT
0x000000B4UL
|
|
#define
|
_EMU_DCDCLPVCTRL_LPVREF_MASK
0x1FEUL
|
|
#define
|
_EMU_DCDCLPVCTRL_LPVREF_SHIFT
1
|
|
#define
|
_EMU_DCDCLPVCTRL_MASK
0x000001FFUL
|
|
#define
|
_EMU_DCDCLPVCTRL_RESETVALUE
0x00000168UL
|
|
#define
|
_EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT
0x00000000UL
|
|
#define
|
_EMU_DCDCMISCCTRL_BYPLIMSEL_MASK
0xF0000UL
|
|
#define
|
_EMU_DCDCMISCCTRL_BYPLIMSEL_SHIFT
16
|
|
#define
|
_EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT
0x00000003UL
|
|
#define
|
_EMU_DCDCMISCCTRL_LNCLIMILIMSEL_MASK
0x7000000UL
|
|
#define
|
_EMU_DCDCMISCCTRL_LNCLIMILIMSEL_SHIFT
24
|
|
#define
|
_EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT
0x00000000UL
|
|
#define
|
_EMU_DCDCMISCCTRL_LNFORCECCM_MASK
0x1UL
|
|
#define
|
_EMU_DCDCMISCCTRL_LNFORCECCM_SHIFT
0
|
|
#define
|
_EMU_DCDCMISCCTRL_LNFORCECCMIMM_DEFAULT
0x00000000UL
|
|
#define
|
_EMU_DCDCMISCCTRL_LNFORCECCMIMM_MASK
0x20UL
|
|
#define
|
_EMU_DCDCMISCCTRL_LNFORCECCMIMM_SHIFT
5
|
|
#define
|
_EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT
0x00000001UL
|
|
#define
|
_EMU_DCDCMISCCTRL_LPCLIMILIMSEL_MASK
0x700000UL
|
|
#define
|
_EMU_DCDCMISCCTRL_LPCLIMILIMSEL_SHIFT
20
|
|
#define
|
_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS0
0x00000000UL
|
|
#define
|
_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS1
0x00000001UL
|
|
#define
|
_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS2
0x00000002UL
|
|
#define
|
_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS3
0x00000003UL
|
|
#define
|
_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_DEFAULT
0x00000000UL
|
|
#define
|
_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_MASK
0x30000000UL
|
|
#define
|
_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_SHIFT
28
|
|
#define
|
_EMU_DCDCMISCCTRL_LPCMPHYSDIS_DEFAULT
0x00000001UL
|
|
#define
|
_EMU_DCDCMISCCTRL_LPCMPHYSDIS_MASK
0x2UL
|
|
#define
|
_EMU_DCDCMISCCTRL_LPCMPHYSDIS_SHIFT
1
|
|
#define
|
_EMU_DCDCMISCCTRL_LPCMPHYSHI_DEFAULT
0x00000001UL
|
|
#define
|
_EMU_DCDCMISCCTRL_LPCMPHYSHI_MASK
0x4UL
|
|
#define
|
_EMU_DCDCMISCCTRL_LPCMPHYSHI_SHIFT
2
|
|
#define
|
_EMU_DCDCMISCCTRL_MASK
0x377FFF27UL
|
|
#define
|
_EMU_DCDCMISCCTRL_NFETCNT_DEFAULT
0x00000007UL
|
|
#define
|
_EMU_DCDCMISCCTRL_NFETCNT_MASK
0xF000UL
|
|
#define
|
_EMU_DCDCMISCCTRL_NFETCNT_SHIFT
12
|
|
#define
|
_EMU_DCDCMISCCTRL_PFETCNT_DEFAULT
0x00000007UL
|
|
#define
|
_EMU_DCDCMISCCTRL_PFETCNT_MASK
0xF00UL
|
|
#define
|
_EMU_DCDCMISCCTRL_PFETCNT_SHIFT
8
|
|
#define
|
_EMU_DCDCMISCCTRL_RESETVALUE
0x03107706UL
|
|
#define
|
_EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT
0x00000000UL
|
|
#define
|
_EMU_DCDCSYNC_DCDCCTRLBUSY_MASK
0x1UL
|
|
#define
|
_EMU_DCDCSYNC_DCDCCTRLBUSY_SHIFT
0
|
|
#define
|
_EMU_DCDCSYNC_MASK
0x00000001UL
|
|
#define
|
_EMU_DCDCSYNC_RESETVALUE
0x00000000UL
|
|
#define
|
_EMU_DCDCZDETCTRL_MASK
0x00000370UL
|
|
#define
|
_EMU_DCDCZDETCTRL_RESETVALUE
0x00000150UL
|
|
#define
|
_EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT
0x00000001UL
|
|
#define
|
_EMU_DCDCZDETCTRL_ZDETBLANKDLY_MASK
0x300UL
|
|
#define
|
_EMU_DCDCZDETCTRL_ZDETBLANKDLY_SHIFT
8
|
|
#define
|
_EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT
0x00000005UL
|
|
#define
|
_EMU_DCDCZDETCTRL_ZDETILIMSEL_MASK
0x70UL
|
|
#define
|
_EMU_DCDCZDETCTRL_ZDETILIMSEL_SHIFT
4
|
|
#define
|
_EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_DEFAULT
0x00000000UL
|
|
#define
|
_EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_MASK
0x1UL
|
|
#define
|
_EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_SHIFT
0
|
|
#define
|
_EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_DEFAULT
0x00000000UL
|
|
#define
|
_EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_MASK
0x2UL
|
|
#define
|
_EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_SHIFT
1
|
|
#define
|
_EMU_EM23PERNORETAINCMD_ADC0UNLOCK_DEFAULT
0x00000000UL
|
|
#define
|
_EMU_EM23PERNORETAINCMD_ADC0UNLOCK_MASK
0x200UL
|
|
#define
|
_EMU_EM23PERNORETAINCMD_ADC0UNLOCK_SHIFT
9
|
|
#define
|
_EMU_EM23PERNORETAINCMD_DAC0UNLOCK_DEFAULT
0x00000000UL
|
|
#define
|
_EMU_EM23PERNORETAINCMD_DAC0UNLOCK_MASK
0x80UL
|
|
#define
|
_EMU_EM23PERNORETAINCMD_DAC0UNLOCK_SHIFT
7
|
|
#define
|
_EMU_EM23PERNORETAINCMD_I2C0UNLOCK_DEFAULT
0x00000000UL
|
|
#define
|
_EMU_EM23PERNORETAINCMD_I2C0UNLOCK_MASK
0x20UL
|
|
#define
|
_EMU_EM23PERNORETAINCMD_I2C0UNLOCK_SHIFT
5
|
|
#define
|
_EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_DEFAULT
0x00000000UL
|
|
#define
|
_EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_MASK
0x100UL
|
|
#define
|
_EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_SHIFT
8
|
|
#define
|
_EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_DEFAULT
0x00000000UL
|
|
#define
|
_EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_MASK
0x2000UL
|
|
#define
|
_EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_SHIFT
13
|
|
#define
|
_EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_DEFAULT
0x00000000UL
|
|
#define
|
_EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_MASK
0x400UL
|
|
#define
|
_EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_SHIFT
10
|
|
#define
|
_EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_DEFAULT
0x00000000UL
|
|
#define
|
_EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_MASK
0x8000UL
|
|
#define
|
_EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_SHIFT
15
|
|
#define
|
_EMU_EM23PERNORETAINCMD_MASK
0x0000BFA7UL
|
|
#define
|
_EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_DEFAULT
0x00000000UL
|
|
#define
|
_EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_MASK
0x4UL
|
|
#define
|
_EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_SHIFT
2
|
|
#define
|
_EMU_EM23PERNORETAINCMD_RESETVALUE
0x00000000UL
|
|
#define
|
_EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_DEFAULT
0x00000000UL
|
|
#define
|
_EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_MASK
0x800UL
|
|
#define
|
_EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_SHIFT
11
|
|
#define
|
_EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_DEFAULT
0x00000000UL
|
|
#define
|
_EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_MASK
0x1000UL
|
|
#define
|
_EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_SHIFT
12
|
|
#define
|
_EMU_EM23PERNORETAINCTRL_ACMP0DIS_DEFAULT
0x00000000UL
|
|
#define
|
_EMU_EM23PERNORETAINCTRL_ACMP0DIS_MASK
0x1UL
|
|
#define
|
_EMU_EM23PERNORETAINCTRL_ACMP0DIS_SHIFT
0
|
|
#define
|
_EMU_EM23PERNORETAINCTRL_ACMP1DIS_DEFAULT
0x00000000UL
|
|
#define
|
_EMU_EM23PERNORETAINCTRL_ACMP1DIS_MASK
0x2UL
|
|
#define
|
_EMU_EM23PERNORETAINCTRL_ACMP1DIS_SHIFT
1
|
|
#define
|
_EMU_EM23PERNORETAINCTRL_ADC0DIS_DEFAULT
0x00000000UL
|
|
#define
|
_EMU_EM23PERNORETAINCTRL_ADC0DIS_MASK
0x200UL
|
|
#define
|
_EMU_EM23PERNORETAINCTRL_ADC0DIS_SHIFT
9
|
|
#define
|
_EMU_EM23PERNORETAINCTRL_DAC0DIS_DEFAULT
0x00000000UL
|
|
#define
|
_EMU_EM23PERNORETAINCTRL_DAC0DIS_MASK
0x80UL
|
|
#define
|
_EMU_EM23PERNORETAINCTRL_DAC0DIS_SHIFT
7
|
|
#define
|
_EMU_EM23PERNORETAINCTRL_I2C0DIS_DEFAULT
0x00000000UL
|
|
#define
|
_EMU_EM23PERNORETAINCTRL_I2C0DIS_MASK
0x20UL
|
|
#define
|
_EMU_EM23PERNORETAINCTRL_I2C0DIS_SHIFT
5
|
|
#define
|
_EMU_EM23PERNORETAINCTRL_IDAC0DIS_DEFAULT
0x00000000UL
|
|
#define
|
_EMU_EM23PERNORETAINCTRL_IDAC0DIS_MASK
0x100UL
|
|
#define
|
_EMU_EM23PERNORETAINCTRL_IDAC0DIS_SHIFT
8
|
|
#define
|
_EMU_EM23PERNORETAINCTRL_LESENSE0DIS_DEFAULT
0x00000000UL
|
|
#define
|
_EMU_EM23PERNORETAINCTRL_LESENSE0DIS_MASK
0x2000UL
|
|
#define
|
_EMU_EM23PERNORETAINCTRL_LESENSE0DIS_SHIFT
13
|
|
#define
|
_EMU_EM23PERNORETAINCTRL_LETIMER0DIS_DEFAULT
0x00000000UL
|
|
#define
|
_EMU_EM23PERNORETAINCTRL_LETIMER0DIS_MASK
0x400UL
|
|
#define
|
_EMU_EM23PERNORETAINCTRL_LETIMER0DIS_SHIFT
10
|
|
#define
|
_EMU_EM23PERNORETAINCTRL_LEUART0DIS_DEFAULT
0x00000000UL
|
|
#define
|
_EMU_EM23PERNORETAINCTRL_LEUART0DIS_MASK
0x8000UL
|
|
#define
|
_EMU_EM23PERNORETAINCTRL_LEUART0DIS_SHIFT
15
|
|
#define
|
_EMU_EM23PERNORETAINCTRL_MASK
0x0000BFA7UL
|
|
#define
|
_EMU_EM23PERNORETAINCTRL_PCNT0DIS_DEFAULT
0x00000000UL
|
|
#define
|
_EMU_EM23PERNORETAINCTRL_PCNT0DIS_MASK
0x4UL
|
|
#define
|
_EMU_EM23PERNORETAINCTRL_PCNT0DIS_SHIFT
2
|
|
#define
|
_EMU_EM23PERNORETAINCTRL_RESETVALUE
0x00000000UL
|
|
#define
|
_EMU_EM23PERNORETAINCTRL_WDOG0DIS_DEFAULT
0x00000000UL
|
|
#define
|
_EMU_EM23PERNORETAINCTRL_WDOG0DIS_MASK
0x800UL
|
|
#define
|
_EMU_EM23PERNORETAINCTRL_WDOG0DIS_SHIFT
11
|
|
#define
|
_EMU_EM23PERNORETAINCTRL_WDOG1DIS_DEFAULT
0x00000000UL
|
|
#define
|
_EMU_EM23PERNORETAINCTRL_WDOG1DIS_MASK
0x1000UL
|
|
#define
|
_EMU_EM23PERNORETAINCTRL_WDOG1DIS_SHIFT
12
|
|
#define
|
_EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_DEFAULT
0x00000000UL
|
|
#define
|
_EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_MASK
0x1UL
|
|
#define
|
_EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_SHIFT
0
|
|
#define
|
_EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_DEFAULT
0x00000000UL
|
|
#define
|
_EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_MASK
0x2UL
|
|
#define
|
_EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_SHIFT
1
|
|
#define
|
_EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_DEFAULT
0x00000000UL
|
|
#define
|
_EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_MASK
0x200UL
|
|
#define
|
_EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_SHIFT
9
|
|
#define
|
_EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_DEFAULT
0x00000000UL
|
|
#define
|
_EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_MASK
0x80UL
|
|
#define
|
_EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_SHIFT
7
|
|
#define
|
_EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_DEFAULT
0x00000000UL
|
|
#define
|
_EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_MASK
0x20UL
|
|
#define
|
_EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_SHIFT
5
|
|
#define
|
_EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_DEFAULT
0x00000000UL
|
|
#define
|
_EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_MASK
0x100UL
|
|
#define
|
_EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_SHIFT
8
|
|
#define
|
_EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_DEFAULT
0x00000000UL
|
|
#define
|
_EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_MASK
0x2000UL
|
|
#define
|
_EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_SHIFT
13
|
|
#define
|
_EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_DEFAULT
0x00000000UL
|
|
#define
|
_EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_MASK
0x400UL
|
|
#define
|
_EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_SHIFT
10
|
|
#define
|
_EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_DEFAULT
0x00000000UL
|
|
#define
|
_EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_MASK
0x8000UL
|
|
#define
|
_EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_SHIFT
15
|
|
#define
|
_EMU_EM23PERNORETAINSTATUS_MASK
0x0000BFA7UL
|
|
#define
|
_EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_DEFAULT
0x00000000UL
|
|
#define
|
_EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_MASK
0x4UL
|
|
#define
|
_EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_SHIFT
2
|
|
#define
|
_EMU_EM23PERNORETAINSTATUS_RESETVALUE
0x00000000UL
|
|
#define
|
_EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_DEFAULT
0x00000000UL
|
|
#define
|
_EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_MASK
0x800UL
|
|
#define
|
_EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_SHIFT
11
|
|
#define
|
_EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_DEFAULT
0x00000000UL
|
|
#define
|
_EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_MASK
0x1000UL
|
|
#define
|
_EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_SHIFT
12
|
|
#define
|
_EMU_EM4CTRL_EM4ENTRY_DEFAULT
0x00000000UL
|
|
#define
|
_EMU_EM4CTRL_EM4ENTRY_MASK
0x30000UL
|
|
#define
|
_EMU_EM4CTRL_EM4ENTRY_SHIFT
16
|
|
#define
|
_EMU_EM4CTRL_EM4IORETMODE_DEFAULT
0x00000000UL
|
|
#define
|
_EMU_EM4CTRL_EM4IORETMODE_DISABLE
0x00000000UL
|
|
#define
|
_EMU_EM4CTRL_EM4IORETMODE_EM4EXIT
0x00000001UL
|
|
#define
|
_EMU_EM4CTRL_EM4IORETMODE_MASK
0x30UL
|
|
#define
|
_EMU_EM4CTRL_EM4IORETMODE_SHIFT
4
|
|
#define
|
_EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH
0x00000002UL
|
|
#define
|
_EMU_EM4CTRL_EM4STATE_DEFAULT
0x00000000UL
|
|
#define
|
_EMU_EM4CTRL_EM4STATE_EM4H
0x00000001UL
|
|
#define
|
_EMU_EM4CTRL_EM4STATE_EM4S
0x00000000UL
|
|
#define
|
_EMU_EM4CTRL_EM4STATE_MASK
0x1UL
|
|
#define
|
_EMU_EM4CTRL_EM4STATE_SHIFT
0
|
|
#define
|
_EMU_EM4CTRL_MASK
0x0003003FUL
|
|
#define
|
_EMU_EM4CTRL_RESETVALUE
0x00000000UL
|
|
#define
|
_EMU_EM4CTRL_RETAINLFRCO_DEFAULT
0x00000000UL
|
|
#define
|
_EMU_EM4CTRL_RETAINLFRCO_MASK
0x2UL
|
|
#define
|
_EMU_EM4CTRL_RETAINLFRCO_SHIFT
1
|
|
#define
|
_EMU_EM4CTRL_RETAINLFXO_DEFAULT
0x00000000UL
|
|
#define
|
_EMU_EM4CTRL_RETAINLFXO_MASK
0x4UL
|
|
#define
|
_EMU_EM4CTRL_RETAINLFXO_SHIFT
2
|
|
#define
|
_EMU_EM4CTRL_RETAINULFRCO_DEFAULT
0x00000000UL
|
|
#define
|
_EMU_EM4CTRL_RETAINULFRCO_MASK
0x8UL
|
|
#define
|
_EMU_EM4CTRL_RETAINULFRCO_SHIFT
3
|
|
#define
|
_EMU_IEN_DCDCINBYPASS_DEFAULT
0x00000000UL
|
|
#define
|
_EMU_IEN_DCDCINBYPASS_MASK
0x100000UL
|
|
#define
|
_EMU_IEN_DCDCINBYPASS_SHIFT
20
|
|
#define
|
_EMU_IEN_DCDCLNRUNNING_DEFAULT
0x00000000UL
|
|
#define
|
_EMU_IEN_DCDCLNRUNNING_MASK
0x80000UL
|
|
#define
|
_EMU_IEN_DCDCLNRUNNING_SHIFT
19
|
|
#define
|
_EMU_IEN_DCDCLPRUNNING_DEFAULT
0x00000000UL
|
|
#define
|
_EMU_IEN_DCDCLPRUNNING_MASK
0x40000UL
|
|
#define
|
_EMU_IEN_DCDCLPRUNNING_SHIFT
18
|
|
#define
|
_EMU_IEN_EM23WAKEUP_DEFAULT
0x00000000UL
|
|
#define
|
_EMU_IEN_EM23WAKEUP_MASK
0x1000000UL
|
|
#define
|
_EMU_IEN_EM23WAKEUP_SHIFT
24
|
|
#define
|
_EMU_IEN_MASK
0xE31FC0FFUL
|
|
#define
|
_EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT
0x00000000UL
|
|
#define
|
_EMU_IEN_NFETOVERCURRENTLIMIT_MASK
0x20000UL
|
|
#define
|
_EMU_IEN_NFETOVERCURRENTLIMIT_SHIFT
17
|
|
#define
|
_EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT
0x00000000UL
|
|
#define
|
_EMU_IEN_PFETOVERCURRENTLIMIT_MASK
0x10000UL
|
|
#define
|
_EMU_IEN_PFETOVERCURRENTLIMIT_SHIFT
16
|
|
#define
|
_EMU_IEN_RESETVALUE
0x00000000UL
|
|
#define
|
_EMU_IEN_TEMP_DEFAULT
0x00000000UL
|
|
#define
|
_EMU_IEN_TEMP_MASK
0x20000000UL
|
|
#define
|
_EMU_IEN_TEMP_SHIFT
29
|
|
#define
|
_EMU_IEN_TEMPHIGH_DEFAULT
0x00000000UL
|
|
#define
|
_EMU_IEN_TEMPHIGH_MASK
0x80000000UL
|
|
#define
|
_EMU_IEN_TEMPHIGH_SHIFT
31
|
|
#define
|
_EMU_IEN_TEMPLOW_DEFAULT
0x00000000UL
|
|
#define
|
_EMU_IEN_TEMPLOW_MASK
0x40000000UL
|
|
#define
|
_EMU_IEN_TEMPLOW_SHIFT
30
|
|
#define
|
_EMU_IEN_VMONALTAVDDFALL_DEFAULT
0x00000000UL
|
|
#define
|
_EMU_IEN_VMONALTAVDDFALL_MASK
0x4UL
|
|
#define
|
_EMU_IEN_VMONALTAVDDFALL_SHIFT
2
|
|
#define
|
_EMU_IEN_VMONALTAVDDRISE_DEFAULT
0x00000000UL
|
|
#define
|
_EMU_IEN_VMONALTAVDDRISE_MASK
0x8UL
|
|
#define
|
_EMU_IEN_VMONALTAVDDRISE_SHIFT
3
|
|
#define
|
_EMU_IEN_VMONAVDDFALL_DEFAULT
0x00000000UL
|
|
#define
|
_EMU_IEN_VMONAVDDFALL_MASK
0x1UL
|
|
#define
|
_EMU_IEN_VMONAVDDFALL_SHIFT
0
|
|
#define
|
_EMU_IEN_VMONAVDDRISE_DEFAULT
0x00000000UL
|
|
#define
|
_EMU_IEN_VMONAVDDRISE_MASK
0x2UL
|
|
#define
|
_EMU_IEN_VMONAVDDRISE_SHIFT
1
|
|
#define
|
_EMU_IEN_VMONDVDDFALL_DEFAULT
0x00000000UL
|
|
#define
|
_EMU_IEN_VMONDVDDFALL_MASK
0x10UL
|
|
#define
|
_EMU_IEN_VMONDVDDFALL_SHIFT
4
|
|
#define
|
_EMU_IEN_VMONDVDDRISE_DEFAULT
0x00000000UL
|
|
#define
|
_EMU_IEN_VMONDVDDRISE_MASK
0x20UL
|
|
#define
|
_EMU_IEN_VMONDVDDRISE_SHIFT
5
|
|
#define
|
_EMU_IEN_VMONFVDDFALL_DEFAULT
0x00000000UL
|
|
#define
|
_EMU_IEN_VMONFVDDFALL_MASK
0x4000UL
|
|
#define
|
_EMU_IEN_VMONFVDDFALL_SHIFT
14
|
|
#define
|
_EMU_IEN_VMONFVDDRISE_DEFAULT
0x00000000UL
|
|
#define
|
_EMU_IEN_VMONFVDDRISE_MASK
0x8000UL
|
|
#define
|
_EMU_IEN_VMONFVDDRISE_SHIFT
15
|
|
#define
|
_EMU_IEN_VMONIO0FALL_DEFAULT
0x00000000UL
|
|
#define
|
_EMU_IEN_VMONIO0FALL_MASK
0x40UL
|
|
#define
|
_EMU_IEN_VMONIO0FALL_SHIFT
6
|
|
#define
|
_EMU_IEN_VMONIO0RISE_DEFAULT
0x00000000UL
|
|
#define
|
_EMU_IEN_VMONIO0RISE_MASK
0x80UL
|
|
#define
|
_EMU_IEN_VMONIO0RISE_SHIFT
7
|
|
#define
|
_EMU_IEN_VSCALEDONE_DEFAULT
0x00000000UL
|
|
#define
|
_EMU_IEN_VSCALEDONE_MASK
0x2000000UL
|
|
#define
|
_EMU_IEN_VSCALEDONE_SHIFT
25
|
|
#define
|
_EMU_IF_DCDCINBYPASS_DEFAULT
0x00000000UL
|
|
#define
|
_EMU_IF_DCDCINBYPASS_MASK
0x100000UL
|
|
#define
|
_EMU_IF_DCDCINBYPASS_SHIFT
20
|
|
#define
|
_EMU_IF_DCDCLNRUNNING_DEFAULT
0x00000000UL
|
|
#define
|
_EMU_IF_DCDCLNRUNNING_MASK
0x80000UL
|
|
#define
|
_EMU_IF_DCDCLNRUNNING_SHIFT
19
|
|
#define
|
_EMU_IF_DCDCLPRUNNING_DEFAULT
0x00000000UL
|
|
#define
|
_EMU_IF_DCDCLPRUNNING_MASK
0x40000UL
|
|
#define
|
_EMU_IF_DCDCLPRUNNING_SHIFT
18
|
|
#define
|
_EMU_IF_EM23WAKEUP_DEFAULT
0x00000000UL
|
|
#define
|
_EMU_IF_EM23WAKEUP_MASK
0x1000000UL
|
|
#define
|
_EMU_IF_EM23WAKEUP_SHIFT
24
|
|
#define
|
_EMU_IF_MASK
0xE31FC0FFUL
|
|
#define
|
_EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT
0x00000000UL
|
|
#define
|
_EMU_IF_NFETOVERCURRENTLIMIT_MASK
0x20000UL
|
|
#define
|
_EMU_IF_NFETOVERCURRENTLIMIT_SHIFT
17
|
|
#define
|
_EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT
0x00000000UL
|
|
#define
|
_EMU_IF_PFETOVERCURRENTLIMIT_MASK
0x10000UL
|
|
#define
|
_EMU_IF_PFETOVERCURRENTLIMIT_SHIFT
16
|
|
#define
|
_EMU_IF_RESETVALUE
0x00000000UL
|
|
#define
|
_EMU_IF_TEMP_DEFAULT
0x00000000UL
|
|
#define
|
_EMU_IF_TEMP_MASK
0x20000000UL
|
|
#define
|
_EMU_IF_TEMP_SHIFT
29
|
|
#define
|
_EMU_IF_TEMPHIGH_DEFAULT
0x00000000UL
|
|
#define
|
_EMU_IF_TEMPHIGH_MASK
0x80000000UL
|
|
#define
|
_EMU_IF_TEMPHIGH_SHIFT
31
|
|
#define
|
_EMU_IF_TEMPLOW_DEFAULT
0x00000000UL
|
|
#define
|
_EMU_IF_TEMPLOW_MASK
0x40000000UL
|
|
#define
|
_EMU_IF_TEMPLOW_SHIFT
30
|
|
#define
|
_EMU_IF_VMONALTAVDDFALL_DEFAULT
0x00000000UL
|
|
#define
|
_EMU_IF_VMONALTAVDDFALL_MASK
0x4UL
|
|
#define
|
_EMU_IF_VMONALTAVDDFALL_SHIFT
2
|
|
#define
|
_EMU_IF_VMONALTAVDDRISE_DEFAULT
0x00000000UL
|
|
#define
|
_EMU_IF_VMONALTAVDDRISE_MASK
0x8UL
|
|
#define
|
_EMU_IF_VMONALTAVDDRISE_SHIFT
3
|
|
#define
|
_EMU_IF_VMONAVDDFALL_DEFAULT
0x00000000UL
|
|
#define
|
_EMU_IF_VMONAVDDFALL_MASK
0x1UL
|
|
#define
|
_EMU_IF_VMONAVDDFALL_SHIFT
0
|
|
#define
|
_EMU_IF_VMONAVDDRISE_DEFAULT
0x00000000UL
|
|
#define
|
_EMU_IF_VMONAVDDRISE_MASK
0x2UL
|
|
#define
|
_EMU_IF_VMONAVDDRISE_SHIFT
1
|
|
#define
|
_EMU_IF_VMONDVDDFALL_DEFAULT
0x00000000UL
|
|
#define
|
_EMU_IF_VMONDVDDFALL_MASK
0x10UL
|
|
#define
|
_EMU_IF_VMONDVDDFALL_SHIFT
4
|
|
#define
|
_EMU_IF_VMONDVDDRISE_DEFAULT
0x00000000UL
|
|
#define
|
_EMU_IF_VMONDVDDRISE_MASK
0x20UL
|
|
#define
|
_EMU_IF_VMONDVDDRISE_SHIFT
5
|
|
#define
|
_EMU_IF_VMONFVDDFALL_DEFAULT
0x00000000UL
|
|
#define
|
_EMU_IF_VMONFVDDFALL_MASK
0x4000UL
|
|
#define
|
_EMU_IF_VMONFVDDFALL_SHIFT
14
|
|
#define
|
_EMU_IF_VMONFVDDRISE_DEFAULT
0x00000000UL
|
|
#define
|
_EMU_IF_VMONFVDDRISE_MASK
0x8000UL
|
|
#define
|
_EMU_IF_VMONFVDDRISE_SHIFT
15
|
|
#define
|
_EMU_IF_VMONIO0FALL_DEFAULT
0x00000000UL
|
|
#define
|
_EMU_IF_VMONIO0FALL_MASK
0x40UL
|
|
#define
|
_EMU_IF_VMONIO0FALL_SHIFT
6
|
|
#define
|
_EMU_IF_VMONIO0RISE_DEFAULT
0x00000000UL
|
|
#define
|
_EMU_IF_VMONIO0RISE_MASK
0x80UL
|
|
#define
|
_EMU_IF_VMONIO0RISE_SHIFT
7
|