EMU Bit FieldsDevices > EMU

Macros

#define _EMU_CMD_EM01VSCALE0_DEFAULT   0x00000000UL
 
#define _EMU_CMD_EM01VSCALE0_MASK   0x10UL
 
#define _EMU_CMD_EM01VSCALE0_SHIFT   4
 
#define _EMU_CMD_EM01VSCALE2_DEFAULT   0x00000000UL
 
#define _EMU_CMD_EM01VSCALE2_MASK   0x40UL
 
#define _EMU_CMD_EM01VSCALE2_SHIFT   6
 
#define _EMU_CMD_EM4UNLATCH_DEFAULT   0x00000000UL
 
#define _EMU_CMD_EM4UNLATCH_MASK   0x1UL
 
#define _EMU_CMD_EM4UNLATCH_SHIFT   0
 
#define _EMU_CMD_MASK   0x00000051UL
 
#define _EMU_CMD_RESETVALUE   0x00000000UL
 
#define _EMU_CTRL_EM01LD_DEFAULT   0x00000000UL
 
#define _EMU_CTRL_EM01LD_MASK   0x8UL
 
#define _EMU_CTRL_EM01LD_SHIFT   3
 
#define _EMU_CTRL_EM23VSCALE_DEFAULT   0x00000000UL
 
#define _EMU_CTRL_EM23VSCALE_MASK   0x300UL
 
#define _EMU_CTRL_EM23VSCALE_RESV   0x00000003UL
 
#define _EMU_CTRL_EM23VSCALE_SHIFT   8
 
#define _EMU_CTRL_EM23VSCALE_VSCALE0   0x00000002UL
 
#define _EMU_CTRL_EM23VSCALE_VSCALE2   0x00000000UL
 
#define _EMU_CTRL_EM23VSCALEAUTOWSEN_DEFAULT   0x00000000UL
 
#define _EMU_CTRL_EM23VSCALEAUTOWSEN_MASK   0x10UL
 
#define _EMU_CTRL_EM23VSCALEAUTOWSEN_SHIFT   4
 
#define _EMU_CTRL_EM2BLOCK_DEFAULT   0x00000000UL
 
#define _EMU_CTRL_EM2BLOCK_MASK   0x2UL
 
#define _EMU_CTRL_EM2BLOCK_SHIFT   1
 
#define _EMU_CTRL_EM2BODDIS_DEFAULT   0x00000000UL
 
#define _EMU_CTRL_EM2BODDIS_MASK   0x4UL
 
#define _EMU_CTRL_EM2BODDIS_SHIFT   2
 
#define _EMU_CTRL_EM4HVSCALE_DEFAULT   0x00000000UL
 
#define _EMU_CTRL_EM4HVSCALE_MASK   0x30000UL
 
#define _EMU_CTRL_EM4HVSCALE_RESV   0x00000003UL
 
#define _EMU_CTRL_EM4HVSCALE_SHIFT   16
 
#define _EMU_CTRL_EM4HVSCALE_VSCALE0   0x00000002UL
 
#define _EMU_CTRL_EM4HVSCALE_VSCALE2   0x00000000UL
 
#define _EMU_CTRL_MASK   0x0003031EUL
 
#define _EMU_CTRL_RESETVALUE   0x00000000UL
 
#define _EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT   0x00000000UL
 
#define _EMU_DCDCCLIMCTRL_BYPLIMEN_MASK   0x2000UL
 
#define _EMU_DCDCCLIMCTRL_BYPLIMEN_SHIFT   13
 
#define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT   0x00000001UL
 
#define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_MASK   0x300UL
 
#define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_SHIFT   8
 
#define _EMU_DCDCCLIMCTRL_MASK   0x00002300UL
 
#define _EMU_DCDCCLIMCTRL_RESETVALUE   0x00000100UL
 
#define _EMU_DCDCCTRL_DCDCMODE_BYPASS   0x00000000UL
 
#define _EMU_DCDCCTRL_DCDCMODE_DEFAULT   0x00000003UL
 
#define _EMU_DCDCCTRL_DCDCMODE_LOWNOISE   0x00000001UL
 
#define _EMU_DCDCCTRL_DCDCMODE_LOWPOWER   0x00000002UL
 
#define _EMU_DCDCCTRL_DCDCMODE_MASK   0x3UL
 
#define _EMU_DCDCCTRL_DCDCMODE_OFF   0x00000003UL
 
#define _EMU_DCDCCTRL_DCDCMODE_SHIFT   0
 
#define _EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT   0x00000001UL
 
#define _EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER   0x00000001UL
 
#define _EMU_DCDCCTRL_DCDCMODEEM23_EM23SW   0x00000000UL
 
#define _EMU_DCDCCTRL_DCDCMODEEM23_MASK   0x10UL
 
#define _EMU_DCDCCTRL_DCDCMODEEM23_SHIFT   4
 
#define _EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT   0x00000001UL
 
#define _EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER   0x00000001UL
 
#define _EMU_DCDCCTRL_DCDCMODEEM4_EM4SW   0x00000000UL
 
#define _EMU_DCDCCTRL_DCDCMODEEM4_MASK   0x20UL
 
#define _EMU_DCDCCTRL_DCDCMODEEM4_SHIFT   5
 
#define _EMU_DCDCCTRL_MASK   0x00000033UL
 
#define _EMU_DCDCCTRL_RESETVALUE   0x00000033UL
 
#define _EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT   0x00000002UL
 
#define _EMU_DCDCLNCOMPCTRL_COMPENC1_MASK   0x300000UL
 
#define _EMU_DCDCLNCOMPCTRL_COMPENC1_SHIFT   20
 
#define _EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT   0x00000007UL
 
#define _EMU_DCDCLNCOMPCTRL_COMPENC2_MASK   0x7000000UL
 
#define _EMU_DCDCLNCOMPCTRL_COMPENC2_SHIFT   24
 
#define _EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT   0x00000005UL
 
#define _EMU_DCDCLNCOMPCTRL_COMPENC3_MASK   0xF0000000UL
 
#define _EMU_DCDCLNCOMPCTRL_COMPENC3_SHIFT   28
 
#define _EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT   0x00000007UL
 
#define _EMU_DCDCLNCOMPCTRL_COMPENR1_MASK   0x7UL
 
#define _EMU_DCDCLNCOMPCTRL_COMPENR1_SHIFT   0
 
#define _EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT   0x00000007UL
 
#define _EMU_DCDCLNCOMPCTRL_COMPENR2_MASK   0x1F0UL
 
#define _EMU_DCDCLNCOMPCTRL_COMPENR2_SHIFT   4
 
#define _EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT   0x00000004UL
 
#define _EMU_DCDCLNCOMPCTRL_COMPENR3_MASK   0xF000UL
 
#define _EMU_DCDCLNCOMPCTRL_COMPENR3_SHIFT   12
 
#define _EMU_DCDCLNCOMPCTRL_MASK   0xF730F1F7UL
 
#define _EMU_DCDCLNCOMPCTRL_RESETVALUE   0x57204077UL
 
#define _EMU_DCDCLNFREQCTRL_MASK   0x1F000007UL
 
#define _EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT   0x00000000UL
 
#define _EMU_DCDCLNFREQCTRL_RCOBAND_MASK   0x7UL
 
#define _EMU_DCDCLNFREQCTRL_RCOBAND_SHIFT   0
 
#define _EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT   0x00000010UL
 
#define _EMU_DCDCLNFREQCTRL_RCOTRIM_MASK   0x1F000000UL
 
#define _EMU_DCDCLNFREQCTRL_RCOTRIM_SHIFT   24
 
#define _EMU_DCDCLNFREQCTRL_RESETVALUE   0x10000000UL
 
#define _EMU_DCDCLNVCTRL_LNATT_DEFAULT   0x00000000UL
 
#define _EMU_DCDCLNVCTRL_LNATT_DIV3   0x00000000UL
 
#define _EMU_DCDCLNVCTRL_LNATT_DIV6   0x00000001UL
 
#define _EMU_DCDCLNVCTRL_LNATT_MASK   0x2UL
 
#define _EMU_DCDCLNVCTRL_LNATT_SHIFT   1
 
#define _EMU_DCDCLNVCTRL_LNVREF_DEFAULT   0x00000071UL
 
#define _EMU_DCDCLNVCTRL_LNVREF_MASK   0x7F00UL
 
#define _EMU_DCDCLNVCTRL_LNVREF_SHIFT   8
 
#define _EMU_DCDCLNVCTRL_MASK   0x00007F02UL
 
#define _EMU_DCDCLNVCTRL_RESETVALUE   0x00007100UL
 
#define _EMU_DCDCLPCTRL_LPBLANK_DEFAULT   0x00000001UL
 
#define _EMU_DCDCLPCTRL_LPBLANK_MASK   0x6000000UL
 
#define _EMU_DCDCLPCTRL_LPBLANK_SHIFT   25
 
#define _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_DEFAULT   0x00000000UL
 
#define _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_MASK   0xF000UL
 
#define _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_SHIFT   12
 
#define _EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT   0x00000001UL
 
#define _EMU_DCDCLPCTRL_LPVREFDUTYEN_MASK   0x1000000UL
 
#define _EMU_DCDCLPCTRL_LPVREFDUTYEN_SHIFT   24
 
#define _EMU_DCDCLPCTRL_MASK   0x0700F000UL
 
#define _EMU_DCDCLPCTRL_RESETVALUE   0x03000000UL
 
#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS0   0x00000000UL
 
#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS1   0x00000001UL
 
#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS2   0x00000002UL
 
#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3   0x00000003UL
 
#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_DEFAULT   0x00000003UL
 
#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK   0x300UL
 
#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_SHIFT   8
 
#define _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_DEFAULT   0x00000000UL
 
#define _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_MASK   0xF000UL
 
#define _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_SHIFT   12
 
#define _EMU_DCDCLPEM01CFG_MASK   0x0000F300UL
 
#define _EMU_DCDCLPEM01CFG_RESETVALUE   0x00000300UL
 
#define _EMU_DCDCLPVCTRL_LPATT_DEFAULT   0x00000000UL
 
#define _EMU_DCDCLPVCTRL_LPATT_DIV4   0x00000000UL
 
#define _EMU_DCDCLPVCTRL_LPATT_DIV8   0x00000001UL
 
#define _EMU_DCDCLPVCTRL_LPATT_MASK   0x1UL
 
#define _EMU_DCDCLPVCTRL_LPATT_SHIFT   0
 
#define _EMU_DCDCLPVCTRL_LPVREF_DEFAULT   0x000000B4UL
 
#define _EMU_DCDCLPVCTRL_LPVREF_MASK   0x1FEUL
 
#define _EMU_DCDCLPVCTRL_LPVREF_SHIFT   1
 
#define _EMU_DCDCLPVCTRL_MASK   0x000001FFUL
 
#define _EMU_DCDCLPVCTRL_RESETVALUE   0x00000168UL
 
#define _EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT   0x00000000UL
 
#define _EMU_DCDCMISCCTRL_BYPLIMSEL_MASK   0xF0000UL
 
#define _EMU_DCDCMISCCTRL_BYPLIMSEL_SHIFT   16
 
#define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT   0x00000003UL
 
#define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_MASK   0x7000000UL
 
#define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_SHIFT   24
 
#define _EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT   0x00000000UL
 
#define _EMU_DCDCMISCCTRL_LNFORCECCM_MASK   0x1UL
 
#define _EMU_DCDCMISCCTRL_LNFORCECCM_SHIFT   0
 
#define _EMU_DCDCMISCCTRL_LNFORCECCMIMM_DEFAULT   0x00000000UL
 
#define _EMU_DCDCMISCCTRL_LNFORCECCMIMM_MASK   0x20UL
 
#define _EMU_DCDCMISCCTRL_LNFORCECCMIMM_SHIFT   5
 
#define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT   0x00000001UL
 
#define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_MASK   0x700000UL
 
#define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_SHIFT   20
 
#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS0   0x00000000UL
 
#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS1   0x00000001UL
 
#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS2   0x00000002UL
 
#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS3   0x00000003UL
 
#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_DEFAULT   0x00000000UL
 
#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_MASK   0x30000000UL
 
#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_SHIFT   28
 
#define _EMU_DCDCMISCCTRL_LPCMPHYSDIS_DEFAULT   0x00000001UL
 
#define _EMU_DCDCMISCCTRL_LPCMPHYSDIS_MASK   0x2UL
 
#define _EMU_DCDCMISCCTRL_LPCMPHYSDIS_SHIFT   1
 
#define _EMU_DCDCMISCCTRL_LPCMPHYSHI_DEFAULT   0x00000001UL
 
#define _EMU_DCDCMISCCTRL_LPCMPHYSHI_MASK   0x4UL
 
#define _EMU_DCDCMISCCTRL_LPCMPHYSHI_SHIFT   2
 
#define _EMU_DCDCMISCCTRL_MASK   0x377FFF27UL
 
#define _EMU_DCDCMISCCTRL_NFETCNT_DEFAULT   0x00000007UL
 
#define _EMU_DCDCMISCCTRL_NFETCNT_MASK   0xF000UL
 
#define _EMU_DCDCMISCCTRL_NFETCNT_SHIFT   12
 
#define _EMU_DCDCMISCCTRL_PFETCNT_DEFAULT   0x00000007UL
 
#define _EMU_DCDCMISCCTRL_PFETCNT_MASK   0xF00UL
 
#define _EMU_DCDCMISCCTRL_PFETCNT_SHIFT   8
 
#define _EMU_DCDCMISCCTRL_RESETVALUE   0x03107706UL
 
#define _EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT   0x00000000UL
 
#define _EMU_DCDCSYNC_DCDCCTRLBUSY_MASK   0x1UL
 
#define _EMU_DCDCSYNC_DCDCCTRLBUSY_SHIFT   0
 
#define _EMU_DCDCSYNC_MASK   0x00000001UL
 
#define _EMU_DCDCSYNC_RESETVALUE   0x00000000UL
 
#define _EMU_DCDCZDETCTRL_MASK   0x00000370UL
 
#define _EMU_DCDCZDETCTRL_RESETVALUE   0x00000150UL
 
#define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT   0x00000001UL
 
#define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_MASK   0x300UL
 
#define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_SHIFT   8
 
#define _EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT   0x00000005UL
 
#define _EMU_DCDCZDETCTRL_ZDETILIMSEL_MASK   0x70UL
 
#define _EMU_DCDCZDETCTRL_ZDETILIMSEL_SHIFT   4
 
#define _EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_DEFAULT   0x00000000UL
 
#define _EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_MASK   0x1UL
 
#define _EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_SHIFT   0
 
#define _EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_DEFAULT   0x00000000UL
 
#define _EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_MASK   0x2UL
 
#define _EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_SHIFT   1
 
#define _EMU_EM23PERNORETAINCMD_ADC0UNLOCK_DEFAULT   0x00000000UL
 
#define _EMU_EM23PERNORETAINCMD_ADC0UNLOCK_MASK   0x200UL
 
#define _EMU_EM23PERNORETAINCMD_ADC0UNLOCK_SHIFT   9
 
#define _EMU_EM23PERNORETAINCMD_DAC0UNLOCK_DEFAULT   0x00000000UL
 
#define _EMU_EM23PERNORETAINCMD_DAC0UNLOCK_MASK   0x80UL
 
#define _EMU_EM23PERNORETAINCMD_DAC0UNLOCK_SHIFT   7
 
#define _EMU_EM23PERNORETAINCMD_I2C0UNLOCK_DEFAULT   0x00000000UL
 
#define _EMU_EM23PERNORETAINCMD_I2C0UNLOCK_MASK   0x20UL
 
#define _EMU_EM23PERNORETAINCMD_I2C0UNLOCK_SHIFT   5
 
#define _EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_DEFAULT   0x00000000UL
 
#define _EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_MASK   0x100UL
 
#define _EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_SHIFT   8
 
#define _EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_DEFAULT   0x00000000UL
 
#define _EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_MASK   0x2000UL
 
#define _EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_SHIFT   13
 
#define _EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_DEFAULT   0x00000000UL
 
#define _EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_MASK   0x400UL
 
#define _EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_SHIFT   10
 
#define _EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_DEFAULT   0x00000000UL
 
#define _EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_MASK   0x8000UL
 
#define _EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_SHIFT   15
 
#define _EMU_EM23PERNORETAINCMD_MASK   0x0000BFA7UL
 
#define _EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_DEFAULT   0x00000000UL
 
#define _EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_MASK   0x4UL
 
#define _EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_SHIFT   2
 
#define _EMU_EM23PERNORETAINCMD_RESETVALUE   0x00000000UL
 
#define _EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_DEFAULT   0x00000000UL
 
#define _EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_MASK   0x800UL
 
#define _EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_SHIFT   11
 
#define _EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_DEFAULT   0x00000000UL
 
#define _EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_MASK   0x1000UL
 
#define _EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_SHIFT   12
 
#define _EMU_EM23PERNORETAINCTRL_ACMP0DIS_DEFAULT   0x00000000UL
 
#define _EMU_EM23PERNORETAINCTRL_ACMP0DIS_MASK   0x1UL
 
#define _EMU_EM23PERNORETAINCTRL_ACMP0DIS_SHIFT   0
 
#define _EMU_EM23PERNORETAINCTRL_ACMP1DIS_DEFAULT   0x00000000UL
 
#define _EMU_EM23PERNORETAINCTRL_ACMP1DIS_MASK   0x2UL
 
#define _EMU_EM23PERNORETAINCTRL_ACMP1DIS_SHIFT   1
 
#define _EMU_EM23PERNORETAINCTRL_ADC0DIS_DEFAULT   0x00000000UL
 
#define _EMU_EM23PERNORETAINCTRL_ADC0DIS_MASK   0x200UL
 
#define _EMU_EM23PERNORETAINCTRL_ADC0DIS_SHIFT   9
 
#define _EMU_EM23PERNORETAINCTRL_DAC0DIS_DEFAULT   0x00000000UL
 
#define _EMU_EM23PERNORETAINCTRL_DAC0DIS_MASK   0x80UL
 
#define _EMU_EM23PERNORETAINCTRL_DAC0DIS_SHIFT   7
 
#define _EMU_EM23PERNORETAINCTRL_I2C0DIS_DEFAULT   0x00000000UL
 
#define _EMU_EM23PERNORETAINCTRL_I2C0DIS_MASK   0x20UL
 
#define _EMU_EM23PERNORETAINCTRL_I2C0DIS_SHIFT   5
 
#define _EMU_EM23PERNORETAINCTRL_IDAC0DIS_DEFAULT   0x00000000UL
 
#define _EMU_EM23PERNORETAINCTRL_IDAC0DIS_MASK   0x100UL
 
#define _EMU_EM23PERNORETAINCTRL_IDAC0DIS_SHIFT   8
 
#define _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_DEFAULT   0x00000000UL
 
#define _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_MASK   0x2000UL
 
#define _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_SHIFT   13
 
#define _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_DEFAULT   0x00000000UL
 
#define _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_MASK   0x400UL
 
#define _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_SHIFT   10
 
#define _EMU_EM23PERNORETAINCTRL_LEUART0DIS_DEFAULT   0x00000000UL
 
#define _EMU_EM23PERNORETAINCTRL_LEUART0DIS_MASK   0x8000UL
 
#define _EMU_EM23PERNORETAINCTRL_LEUART0DIS_SHIFT   15
 
#define _EMU_EM23PERNORETAINCTRL_MASK   0x0000BFA7UL
 
#define _EMU_EM23PERNORETAINCTRL_PCNT0DIS_DEFAULT   0x00000000UL
 
#define _EMU_EM23PERNORETAINCTRL_PCNT0DIS_MASK   0x4UL
 
#define _EMU_EM23PERNORETAINCTRL_PCNT0DIS_SHIFT   2
 
#define _EMU_EM23PERNORETAINCTRL_RESETVALUE   0x00000000UL
 
#define _EMU_EM23PERNORETAINCTRL_WDOG0DIS_DEFAULT   0x00000000UL
 
#define _EMU_EM23PERNORETAINCTRL_WDOG0DIS_MASK   0x800UL
 
#define _EMU_EM23PERNORETAINCTRL_WDOG0DIS_SHIFT   11
 
#define _EMU_EM23PERNORETAINCTRL_WDOG1DIS_DEFAULT   0x00000000UL
 
#define _EMU_EM23PERNORETAINCTRL_WDOG1DIS_MASK   0x1000UL
 
#define _EMU_EM23PERNORETAINCTRL_WDOG1DIS_SHIFT   12
 
#define _EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_DEFAULT   0x00000000UL
 
#define _EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_MASK   0x1UL
 
#define _EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_SHIFT   0
 
#define _EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_DEFAULT   0x00000000UL
 
#define _EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_MASK   0x2UL
 
#define _EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_SHIFT   1
 
#define _EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_DEFAULT   0x00000000UL
 
#define _EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_MASK   0x200UL
 
#define _EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_SHIFT   9
 
#define _EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_DEFAULT   0x00000000UL
 
#define _EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_MASK   0x80UL
 
#define _EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_SHIFT   7
 
#define _EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_DEFAULT   0x00000000UL
 
#define _EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_MASK   0x20UL
 
#define _EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_SHIFT   5
 
#define _EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_DEFAULT   0x00000000UL
 
#define _EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_MASK   0x100UL
 
#define _EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_SHIFT   8
 
#define _EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_DEFAULT   0x00000000UL
 
#define _EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_MASK   0x2000UL
 
#define _EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_SHIFT   13
 
#define _EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_DEFAULT   0x00000000UL
 
#define _EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_MASK   0x400UL
 
#define _EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_SHIFT   10
 
#define _EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_DEFAULT   0x00000000UL
 
#define _EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_MASK   0x8000UL
 
#define _EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_SHIFT   15
 
#define _EMU_EM23PERNORETAINSTATUS_MASK   0x0000BFA7UL
 
#define _EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_DEFAULT   0x00000000UL
 
#define _EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_MASK   0x4UL
 
#define _EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_SHIFT   2
 
#define _EMU_EM23PERNORETAINSTATUS_RESETVALUE   0x00000000UL
 
#define _EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_DEFAULT   0x00000000UL
 
#define _EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_MASK   0x800UL
 
#define _EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_SHIFT   11
 
#define _EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_DEFAULT   0x00000000UL
 
#define _EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_MASK   0x1000UL
 
#define _EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_SHIFT   12
 
#define _EMU_EM4CTRL_EM4ENTRY_DEFAULT   0x00000000UL
 
#define _EMU_EM4CTRL_EM4ENTRY_MASK   0x30000UL
 
#define _EMU_EM4CTRL_EM4ENTRY_SHIFT   16
 
#define _EMU_EM4CTRL_EM4IORETMODE_DEFAULT   0x00000000UL
 
#define _EMU_EM4CTRL_EM4IORETMODE_DISABLE   0x00000000UL
 
#define _EMU_EM4CTRL_EM4IORETMODE_EM4EXIT   0x00000001UL
 
#define _EMU_EM4CTRL_EM4IORETMODE_MASK   0x30UL
 
#define _EMU_EM4CTRL_EM4IORETMODE_SHIFT   4
 
#define _EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH   0x00000002UL
 
#define _EMU_EM4CTRL_EM4STATE_DEFAULT   0x00000000UL
 
#define _EMU_EM4CTRL_EM4STATE_EM4H   0x00000001UL
 
#define _EMU_EM4CTRL_EM4STATE_EM4S   0x00000000UL
 
#define _EMU_EM4CTRL_EM4STATE_MASK   0x1UL
 
#define _EMU_EM4CTRL_EM4STATE_SHIFT   0
 
#define _EMU_EM4CTRL_MASK   0x0003003FUL
 
#define _EMU_EM4CTRL_RESETVALUE   0x00000000UL
 
#define _EMU_EM4CTRL_RETAINLFRCO_DEFAULT   0x00000000UL
 
#define _EMU_EM4CTRL_RETAINLFRCO_MASK   0x2UL
 
#define _EMU_EM4CTRL_RETAINLFRCO_SHIFT   1
 
#define _EMU_EM4CTRL_RETAINLFXO_DEFAULT   0x00000000UL
 
#define _EMU_EM4CTRL_RETAINLFXO_MASK   0x4UL
 
#define _EMU_EM4CTRL_RETAINLFXO_SHIFT   2
 
#define _EMU_EM4CTRL_RETAINULFRCO_DEFAULT   0x00000000UL
 
#define _EMU_EM4CTRL_RETAINULFRCO_MASK   0x8UL
 
#define _EMU_EM4CTRL_RETAINULFRCO_SHIFT   3
 
#define _EMU_IEN_DCDCINBYPASS_DEFAULT   0x00000000UL
 
#define _EMU_IEN_DCDCINBYPASS_MASK   0x100000UL
 
#define _EMU_IEN_DCDCINBYPASS_SHIFT   20
 
#define _EMU_IEN_DCDCLNRUNNING_DEFAULT   0x00000000UL
 
#define _EMU_IEN_DCDCLNRUNNING_MASK   0x80000UL
 
#define _EMU_IEN_DCDCLNRUNNING_SHIFT   19
 
#define _EMU_IEN_DCDCLPRUNNING_DEFAULT   0x00000000UL
 
#define _EMU_IEN_DCDCLPRUNNING_MASK   0x40000UL
 
#define _EMU_IEN_DCDCLPRUNNING_SHIFT   18
 
#define _EMU_IEN_EM23WAKEUP_DEFAULT   0x00000000UL
 
#define _EMU_IEN_EM23WAKEUP_MASK   0x1000000UL
 
#define _EMU_IEN_EM23WAKEUP_SHIFT   24
 
#define _EMU_IEN_MASK   0xE31FC0FFUL
 
#define _EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT   0x00000000UL
 
#define _EMU_IEN_NFETOVERCURRENTLIMIT_MASK   0x20000UL
 
#define _EMU_IEN_NFETOVERCURRENTLIMIT_SHIFT   17
 
#define _EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT   0x00000000UL
 
#define _EMU_IEN_PFETOVERCURRENTLIMIT_MASK   0x10000UL
 
#define _EMU_IEN_PFETOVERCURRENTLIMIT_SHIFT   16
 
#define _EMU_IEN_RESETVALUE   0x00000000UL
 
#define _EMU_IEN_TEMP_DEFAULT   0x00000000UL
 
#define _EMU_IEN_TEMP_MASK   0x20000000UL
 
#define _EMU_IEN_TEMP_SHIFT   29
 
#define _EMU_IEN_TEMPHIGH_DEFAULT   0x00000000UL
 
#define _EMU_IEN_TEMPHIGH_MASK   0x80000000UL
 
#define _EMU_IEN_TEMPHIGH_SHIFT   31
 
#define _EMU_IEN_TEMPLOW_DEFAULT   0x00000000UL
 
#define _EMU_IEN_TEMPLOW_MASK   0x40000000UL
 
#define _EMU_IEN_TEMPLOW_SHIFT   30
 
#define _EMU_IEN_VMONALTAVDDFALL_DEFAULT   0x00000000UL
 
#define _EMU_IEN_VMONALTAVDDFALL_MASK   0x4UL
 
#define _EMU_IEN_VMONALTAVDDFALL_SHIFT   2
 
#define _EMU_IEN_VMONALTAVDDRISE_DEFAULT   0x00000000UL
 
#define _EMU_IEN_VMONALTAVDDRISE_MASK   0x8UL
 
#define _EMU_IEN_VMONALTAVDDRISE_SHIFT   3
 
#define _EMU_IEN_VMONAVDDFALL_DEFAULT   0x00000000UL
 
#define _EMU_IEN_VMONAVDDFALL_MASK   0x1UL
 
#define _EMU_IEN_VMONAVDDFALL_SHIFT   0
 
#define _EMU_IEN_VMONAVDDRISE_DEFAULT   0x00000000UL
 
#define _EMU_IEN_VMONAVDDRISE_MASK   0x2UL
 
#define _EMU_IEN_VMONAVDDRISE_SHIFT   1
 
#define _EMU_IEN_VMONDVDDFALL_DEFAULT   0x00000000UL
 
#define _EMU_IEN_VMONDVDDFALL_MASK   0x10UL
 
#define _EMU_IEN_VMONDVDDFALL_SHIFT   4
 
#define _EMU_IEN_VMONDVDDRISE_DEFAULT   0x00000000UL
 
#define _EMU_IEN_VMONDVDDRISE_MASK   0x20UL
 
#define _EMU_IEN_VMONDVDDRISE_SHIFT   5
 
#define _EMU_IEN_VMONFVDDFALL_DEFAULT   0x00000000UL
 
#define _EMU_IEN_VMONFVDDFALL_MASK   0x4000UL
 
#define _EMU_IEN_VMONFVDDFALL_SHIFT   14
 
#define _EMU_IEN_VMONFVDDRISE_DEFAULT   0x00000000UL
 
#define _EMU_IEN_VMONFVDDRISE_MASK   0x8000UL
 
#define _EMU_IEN_VMONFVDDRISE_SHIFT   15
 
#define _EMU_IEN_VMONIO0FALL_DEFAULT   0x00000000UL
 
#define _EMU_IEN_VMONIO0FALL_MASK   0x40UL
 
#define _EMU_IEN_VMONIO0FALL_SHIFT   6
 
#define _EMU_IEN_VMONIO0RISE_DEFAULT   0x00000000UL
 
#define _EMU_IEN_VMONIO0RISE_MASK   0x80UL
 
#define _EMU_IEN_VMONIO0RISE_SHIFT   7
 
#define _EMU_IEN_VSCALEDONE_DEFAULT   0x00000000UL
 
#define _EMU_IEN_VSCALEDONE_MASK   0x2000000UL
 
#define _EMU_IEN_VSCALEDONE_SHIFT   25
 
#define _EMU_IF_DCDCINBYPASS_DEFAULT   0x00000000UL
 
#define _EMU_IF_DCDCINBYPASS_MASK   0x100000UL
 
#define _EMU_IF_DCDCINBYPASS_SHIFT   20
 
#define _EMU_IF_DCDCLNRUNNING_DEFAULT   0x00000000UL
 
#define _EMU_IF_DCDCLNRUNNING_MASK   0x80000UL
 
#define _EMU_IF_DCDCLNRUNNING_SHIFT   19
 
#define _EMU_IF_DCDCLPRUNNING_DEFAULT   0x00000000UL
 
#define _EMU_IF_DCDCLPRUNNING_MASK   0x40000UL
 
#define _EMU_IF_DCDCLPRUNNING_SHIFT   18
 
#define _EMU_IF_EM23WAKEUP_DEFAULT   0x00000000UL
 
#define _EMU_IF_EM23WAKEUP_MASK   0x1000000UL
 
#define _EMU_IF_EM23WAKEUP_SHIFT   24
 
#define _EMU_IF_MASK   0xE31FC0FFUL
 
#define _EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT   0x00000000UL
 
#define _EMU_IF_NFETOVERCURRENTLIMIT_MASK   0x20000UL
 
#define _EMU_IF_NFETOVERCURRENTLIMIT_SHIFT   17
 
#define _EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT   0x00000000UL
 
#define _EMU_IF_PFETOVERCURRENTLIMIT_MASK   0x10000UL
 
#define _EMU_IF_PFETOVERCURRENTLIMIT_SHIFT   16
 
#define _EMU_IF_RESETVALUE   0x00000000UL
 
#define _EMU_IF_TEMP_DEFAULT   0x00000000UL
 
#define _EMU_IF_TEMP_MASK   0x20000000UL
 
#define _EMU_IF_TEMP_SHIFT   29
 
#define _EMU_IF_TEMPHIGH_DEFAULT   0x00000000UL
 
#define _EMU_IF_TEMPHIGH_MASK   0x80000000UL
 
#define _EMU_IF_TEMPHIGH_SHIFT   31
 
#define _EMU_IF_TEMPLOW_DEFAULT   0x00000000UL
 
#define _EMU_IF_TEMPLOW_MASK   0x40000000UL
 
#define _EMU_IF_TEMPLOW_SHIFT   30
 
#define _EMU_IF_VMONALTAVDDFALL_DEFAULT   0x00000000UL
 
#define _EMU_IF_VMONALTAVDDFALL_MASK   0x4UL
 
#define _EMU_IF_VMONALTAVDDFALL_SHIFT   2
 
#define _EMU_IF_VMONALTAVDDRISE_DEFAULT   0x00000000UL
 
#define _EMU_IF_VMONALTAVDDRISE_MASK   0x8UL
 
#define _EMU_IF_VMONALTAVDDRISE_SHIFT   3
 
#define _EMU_IF_VMONAVDDFALL_DEFAULT   0x00000000UL
 
#define _EMU_IF_VMONAVDDFALL_MASK   0x1UL
 
#define _EMU_IF_VMONAVDDFALL_SHIFT   0
 
#define _EMU_IF_VMONAVDDRISE_DEFAULT   0x00000000UL
 
#define _EMU_IF_VMONAVDDRISE_MASK   0x2UL
 
#define _EMU_IF_VMONAVDDRISE_SHIFT   1
 
#define _EMU_IF_VMONDVDDFALL_DEFAULT   0x00000000UL
 
#define _EMU_IF_VMONDVDDFALL_MASK   0x10UL
 
#define _EMU_IF_VMONDVDDFALL_SHIFT   4
 
#define _EMU_IF_VMONDVDDRISE_DEFAULT   0x00000000UL
 
#define _EMU_IF_VMONDVDDRISE_MASK   0x20UL
 
#define _EMU_IF_VMONDVDDRISE_SHIFT   5
 
#define _EMU_IF_VMONFVDDFALL_DEFAULT   0x00000000UL
 
#define _EMU_IF_VMONFVDDFALL_MASK   0x4000UL
 
#define _EMU_IF_VMONFVDDFALL_SHIFT   14
 
#define _EMU_IF_VMONFVDDRISE_DEFAULT   0x00000000UL
 
#define _EMU_IF_VMONFVDDRISE_MASK   0x8000UL
 
#define _EMU_IF_VMONFVDDRISE_SHIFT   15
 
#define _EMU_IF_VMONIO0FALL_DEFAULT   0x00000000UL
 
#define _EMU_IF_VMONIO0FALL_MASK   0x40UL
 
#define _EMU_IF_VMONIO0FALL_SHIFT   6
 
#define _EMU_IF_VMONIO0RISE_DEFAULT   0x00000000UL
 
#define _EMU_IF_VMONIO0RISE_MASK   0x80UL
 
#define _EMU_IF_VMONIO0RISE_SHIFT   7
 
#define _EMU_IF_VSCALEDONE_DEFAULT   0x00000000UL
 
#define _EMU_IF_VSCALEDONE_MASK   0x2000000UL
 
#define _EMU_IF_VSCALEDONE_SHIFT   25
 
#define _EMU_IFC_DCDCINBYPASS_DEFAULT   0x00000000UL
 
#define _EMU_IFC_DCDCINBYPASS_MASK   0x100000UL
 
#define _EMU_IFC_DCDCINBYPASS_SHIFT   20
 
#define _EMU_IFC_DCDCLNRUNNING_DEFAULT   0x00000000UL
 
#define _EMU_IFC_DCDCLNRUNNING_MASK   0x80000UL
 
#define _EMU_IFC_DCDCLNRUNNING_SHIFT   19
 
#define _EMU_IFC_DCDCLPRUNNING_DEFAULT   0x00000000UL
 
#define _EMU_IFC_DCDCLPRUNNING_MASK   0x40000UL
 
#define _EMU_IFC_DCDCLPRUNNING_SHIFT   18
 
#define _EMU_IFC_EM23WAKEUP_DEFAULT   0x00000000UL
 
#define _EMU_IFC_EM23WAKEUP_MASK   0x1000000UL
 
#define _EMU_IFC_EM23WAKEUP_SHIFT   24
 
#define _EMU_IFC_MASK   0xE31FC0FFUL
 
#define _EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT   0x00000000UL
 
#define _EMU_IFC_NFETOVERCURRENTLIMIT_MASK   0x20000UL
 
#define _EMU_IFC_NFETOVERCURRENTLIMIT_SHIFT   17
 
#define _EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT   0x00000000UL
 
#define _EMU_IFC_PFETOVERCURRENTLIMIT_MASK   0x10000UL
 
#define _EMU_IFC_PFETOVERCURRENTLIMIT_SHIFT   16
 
#define _EMU_IFC_RESETVALUE   0x00000000UL
 
#define _EMU_IFC_TEMP_DEFAULT   0x00000000UL
 
#define _EMU_IFC_TEMP_MASK   0x20000000UL
 
#define _EMU_IFC_TEMP_SHIFT   29
 
#define _EMU_IFC_TEMPHIGH_DEFAULT   0x00000000UL
 
#define _EMU_IFC_TEMPHIGH_MASK   0x80000000UL
 
#define _EMU_IFC_TEMPHIGH_SHIFT   31
 
#define _EMU_IFC_TEMPLOW_DEFAULT   0x00000000UL
 
#define _EMU_IFC_TEMPLOW_MASK   0x40000000UL
 
#define _EMU_IFC_TEMPLOW_SHIFT   30
 
#define _EMU_IFC_VMONALTAVDDFALL_DEFAULT   0x00000000UL
 
#define _EMU_IFC_VMONALTAVDDFALL_MASK   0x4UL
 
#define _EMU_IFC_VMONALTAVDDFALL_SHIFT   2
 
#define _EMU_IFC_VMONALTAVDDRISE_DEFAULT   0x00000000UL
 
#define _EMU_IFC_VMONALTAVDDRISE_MASK   0x8UL
 
#define _EMU_IFC_VMONALTAVDDRISE_SHIFT   3
 
#define _EMU_IFC_VMONAVDDFALL_DEFAULT   0x00000000UL
 
#define _EMU_IFC_VMONAVDDFALL_MASK   0x1UL
 
#define _EMU_IFC_VMONAVDDFALL_SHIFT   0
 
#define _EMU_IFC_VMONAVDDRISE_DEFAULT   0x00000000UL
 
#define _EMU_IFC_VMONAVDDRISE_MASK   0x2UL
 
#define _EMU_IFC_VMONAVDDRISE_SHIFT   1
 
#define _EMU_IFC_VMONDVDDFALL_DEFAULT   0x00000000UL
 
#define _EMU_IFC_VMONDVDDFALL_MASK   0x10UL
 
#define _EMU_IFC_VMONDVDDFALL_SHIFT   4
 
#define _EMU_IFC_VMONDVDDRISE_DEFAULT   0x00000000UL
 
#define _EMU_IFC_VMONDVDDRISE_MASK   0x20UL
 
#define _EMU_IFC_VMONDVDDRISE_SHIFT   5
 
#define _EMU_IFC_VMONFVDDFALL_DEFAULT   0x00000000UL
 
#define _EMU_IFC_VMONFVDDFALL_MASK   0x4000UL
 
#define _EMU_IFC_VMONFVDDFALL_SHIFT   14
 
#define _EMU_IFC_VMONFVDDRISE_DEFAULT   0x00000000UL
 
#define _EMU_IFC_VMONFVDDRISE_MASK   0x8000UL
 
#define _EMU_IFC_VMONFVDDRISE_SHIFT   15
 
#define _EMU_IFC_VMONIO0FALL_DEFAULT   0x00000000UL
 
#define _EMU_IFC_VMONIO0FALL_MASK   0x40UL
 
#define _EMU_IFC_VMONIO0FALL_SHIFT   6
 
#define _EMU_IFC_VMONIO0RISE_DEFAULT   0x00000000UL
 
#define _EMU_IFC_VMONIO0RISE_MASK   0x80UL
 
#define _EMU_IFC_VMONIO0RISE_SHIFT   7
 
#define _EMU_IFC_VSCALEDONE_DEFAULT   0x00000000UL
 
#define _EMU_IFC_VSCALEDONE_MASK   0x2000000UL
 
#define _EMU_IFC_VSCALEDONE_SHIFT   25
 
#define _EMU_IFS_DCDCINBYPASS_DEFAULT   0x00000000UL
 
#define _EMU_IFS_DCDCINBYPASS_MASK   0x100000UL
 
#define _EMU_IFS_DCDCINBYPASS_SHIFT   20
 
#define _EMU_IFS_DCDCLNRUNNING_DEFAULT   0x00000000UL
 
#define _EMU_IFS_DCDCLNRUNNING_MASK   0x80000UL
 
#define _EMU_IFS_DCDCLNRUNNING_SHIFT   19
 
#define _EMU_IFS_DCDCLPRUNNING_DEFAULT   0x00000000UL
 
#define _EMU_IFS_DCDCLPRUNNING_MASK   0x40000UL
 
#define _EMU_IFS_DCDCLPRUNNING_SHIFT   18
 
#define _EMU_IFS_EM23WAKEUP_DEFAULT   0x00000000UL
 
#define _EMU_IFS_EM23WAKEUP_MASK   0x1000000UL
 
#define _EMU_IFS_EM23WAKEUP_SHIFT   24
 
#define _EMU_IFS_MASK   0xE31FC0FFUL
 
#define _EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT   0x00000000UL
 
#define _EMU_IFS_NFETOVERCURRENTLIMIT_MASK   0x20000UL
 
#define _EMU_IFS_NFETOVERCURRENTLIMIT_SHIFT   17
 
#define _EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT   0x00000000UL
 
#define _EMU_IFS_PFETOVERCURRENTLIMIT_MASK   0x10000UL
 
#define _EMU_IFS_PFETOVERCURRENTLIMIT_SHIFT   16
 
#define _EMU_IFS_RESETVALUE   0x00000000UL
 
#define _EMU_IFS_TEMP_DEFAULT   0x00000000UL
 
#define _EMU_IFS_TEMP_MASK   0x20000000UL
 
#define _EMU_IFS_TEMP_SHIFT   29
 
#define _EMU_IFS_TEMPHIGH_DEFAULT   0x00000000UL
 
#define _EMU_IFS_TEMPHIGH_MASK   0x80000000UL
 
#define _EMU_IFS_TEMPHIGH_SHIFT   31
 
#define _EMU_IFS_TEMPLOW_DEFAULT   0x00000000UL
 
#define _EMU_IFS_TEMPLOW_MASK   0x40000000UL
 
#define _EMU_IFS_TEMPLOW_SHIFT   30
 
#define _EMU_IFS_VMONALTAVDDFALL_DEFAULT   0x00000000UL
 
#define _EMU_IFS_VMONALTAVDDFALL_MASK   0x4UL
 
#define _EMU_IFS_VMONALTAVDDFALL_SHIFT   2
 
#define _EMU_IFS_VMONALTAVDDRISE_DEFAULT   0x00000000UL
 
#define _EMU_IFS_VMONALTAVDDRISE_MASK   0x8UL
 
#define _EMU_IFS_VMONALTAVDDRISE_SHIFT   3
 
#define _EMU_IFS_VMONAVDDFALL_DEFAULT   0x00000000UL
 
#define _EMU_IFS_VMONAVDDFALL_MASK   0x1UL
 
#define _EMU_IFS_VMONAVDDFALL_SHIFT   0
 
#define _EMU_IFS_VMONAVDDRISE_DEFAULT   0x00000000UL
 
#define _EMU_IFS_VMONAVDDRISE_MASK   0x2UL
 
#define _EMU_IFS_VMONAVDDRISE_SHIFT   1
 
#define _EMU_IFS_VMONDVDDFALL_DEFAULT   0x00000000UL
 
#define _EMU_IFS_VMONDVDDFALL_MASK   0x10UL
 
#define _EMU_IFS_VMONDVDDFALL_SHIFT   4
 
#define _EMU_IFS_VMONDVDDRISE_DEFAULT   0x00000000UL
 
#define _EMU_IFS_VMONDVDDRISE_MASK   0x20UL
 
#define _EMU_IFS_VMONDVDDRISE_SHIFT   5
 
#define _EMU_IFS_VMONFVDDFALL_DEFAULT   0x00000000UL
 
#define _EMU_IFS_VMONFVDDFALL_MASK   0x4000UL
 
#define _EMU_IFS_VMONFVDDFALL_SHIFT   14
 
#define _EMU_IFS_VMONFVDDRISE_DEFAULT   0x00000000UL
 
#define _EMU_IFS_VMONFVDDRISE_MASK   0x8000UL
 
#define _EMU_IFS_VMONFVDDRISE_SHIFT   15
 
#define _EMU_IFS_VMONIO0FALL_DEFAULT   0x00000000UL
 
#define _EMU_IFS_VMONIO0FALL_MASK   0x40UL
 
#define _EMU_IFS_VMONIO0FALL_SHIFT   6
 
#define _EMU_IFS_VMONIO0RISE_DEFAULT   0x00000000UL
 
#define _EMU_IFS_VMONIO0RISE_MASK   0x80UL
 
#define _EMU_IFS_VMONIO0RISE_SHIFT   7
 
#define _EMU_IFS_VSCALEDONE_DEFAULT   0x00000000UL
 
#define _EMU_IFS_VSCALEDONE_MASK   0x2000000UL
 
#define _EMU_IFS_VSCALEDONE_SHIFT   25
 
#define _EMU_LOCK_LOCKKEY_DEFAULT   0x00000000UL
 
#define _EMU_LOCK_LOCKKEY_LOCK   0x00000000UL
 
#define _EMU_LOCK_LOCKKEY_LOCKED   0x00000001UL
 
#define _EMU_LOCK_LOCKKEY_MASK   0xFFFFUL
 
#define _EMU_LOCK_LOCKKEY_SHIFT   0
 
#define _EMU_LOCK_LOCKKEY_UNLOCK   0x0000ADE8UL
 
#define _EMU_LOCK_LOCKKEY_UNLOCKED   0x00000000UL
 
#define _EMU_LOCK_MASK   0x0000FFFFUL
 
#define _EMU_LOCK_RESETVALUE   0x00000000UL
 
#define _EMU_PWRCTRL_ANASW_AVDD   0x00000000UL
 
#define _EMU_PWRCTRL_ANASW_DEFAULT   0x00000000UL
 
#define _EMU_PWRCTRL_ANASW_DVDD   0x00000001UL
 
#define _EMU_PWRCTRL_ANASW_MASK   0x20UL
 
#define _EMU_PWRCTRL_ANASW_SHIFT   5
 
#define _EMU_PWRCTRL_IMMEDIATEPWRSWITCH_DEFAULT   0x00000000UL
 
#define _EMU_PWRCTRL_IMMEDIATEPWRSWITCH_MASK   0x2000UL
 
#define _EMU_PWRCTRL_IMMEDIATEPWRSWITCH_SHIFT   13
 
#define _EMU_PWRCTRL_MASK   0x00002420UL
 
#define _EMU_PWRCTRL_REGPWRSEL_AVDD   0x00000000UL
 
#define _EMU_PWRCTRL_REGPWRSEL_DEFAULT   0x00000000UL
 
#define _EMU_PWRCTRL_REGPWRSEL_DVDD   0x00000001UL
 
#define _EMU_PWRCTRL_REGPWRSEL_MASK   0x400UL
 
#define _EMU_PWRCTRL_REGPWRSEL_SHIFT   10
 
#define _EMU_PWRCTRL_RESETVALUE   0x00000000UL
 
#define _EMU_PWRLOCK_LOCKKEY_DEFAULT   0x00000000UL
 
#define _EMU_PWRLOCK_LOCKKEY_LOCK   0x00000000UL
 
#define _EMU_PWRLOCK_LOCKKEY_LOCKED   0x00000001UL
 
#define _EMU_PWRLOCK_LOCKKEY_MASK   0xFFFFUL
 
#define _EMU_PWRLOCK_LOCKKEY_SHIFT   0
 
#define _EMU_PWRLOCK_LOCKKEY_UNLOCK   0x0000ADE8UL
 
#define _EMU_PWRLOCK_LOCKKEY_UNLOCKED   0x00000000UL
 
#define _EMU_PWRLOCK_MASK   0x0000FFFFUL
 
#define _EMU_PWRLOCK_RESETVALUE   0x00000000UL
 
#define _EMU_RAM0CTRL_MASK   0x00000000UL
 
#define _EMU_RAM0CTRL_RESETVALUE   0x00000000UL
 
#define _EMU_RAM1CTRL_MASK   0x00000001UL
 
#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK   0x00000001UL
 
#define _EMU_RAM1CTRL_RAMPOWERDOWN_DEFAULT   0x00000000UL
 
#define _EMU_RAM1CTRL_RAMPOWERDOWN_MASK   0x1UL
 
#define _EMU_RAM1CTRL_RAMPOWERDOWN_NONE   0x00000000UL
 
#define _EMU_RAM1CTRL_RAMPOWERDOWN_SHIFT   0
 
#define _EMU_RAM1CTRL_RESETVALUE   0x00000000UL
 
#define _EMU_RAM2CTRL_MASK   0x00000001UL
 
#define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK   0x00000001UL
 
#define _EMU_RAM2CTRL_RAMPOWERDOWN_DEFAULT   0x00000000UL
 
#define _EMU_RAM2CTRL_RAMPOWERDOWN_MASK   0x1UL
 
#define _EMU_RAM2CTRL_RAMPOWERDOWN_NONE   0x00000000UL
 
#define _EMU_RAM2CTRL_RAMPOWERDOWN_SHIFT   0
 
#define _EMU_RAM2CTRL_RESETVALUE   0x00000000UL
 
#define _EMU_STATUS_EM4IORET_DEFAULT   0x00000000UL
 
#define _EMU_STATUS_EM4IORET_DISABLED   0x00000000UL
 
#define _EMU_STATUS_EM4IORET_ENABLED   0x00000001UL
 
#define _EMU_STATUS_EM4IORET_MASK   0x100000UL
 
#define _EMU_STATUS_EM4IORET_SHIFT   20
 
#define _EMU_STATUS_MASK   0x0417011FUL
 
#define _EMU_STATUS_RESETVALUE   0x00000000UL
 
#define _EMU_STATUS_TEMPACTIVE_DEFAULT   0x00000000UL
 
#define _EMU_STATUS_TEMPACTIVE_MASK   0x4000000UL
 
#define _EMU_STATUS_TEMPACTIVE_SHIFT   26
 
#define _EMU_STATUS_VMONALTAVDD_DEFAULT   0x00000000UL
 
#define _EMU_STATUS_VMONALTAVDD_MASK   0x4UL
 
#define _EMU_STATUS_VMONALTAVDD_SHIFT   2
 
#define _EMU_STATUS_VMONAVDD_DEFAULT   0x00000000UL
 
#define _EMU_STATUS_VMONAVDD_MASK   0x2UL
 
#define _EMU_STATUS_VMONAVDD_SHIFT   1
 
#define _EMU_STATUS_VMONDVDD_DEFAULT   0x00000000UL
 
#define _EMU_STATUS_VMONDVDD_MASK   0x8UL
 
#define _EMU_STATUS_VMONDVDD_SHIFT   3
 
#define _EMU_STATUS_VMONFVDD_DEFAULT   0x00000000UL
 
#define _EMU_STATUS_VMONFVDD_MASK   0x100UL
 
#define _EMU_STATUS_VMONFVDD_SHIFT   8
 
#define _EMU_STATUS_VMONIO0_DEFAULT   0x00000000UL
 
#define _EMU_STATUS_VMONIO0_MASK   0x10UL
 
#define _EMU_STATUS_VMONIO0_SHIFT   4
 
#define _EMU_STATUS_VMONRDY_DEFAULT   0x00000000UL
 
#define _EMU_STATUS_VMONRDY_MASK   0x1UL
 
#define _EMU_STATUS_VMONRDY_SHIFT   0
 
#define _EMU_STATUS_VSCALE_DEFAULT   0x00000000UL
 
#define _EMU_STATUS_VSCALE_MASK   0x30000UL
 
#define _EMU_STATUS_VSCALE_RESV   0x00000003UL
 
#define _EMU_STATUS_VSCALE_SHIFT   16
 
#define _EMU_STATUS_VSCALE_VSCALE0   0x00000002UL
 
#define _EMU_STATUS_VSCALE_VSCALE2   0x00000000UL
 
#define _EMU_STATUS_VSCALEBUSY_DEFAULT   0x00000000UL
 
#define _EMU_STATUS_VSCALEBUSY_MASK   0x40000UL
 
#define _EMU_STATUS_VSCALEBUSY_SHIFT   18
 
#define _EMU_TEMP_MASK   0x000000FFUL
 
#define _EMU_TEMP_RESETVALUE   0x00000000UL
 
#define _EMU_TEMP_TEMP_DEFAULT   0x00000000UL
 
#define _EMU_TEMP_TEMP_MASK   0xFFUL
 
#define _EMU_TEMP_TEMP_SHIFT   0
 
#define _EMU_TEMPLIMITS_EM4WUEN_DEFAULT   0x00000000UL
 
#define _EMU_TEMPLIMITS_EM4WUEN_MASK   0x10000UL
 
#define _EMU_TEMPLIMITS_EM4WUEN_SHIFT   16
 
#define _EMU_TEMPLIMITS_MASK   0x0001FFFFUL
 
#define _EMU_TEMPLIMITS_RESETVALUE   0x0000FF00UL
 
#define _EMU_TEMPLIMITS_TEMPHIGH_DEFAULT   0x000000FFUL
 
#define _EMU_TEMPLIMITS_TEMPHIGH_MASK   0xFF00UL
 
#define _EMU_TEMPLIMITS_TEMPHIGH_SHIFT   8
 
#define _EMU_TEMPLIMITS_TEMPLOW_DEFAULT   0x00000000UL
 
#define _EMU_TEMPLIMITS_TEMPLOW_MASK   0xFFUL
 
#define _EMU_TEMPLIMITS_TEMPLOW_SHIFT   0
 
#define _EMU_VMONALTAVDDCTRL_EN_DEFAULT   0x00000000UL
 
#define _EMU_VMONALTAVDDCTRL_EN_MASK   0x1UL
 
#define _EMU_VMONALTAVDDCTRL_EN_SHIFT   0
 
#define _EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT   0x00000000UL
 
#define _EMU_VMONALTAVDDCTRL_FALLWU_MASK   0x8UL
 
#define _EMU_VMONALTAVDDCTRL_FALLWU_SHIFT   3
 
#define _EMU_VMONALTAVDDCTRL_MASK   0x0000FF0DUL
 
#define _EMU_VMONALTAVDDCTRL_RESETVALUE   0x00000000UL
 
#define _EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT   0x00000000UL
 
#define _EMU_VMONALTAVDDCTRL_RISEWU_MASK   0x4UL
 
#define _EMU_VMONALTAVDDCTRL_RISEWU_SHIFT   2
 
#define _EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT   0x00000000UL
 
#define _EMU_VMONALTAVDDCTRL_THRESCOARSE_MASK   0xF000UL
 
#define _EMU_VMONALTAVDDCTRL_THRESCOARSE_SHIFT   12
 
#define _EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT   0x00000000UL
 
#define _EMU_VMONALTAVDDCTRL_THRESFINE_MASK   0xF00UL
 
#define _EMU_VMONALTAVDDCTRL_THRESFINE_SHIFT   8
 
#define _EMU_VMONAVDDCTRL_EN_DEFAULT   0x00000000UL
 
#define _EMU_VMONAVDDCTRL_EN_MASK   0x1UL
 
#define _EMU_VMONAVDDCTRL_EN_SHIFT   0
 
#define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT   0x00000000UL
 
#define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_MASK   0xF000UL
 
#define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_SHIFT   12
 
#define _EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT   0x00000000UL
 
#define _EMU_VMONAVDDCTRL_FALLTHRESFINE_MASK   0xF00UL
 
#define _EMU_VMONAVDDCTRL_FALLTHRESFINE_SHIFT   8
 
#define _EMU_VMONAVDDCTRL_FALLWU_DEFAULT   0x00000000UL
 
#define _EMU_VMONAVDDCTRL_FALLWU_MASK   0x8UL
 
#define _EMU_VMONAVDDCTRL_FALLWU_SHIFT   3
 
#define _EMU_VMONAVDDCTRL_MASK   0x00FFFF0DUL
 
#define _EMU_VMONAVDDCTRL_RESETVALUE   0x00000000UL
 
#define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT   0x00000000UL
 
#define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_MASK   0xF00000UL
 
#define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_SHIFT   20
 
#define _EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT   0x00000000UL
 
#define _EMU_VMONAVDDCTRL_RISETHRESFINE_MASK   0xF0000UL
 
#define _EMU_VMONAVDDCTRL_RISETHRESFINE_SHIFT   16
 
#define _EMU_VMONAVDDCTRL_RISEWU_DEFAULT   0x00000000UL
 
#define _EMU_VMONAVDDCTRL_RISEWU_MASK   0x4UL
 
#define _EMU_VMONAVDDCTRL_RISEWU_SHIFT   2
 
#define _EMU_VMONDVDDCTRL_EN_DEFAULT   0x00000000UL
 
#define _EMU_VMONDVDDCTRL_EN_MASK   0x1UL
 
#define _EMU_VMONDVDDCTRL_EN_SHIFT   0
 
#define _EMU_VMONDVDDCTRL_FALLWU_DEFAULT   0x00000000UL
 
#define _EMU_VMONDVDDCTRL_FALLWU_MASK   0x8UL
 
#define _EMU_VMONDVDDCTRL_FALLWU_SHIFT   3
 
#define _EMU_VMONDVDDCTRL_MASK   0x0000FF0DUL
 
#define _EMU_VMONDVDDCTRL_RESETVALUE   0x00000000UL
 
#define _EMU_VMONDVDDCTRL_RISEWU_DEFAULT   0x00000000UL
 
#define _EMU_VMONDVDDCTRL_RISEWU_MASK   0x4UL
 
#define _EMU_VMONDVDDCTRL_RISEWU_SHIFT   2
 
#define _EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT   0x00000000UL
 
#define _EMU_VMONDVDDCTRL_THRESCOARSE_MASK   0xF000UL
 
#define _EMU_VMONDVDDCTRL_THRESCOARSE_SHIFT   12
 
#define _EMU_VMONDVDDCTRL_THRESFINE_DEFAULT   0x00000000UL
 
#define _EMU_VMONDVDDCTRL_THRESFINE_MASK   0xF00UL
 
#define _EMU_VMONDVDDCTRL_THRESFINE_SHIFT   8
 
#define _EMU_VMONIO0CTRL_EN_DEFAULT   0x00000000UL
 
#define _EMU_VMONIO0CTRL_EN_MASK   0x1UL
 
#define _EMU_VMONIO0CTRL_EN_SHIFT   0
 
#define _EMU_VMONIO0CTRL_FALLWU_DEFAULT   0x00000000UL
 
#define _EMU_VMONIO0CTRL_FALLWU_MASK   0x8UL
 
#define _EMU_VMONIO0CTRL_FALLWU_SHIFT   3
 
#define _EMU_VMONIO0CTRL_MASK   0x0000FF1DUL
 
#define _EMU_VMONIO0CTRL_RESETVALUE   0x00000000UL
 
#define _EMU_VMONIO0CTRL_RETDIS_DEFAULT   0x00000000UL
 
#define _EMU_VMONIO0CTRL_RETDIS_MASK   0x10UL
 
#define _EMU_VMONIO0CTRL_RETDIS_SHIFT   4
 
#define _EMU_VMONIO0CTRL_RISEWU_DEFAULT   0x00000000UL
 
#define _EMU_VMONIO0CTRL_RISEWU_MASK   0x4UL
 
#define _EMU_VMONIO0CTRL_RISEWU_SHIFT   2
 
#define _EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT   0x00000000UL
 
#define _EMU_VMONIO0CTRL_THRESCOARSE_MASK   0xF000UL
 
#define _EMU_VMONIO0CTRL_THRESCOARSE_SHIFT   12
 
#define _EMU_VMONIO0CTRL_THRESFINE_DEFAULT   0x00000000UL
 
#define _EMU_VMONIO0CTRL_THRESFINE_MASK   0xF00UL
 
#define _EMU_VMONIO0CTRL_THRESFINE_SHIFT   8
 
#define EMU_CMD_EM01VSCALE0   (0x1UL << 4)
 
#define EMU_CMD_EM01VSCALE0_DEFAULT   (_EMU_CMD_EM01VSCALE0_DEFAULT << 4)
 
#define EMU_CMD_EM01VSCALE2   (0x1UL << 6)
 
#define EMU_CMD_EM01VSCALE2_DEFAULT   (_EMU_CMD_EM01VSCALE2_DEFAULT << 6)
 
#define EMU_CMD_EM4UNLATCH   (0x1UL << 0)
 
#define EMU_CMD_EM4UNLATCH_DEFAULT   (_EMU_CMD_EM4UNLATCH_DEFAULT << 0)
 
#define EMU_CTRL_EM01LD   (0x1UL << 3)
 
#define EMU_CTRL_EM01LD_DEFAULT   (_EMU_CTRL_EM01LD_DEFAULT << 3)
 
#define EMU_CTRL_EM23VSCALE_DEFAULT   (_EMU_CTRL_EM23VSCALE_DEFAULT << 8)
 
#define EMU_CTRL_EM23VSCALE_RESV   (_EMU_CTRL_EM23VSCALE_RESV << 8)
 
#define EMU_CTRL_EM23VSCALE_VSCALE0   (_EMU_CTRL_EM23VSCALE_VSCALE0 << 8)
 
#define EMU_CTRL_EM23VSCALE_VSCALE2   (_EMU_CTRL_EM23VSCALE_VSCALE2 << 8)
 
#define EMU_CTRL_EM23VSCALEAUTOWSEN   (0x1UL << 4)
 
#define EMU_CTRL_EM23VSCALEAUTOWSEN_DEFAULT   (_EMU_CTRL_EM23VSCALEAUTOWSEN_DEFAULT << 4)
 
#define EMU_CTRL_EM2BLOCK   (0x1UL << 1)
 
#define EMU_CTRL_EM2BLOCK_DEFAULT   (_EMU_CTRL_EM2BLOCK_DEFAULT << 1)
 
#define EMU_CTRL_EM2BODDIS   (0x1UL << 2)
 
#define EMU_CTRL_EM2BODDIS_DEFAULT   (_EMU_CTRL_EM2BODDIS_DEFAULT << 2)
 
#define EMU_CTRL_EM4HVSCALE_DEFAULT   (_EMU_CTRL_EM4HVSCALE_DEFAULT << 16)
 
#define EMU_CTRL_EM4HVSCALE_RESV   (_EMU_CTRL_EM4HVSCALE_RESV << 16)
 
#define EMU_CTRL_EM4HVSCALE_VSCALE0   (_EMU_CTRL_EM4HVSCALE_VSCALE0 << 16)
 
#define EMU_CTRL_EM4HVSCALE_VSCALE2   (_EMU_CTRL_EM4HVSCALE_VSCALE2 << 16)
 
#define EMU_DCDCCLIMCTRL_BYPLIMEN   (0x1UL << 13)
 
#define EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT   (_EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT << 13)
 
#define EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT   (_EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT << 8)
 
#define EMU_DCDCCTRL_DCDCMODE_BYPASS   (_EMU_DCDCCTRL_DCDCMODE_BYPASS << 0)
 
#define EMU_DCDCCTRL_DCDCMODE_DEFAULT   (_EMU_DCDCCTRL_DCDCMODE_DEFAULT << 0)
 
#define EMU_DCDCCTRL_DCDCMODE_LOWNOISE   (_EMU_DCDCCTRL_DCDCMODE_LOWNOISE << 0)
 
#define EMU_DCDCCTRL_DCDCMODE_LOWPOWER   (_EMU_DCDCCTRL_DCDCMODE_LOWPOWER << 0)
 
#define EMU_DCDCCTRL_DCDCMODE_OFF   (_EMU_DCDCCTRL_DCDCMODE_OFF << 0)
 
#define EMU_DCDCCTRL_DCDCMODEEM23   (0x1UL << 4)
 
#define EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT   (_EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT << 4)
 
#define EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER   (_EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER << 4)
 
#define EMU_DCDCCTRL_DCDCMODEEM23_EM23SW   (_EMU_DCDCCTRL_DCDCMODEEM23_EM23SW << 4)
 
#define EMU_DCDCCTRL_DCDCMODEEM4   (0x1UL << 5)
 
#define EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT   (_EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT << 5)
 
#define EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER   (_EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER << 5)
 
#define EMU_DCDCCTRL_DCDCMODEEM4_EM4SW   (_EMU_DCDCCTRL_DCDCMODEEM4_EM4SW << 5)
 
#define EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT   (_EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT << 20)
 
#define EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT   (_EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT << 24)
 
#define EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT   (_EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT << 28)
 
#define EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT   (_EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT << 0)
 
#define EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT   (_EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT << 4)
 
#define EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT   (_EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT << 12)
 
#define EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT   (_EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT << 0)
 
#define EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT   (_EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT << 24)
 
#define EMU_DCDCLNVCTRL_LNATT   (0x1UL << 1)
 
#define EMU_DCDCLNVCTRL_LNATT_DEFAULT   (_EMU_DCDCLNVCTRL_LNATT_DEFAULT << 1)
 
#define EMU_DCDCLNVCTRL_LNATT_DIV3   (_EMU_DCDCLNVCTRL_LNATT_DIV3 << 1)
 
#define EMU_DCDCLNVCTRL_LNATT_DIV6   (_EMU_DCDCLNVCTRL_LNATT_DIV6 << 1)
 
#define EMU_DCDCLNVCTRL_LNVREF_DEFAULT   (_EMU_DCDCLNVCTRL_LNVREF_DEFAULT << 8)
 
#define EMU_DCDCLPCTRL_LPBLANK_DEFAULT   (_EMU_DCDCLPCTRL_LPBLANK_DEFAULT << 25)
 
#define EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_DEFAULT   (_EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_DEFAULT << 12)
 
#define EMU_DCDCLPCTRL_LPVREFDUTYEN   (0x1UL << 24)
 
#define EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT   (_EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT << 24)
 
#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS0   (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS0 << 8)
 
#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS1   (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS1 << 8)
 
#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS2   (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS2 << 8)
 
#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3   (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3 << 8)
 
#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_DEFAULT   (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_DEFAULT << 8)
 
#define EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_DEFAULT   (_EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_DEFAULT << 12)
 
#define EMU_DCDCLPVCTRL_LPATT   (0x1UL << 0)
 
#define EMU_DCDCLPVCTRL_LPATT_DEFAULT   (_EMU_DCDCLPVCTRL_LPATT_DEFAULT << 0)
 
#define EMU_DCDCLPVCTRL_LPATT_DIV4   (_EMU_DCDCLPVCTRL_LPATT_DIV4 << 0)
 
#define EMU_DCDCLPVCTRL_LPATT_DIV8   (_EMU_DCDCLPVCTRL_LPATT_DIV8 << 0)
 
#define EMU_DCDCLPVCTRL_LPVREF_DEFAULT   (_EMU_DCDCLPVCTRL_LPVREF_DEFAULT << 1)
 
#define EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT   (_EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT << 16)
 
#define EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT   (_EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT << 24)
 
#define EMU_DCDCMISCCTRL_LNFORCECCM   (0x1UL << 0)
 
#define EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT   (_EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT << 0)
 
#define EMU_DCDCMISCCTRL_LNFORCECCMIMM   (0x1UL << 5)
 
#define EMU_DCDCMISCCTRL_LNFORCECCMIMM_DEFAULT   (_EMU_DCDCMISCCTRL_LNFORCECCMIMM_DEFAULT << 5)
 
#define EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT   (_EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT << 20)
 
#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS0   (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS0 << 28)
 
#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS1   (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS1 << 28)
 
#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS2   (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS2 << 28)
 
#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS3   (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS3 << 28)
 
#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_DEFAULT   (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_DEFAULT << 28)
 
#define EMU_DCDCMISCCTRL_LPCMPHYSDIS   (0x1UL << 1)
 
#define EMU_DCDCMISCCTRL_LPCMPHYSDIS_DEFAULT   (_EMU_DCDCMISCCTRL_LPCMPHYSDIS_DEFAULT << 1)
 
#define EMU_DCDCMISCCTRL_LPCMPHYSHI   (0x1UL << 2)
 
#define EMU_DCDCMISCCTRL_LPCMPHYSHI_DEFAULT   (_EMU_DCDCMISCCTRL_LPCMPHYSHI_DEFAULT << 2)
 
#define EMU_DCDCMISCCTRL_NFETCNT_DEFAULT   (_EMU_DCDCMISCCTRL_NFETCNT_DEFAULT << 12)
 
#define EMU_DCDCMISCCTRL_PFETCNT_DEFAULT   (_EMU_DCDCMISCCTRL_PFETCNT_DEFAULT << 8)
 
#define EMU_DCDCSYNC_DCDCCTRLBUSY   (0x1UL << 0)
 
#define EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT   (_EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT << 0)
 
#define EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT   (_EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT << 8)
 
#define EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT   (_EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT << 4)
 
#define EMU_EM23PERNORETAINCMD_ACMP0UNLOCK   (0x1UL << 0)
 
#define EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_DEFAULT   (_EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_DEFAULT << 0)
 
#define EMU_EM23PERNORETAINCMD_ACMP1UNLOCK   (0x1UL << 1)
 
#define EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_DEFAULT   (_EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_DEFAULT << 1)
 
#define EMU_EM23PERNORETAINCMD_ADC0UNLOCK   (0x1UL << 9)
 
#define EMU_EM23PERNORETAINCMD_ADC0UNLOCK_DEFAULT   (_EMU_EM23PERNORETAINCMD_ADC0UNLOCK_DEFAULT << 9)
 
#define EMU_EM23PERNORETAINCMD_DAC0UNLOCK   (0x1UL << 7)
 
#define EMU_EM23PERNORETAINCMD_DAC0UNLOCK_DEFAULT   (_EMU_EM23PERNORETAINCMD_DAC0UNLOCK_DEFAULT << 7)
 
#define EMU_EM23PERNORETAINCMD_I2C0UNLOCK   (0x1UL << 5)
 
#define EMU_EM23PERNORETAINCMD_I2C0UNLOCK_DEFAULT   (_EMU_EM23PERNORETAINCMD_I2C0UNLOCK_DEFAULT << 5)
 
#define EMU_EM23PERNORETAINCMD_IDAC0UNLOCK   (0x1UL << 8)
 
#define EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_DEFAULT   (_EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_DEFAULT << 8)
 
#define EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK   (0x1UL << 13)
 
#define EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_DEFAULT   (_EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_DEFAULT << 13)
 
#define EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK   (0x1UL << 10)
 
#define EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_DEFAULT   (_EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_DEFAULT << 10)
 
#define EMU_EM23PERNORETAINCMD_LEUART0UNLOCK   (0x1UL << 15)
 
#define EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_DEFAULT   (_EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_DEFAULT << 15)
 
#define EMU_EM23PERNORETAINCMD_PCNT0UNLOCK   (0x1UL << 2)
 
#define EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_DEFAULT   (_EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_DEFAULT << 2)
 
#define EMU_EM23PERNORETAINCMD_WDOG0UNLOCK   (0x1UL << 11)
 
#define EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_DEFAULT   (_EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_DEFAULT << 11)
 
#define EMU_EM23PERNORETAINCMD_WDOG1UNLOCK   (0x1UL << 12)
 
#define EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_DEFAULT   (_EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_DEFAULT << 12)
 
#define EMU_EM23PERNORETAINCTRL_ACMP0DIS   (0x1UL << 0)
 
#define EMU_EM23PERNORETAINCTRL_ACMP0DIS_DEFAULT   (_EMU_EM23PERNORETAINCTRL_ACMP0DIS_DEFAULT << 0)
 
#define EMU_EM23PERNORETAINCTRL_ACMP1DIS   (0x1UL << 1)
 
#define EMU_EM23PERNORETAINCTRL_ACMP1DIS_DEFAULT   (_EMU_EM23PERNORETAINCTRL_ACMP1DIS_DEFAULT << 1)
 
#define EMU_EM23PERNORETAINCTRL_ADC0DIS   (0x1UL << 9)
 
#define EMU_EM23PERNORETAINCTRL_ADC0DIS_DEFAULT   (_EMU_EM23PERNORETAINCTRL_ADC0DIS_DEFAULT << 9)
 
#define EMU_EM23PERNORETAINCTRL_DAC0DIS   (0x1UL << 7)
 
#define EMU_EM23PERNORETAINCTRL_DAC0DIS_DEFAULT   (_EMU_EM23PERNORETAINCTRL_DAC0DIS_DEFAULT << 7)
 
#define EMU_EM23PERNORETAINCTRL_I2C0DIS   (0x1UL << 5)
 
#define EMU_EM23PERNORETAINCTRL_I2C0DIS_DEFAULT   (_EMU_EM23PERNORETAINCTRL_I2C0DIS_DEFAULT << 5)
 
#define EMU_EM23PERNORETAINCTRL_IDAC0DIS   (0x1UL << 8)
 
#define EMU_EM23PERNORETAINCTRL_IDAC0DIS_DEFAULT   (_EMU_EM23PERNORETAINCTRL_IDAC0DIS_DEFAULT << 8)
 
#define EMU_EM23PERNORETAINCTRL_LESENSE0DIS   (0x1UL << 13)
 
#define EMU_EM23PERNORETAINCTRL_LESENSE0DIS_DEFAULT   (_EMU_EM23PERNORETAINCTRL_LESENSE0DIS_DEFAULT << 13)
 
#define EMU_EM23PERNORETAINCTRL_LETIMER0DIS   (0x1UL << 10)
 
#define EMU_EM23PERNORETAINCTRL_LETIMER0DIS_DEFAULT   (_EMU_EM23PERNORETAINCTRL_LETIMER0DIS_DEFAULT << 10)
 
#define EMU_EM23PERNORETAINCTRL_LEUART0DIS   (0x1UL << 15)
 
#define EMU_EM23PERNORETAINCTRL_LEUART0DIS_DEFAULT   (_EMU_EM23PERNORETAINCTRL_LEUART0DIS_DEFAULT << 15)
 
#define EMU_EM23PERNORETAINCTRL_PCNT0DIS   (0x1UL << 2)
 
#define EMU_EM23PERNORETAINCTRL_PCNT0DIS_DEFAULT   (_EMU_EM23PERNORETAINCTRL_PCNT0DIS_DEFAULT << 2)
 
#define EMU_EM23PERNORETAINCTRL_WDOG0DIS   (0x1UL << 11)
 
#define EMU_EM23PERNORETAINCTRL_WDOG0DIS_DEFAULT   (_EMU_EM23PERNORETAINCTRL_WDOG0DIS_DEFAULT << 11)
 
#define EMU_EM23PERNORETAINCTRL_WDOG1DIS   (0x1UL << 12)
 
#define EMU_EM23PERNORETAINCTRL_WDOG1DIS_DEFAULT   (_EMU_EM23PERNORETAINCTRL_WDOG1DIS_DEFAULT << 12)
 
#define EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED   (0x1UL << 0)
 
#define EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_DEFAULT   (_EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_DEFAULT << 0)
 
#define EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED   (0x1UL << 1)
 
#define EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_DEFAULT   (_EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_DEFAULT << 1)
 
#define EMU_EM23PERNORETAINSTATUS_ADC0LOCKED   (0x1UL << 9)
 
#define EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_DEFAULT   (_EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_DEFAULT << 9)
 
#define EMU_EM23PERNORETAINSTATUS_DAC0LOCKED   (0x1UL << 7)
 
#define EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_DEFAULT   (_EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_DEFAULT << 7)
 
#define EMU_EM23PERNORETAINSTATUS_I2C0LOCKED   (0x1UL << 5)
 
#define EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_DEFAULT   (_EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_DEFAULT << 5)
 
#define EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED   (0x1UL << 8)
 
#define EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_DEFAULT   (_EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_DEFAULT << 8)
 
#define EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED   (0x1UL << 13)
 
#define EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_DEFAULT   (_EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_DEFAULT << 13)
 
#define EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED   (0x1UL << 10)
 
#define EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_DEFAULT   (_EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_DEFAULT << 10)
 
#define EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED   (0x1UL << 15)
 
#define EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_DEFAULT   (_EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_DEFAULT << 15)
 
#define EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED   (0x1UL << 2)
 
#define EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_DEFAULT   (_EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_DEFAULT << 2)
 
#define EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED   (0x1UL << 11)
 
#define EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_DEFAULT   (_EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_DEFAULT << 11)
 
#define EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED   (0x1UL << 12)
 
#define EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_DEFAULT   (_EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_DEFAULT << 12)
 
#define EMU_EM4CTRL_EM4ENTRY_DEFAULT   (_EMU_EM4CTRL_EM4ENTRY_DEFAULT << 16)
 
#define EMU_EM4CTRL_EM4IORETMODE_DEFAULT   (_EMU_EM4CTRL_EM4IORETMODE_DEFAULT << 4)
 
#define EMU_EM4CTRL_EM4IORETMODE_DISABLE   (_EMU_EM4CTRL_EM4IORETMODE_DISABLE << 4)
 
#define EMU_EM4CTRL_EM4IORETMODE_EM4EXIT   (_EMU_EM4CTRL_EM4IORETMODE_EM4EXIT << 4)
 
#define EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH   (_EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH << 4)
 
#define EMU_EM4CTRL_EM4STATE   (0x1UL << 0)
 
#define EMU_EM4CTRL_EM4STATE_DEFAULT   (_EMU_EM4CTRL_EM4STATE_DEFAULT << 0)
 
#define EMU_EM4CTRL_EM4STATE_EM4H   (_EMU_EM4CTRL_EM4STATE_EM4H << 0)
 
#define EMU_EM4CTRL_EM4STATE_EM4S   (_EMU_EM4CTRL_EM4STATE_EM4S << 0)
 
#define EMU_EM4CTRL_RETAINLFRCO   (0x1UL << 1)
 
#define EMU_EM4CTRL_RETAINLFRCO_DEFAULT   (_EMU_EM4CTRL_RETAINLFRCO_DEFAULT << 1)
 
#define EMU_EM4CTRL_RETAINLFXO   (0x1UL << 2)
 
#define EMU_EM4CTRL_RETAINLFXO_DEFAULT   (_EMU_EM4CTRL_RETAINLFXO_DEFAULT << 2)
 
#define EMU_EM4CTRL_RETAINULFRCO   (0x1UL << 3)
 
#define EMU_EM4CTRL_RETAINULFRCO_DEFAULT   (_EMU_EM4CTRL_RETAINULFRCO_DEFAULT << 3)
 
#define EMU_IEN_DCDCINBYPASS   (0x1UL << 20)
 
#define EMU_IEN_DCDCINBYPASS_DEFAULT   (_EMU_IEN_DCDCINBYPASS_DEFAULT << 20)
 
#define EMU_IEN_DCDCLNRUNNING   (0x1UL << 19)
 
#define EMU_IEN_DCDCLNRUNNING_DEFAULT   (_EMU_IEN_DCDCLNRUNNING_DEFAULT << 19)
 
#define EMU_IEN_DCDCLPRUNNING   (0x1UL << 18)
 
#define EMU_IEN_DCDCLPRUNNING_DEFAULT   (_EMU_IEN_DCDCLPRUNNING_DEFAULT << 18)
 
#define EMU_IEN_EM23WAKEUP   (0x1UL << 24)
 
#define EMU_IEN_EM23WAKEUP_DEFAULT   (_EMU_IEN_EM23WAKEUP_DEFAULT << 24)
 
#define EMU_IEN_NFETOVERCURRENTLIMIT   (0x1UL << 17)
 
#define EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT   (_EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT << 17)
 
#define EMU_IEN_PFETOVERCURRENTLIMIT   (0x1UL << 16)
 
#define EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT   (_EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT << 16)
 
#define EMU_IEN_TEMP   (0x1UL << 29)
 
#define EMU_IEN_TEMP_DEFAULT   (_EMU_IEN_TEMP_DEFAULT << 29)
 
#define EMU_IEN_TEMPHIGH   (0x1UL << 31)
 
#define EMU_IEN_TEMPHIGH_DEFAULT   (_EMU_IEN_TEMPHIGH_DEFAULT << 31)
 
#define EMU_IEN_TEMPLOW   (0x1UL << 30)
 
#define EMU_IEN_TEMPLOW_DEFAULT   (_EMU_IEN_TEMPLOW_DEFAULT << 30)
 
#define EMU_IEN_VMONALTAVDDFALL   (0x1UL << 2)
 
#define EMU_IEN_VMONALTAVDDFALL_DEFAULT   (_EMU_IEN_VMONALTAVDDFALL_DEFAULT << 2)
 
#define EMU_IEN_VMONALTAVDDRISE   (0x1UL << 3)
 
#define EMU_IEN_VMONALTAVDDRISE_DEFAULT   (_EMU_IEN_VMONALTAVDDRISE_DEFAULT << 3)
 
#define EMU_IEN_VMONAVDDFALL   (0x1UL << 0)
 
#define EMU_IEN_VMONAVDDFALL_DEFAULT   (_EMU_IEN_VMONAVDDFALL_DEFAULT << 0)
 
#define EMU_IEN_VMONAVDDRISE   (0x1UL << 1)
 
#define EMU_IEN_VMONAVDDRISE_DEFAULT   (_EMU_IEN_VMONAVDDRISE_DEFAULT << 1)
 
#define EMU_IEN_VMONDVDDFALL   (0x1UL << 4)
 
#define EMU_IEN_VMONDVDDFALL_DEFAULT   (_EMU_IEN_VMONDVDDFALL_DEFAULT << 4)
 
#define EMU_IEN_VMONDVDDRISE   (0x1UL << 5)
 
#define EMU_IEN_VMONDVDDRISE_DEFAULT   (_EMU_IEN_VMONDVDDRISE_DEFAULT << 5)
 
#define EMU_IEN_VMONFVDDFALL   (0x1UL << 14)
 
#define EMU_IEN_VMONFVDDFALL_DEFAULT   (_EMU_IEN_VMONFVDDFALL_DEFAULT << 14)
 
#define EMU_IEN_VMONFVDDRISE   (0x1UL << 15)
 
#define EMU_IEN_VMONFVDDRISE_DEFAULT   (_EMU_IEN_VMONFVDDRISE_DEFAULT << 15)
 
#define EMU_IEN_VMONIO0FALL   (0x1UL << 6)
 
#define EMU_IEN_VMONIO0FALL_DEFAULT   (_EMU_IEN_VMONIO0FALL_DEFAULT << 6)
 
#define EMU_IEN_VMONIO0RISE   (0x1UL << 7)
 
#define EMU_IEN_VMONIO0RISE_DEFAULT   (_EMU_IEN_VMONIO0RISE_DEFAULT << 7)
 
#define EMU_IEN_VSCALEDONE   (0x1UL << 25)
 
#define EMU_IEN_VSCALEDONE_DEFAULT   (_EMU_IEN_VSCALEDONE_DEFAULT << 25)
 
#define EMU_IF_DCDCINBYPASS   (0x1UL << 20)
 
#define EMU_IF_DCDCINBYPASS_DEFAULT   (_EMU_IF_DCDCINBYPASS_DEFAULT << 20)
 
#define EMU_IF_DCDCLNRUNNING   (0x1UL << 19)
 
#define EMU_IF_DCDCLNRUNNING_DEFAULT   (_EMU_IF_DCDCLNRUNNING_DEFAULT << 19)
 
#define EMU_IF_DCDCLPRUNNING   (0x1UL << 18)
 
#define EMU_IF_DCDCLPRUNNING_DEFAULT   (_EMU_IF_DCDCLPRUNNING_DEFAULT << 18)
 
#define EMU_IF_EM23WAKEUP   (0x1UL << 24)
 
#define EMU_IF_EM23WAKEUP_DEFAULT   (_EMU_IF_EM23WAKEUP_DEFAULT << 24)
 
#define EMU_IF_NFETOVERCURRENTLIMIT   (0x1UL << 17)
 
#define EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT   (_EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT << 17)
 
#define EMU_IF_PFETOVERCURRENTLIMIT   (0x1UL << 16)
 
#define EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT   (_EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT << 16)
 
#define EMU_IF_TEMP   (0x1UL << 29)
 
#define EMU_IF_TEMP_DEFAULT   (_EMU_IF_TEMP_DEFAULT << 29)
 
#define EMU_IF_TEMPHIGH   (0x1UL << 31)
 
#define EMU_IF_TEMPHIGH_DEFAULT   (_EMU_IF_TEMPHIGH_DEFAULT << 31)
 
#define EMU_IF_TEMPLOW   (0x1UL << 30)
 
#define EMU_IF_TEMPLOW_DEFAULT   (_EMU_IF_TEMPLOW_DEFAULT << 30)
 
#define EMU_IF_VMONALTAVDDFALL   (0x1UL << 2)
 
#define EMU_IF_VMONALTAVDDFALL_DEFAULT   (_EMU_IF_VMONALTAVDDFALL_DEFAULT << 2)
 
#define EMU_IF_VMONALTAVDDRISE   (0x1UL << 3)
 
#define EMU_IF_VMONALTAVDDRISE_DEFAULT   (_EMU_IF_VMONALTAVDDRISE_DEFAULT << 3)
 
#define EMU_IF_VMONAVDDFALL   (0x1UL << 0)
 
#define EMU_IF_VMONAVDDFALL_DEFAULT   (_EMU_IF_VMONAVDDFALL_DEFAULT << 0)
 
#define EMU_IF_VMONAVDDRISE   (0x1UL << 1)
 
#define EMU_IF_VMONAVDDRISE_DEFAULT   (_EMU_IF_VMONAVDDRISE_DEFAULT << 1)
 
#define EMU_IF_VMONDVDDFALL   (0x1UL << 4)
 
#define EMU_IF_VMONDVDDFALL_DEFAULT   (_EMU_IF_VMONDVDDFALL_DEFAULT << 4)
 
#define EMU_IF_VMONDVDDRISE   (0x1UL << 5)
 
#define EMU_IF_VMONDVDDRISE_DEFAULT   (_EMU_IF_VMONDVDDRISE_DEFAULT << 5)
 
#define EMU_IF_VMONFVDDFALL   (0x1UL << 14)
 
#define EMU_IF_VMONFVDDFALL_DEFAULT   (_EMU_IF_VMONFVDDFALL_DEFAULT << 14)
 
#define EMU_IF_VMONFVDDRISE   (0x1UL << 15)
 
#define EMU_IF_VMONFVDDRISE_DEFAULT   (_EMU_IF_VMONFVDDRISE_DEFAULT << 15)
 
#define EMU_IF_VMONIO0FALL   (0x1UL << 6)
 
#define EMU_IF_VMONIO0FALL_DEFAULT   (_EMU_IF_VMONIO0FALL_DEFAULT << 6)
 
#define EMU_IF_VMONIO0RISE   (0x1UL << 7)
 
#define EMU_IF_VMONIO0RISE_DEFAULT   (_EMU_IF_VMONIO0RISE_DEFAULT << 7)
 
#define EMU_IF_VSCALEDONE   (0x1UL << 25)
 
#define EMU_IF_VSCALEDONE_DEFAULT   (_EMU_IF_VSCALEDONE_DEFAULT << 25)
 
#define EMU_IFC_DCDCINBYPASS   (0x1UL << 20)
 
#define EMU_IFC_DCDCINBYPASS_DEFAULT   (_EMU_IFC_DCDCINBYPASS_DEFAULT << 20)
 
#define EMU_IFC_DCDCLNRUNNING   (0x1UL << 19)
 
#define EMU_IFC_DCDCLNRUNNING_DEFAULT   (_EMU_IFC_DCDCLNRUNNING_DEFAULT << 19)
 
#define EMU_IFC_DCDCLPRUNNING   (0x1UL << 18)
 
#define EMU_IFC_DCDCLPRUNNING_DEFAULT   (_EMU_IFC_DCDCLPRUNNING_DEFAULT << 18)
 
#define EMU_IFC_EM23WAKEUP   (0x1UL << 24)
 
#define EMU_IFC_EM23WAKEUP_DEFAULT   (_EMU_IFC_EM23WAKEUP_DEFAULT << 24)
 
#define EMU_IFC_NFETOVERCURRENTLIMIT   (0x1UL << 17)
 
#define EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT   (_EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT << 17)
 
#define EMU_IFC_PFETOVERCURRENTLIMIT   (0x1UL << 16)
 
#define EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT   (_EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT << 16)
 
#define EMU_IFC_TEMP   (0x1UL << 29)
 
#define EMU_IFC_TEMP_DEFAULT   (_EMU_IFC_TEMP_DEFAULT << 29)
 
#define EMU_IFC_TEMPHIGH   (0x1UL << 31)
 
#define EMU_IFC_TEMPHIGH_DEFAULT   (_EMU_IFC_TEMPHIGH_DEFAULT << 31)
 
#define EMU_IFC_TEMPLOW   (0x1UL << 30)
 
#define EMU_IFC_TEMPLOW_DEFAULT   (_EMU_IFC_TEMPLOW_DEFAULT << 30)
 
#define EMU_IFC_VMONALTAVDDFALL   (0x1UL << 2)
 
#define EMU_IFC_VMONALTAVDDFALL_DEFAULT   (_EMU_IFC_VMONALTAVDDFALL_DEFAULT << 2)
 
#define EMU_IFC_VMONALTAVDDRISE   (0x1UL << 3)
 
#define EMU_IFC_VMONALTAVDDRISE_DEFAULT   (_EMU_IFC_VMONALTAVDDRISE_DEFAULT << 3)
 
#define EMU_IFC_VMONAVDDFALL   (0x1UL << 0)
 
#define EMU_IFC_VMONAVDDFALL_DEFAULT   (_EMU_IFC_VMONAVDDFALL_DEFAULT << 0)
 
#define EMU_IFC_VMONAVDDRISE   (0x1UL << 1)
 
#define EMU_IFC_VMONAVDDRISE_DEFAULT   (_EMU_IFC_VMONAVDDRISE_DEFAULT << 1)
 
#define EMU_IFC_VMONDVDDFALL   (0x1UL << 4)
 
#define EMU_IFC_VMONDVDDFALL_DEFAULT   (_EMU_IFC_VMONDVDDFALL_DEFAULT << 4)
 
#define EMU_IFC_VMONDVDDRISE   (0x1UL << 5)
 
#define EMU_IFC_VMONDVDDRISE_DEFAULT   (_EMU_IFC_VMONDVDDRISE_DEFAULT << 5)
 
#define EMU_IFC_VMONFVDDFALL   (0x1UL << 14)
 
#define EMU_IFC_VMONFVDDFALL_DEFAULT   (_EMU_IFC_VMONFVDDFALL_DEFAULT << 14)
 
#define EMU_IFC_VMONFVDDRISE   (0x1UL << 15)
 
#define EMU_IFC_VMONFVDDRISE_DEFAULT   (_EMU_IFC_VMONFVDDRISE_DEFAULT << 15)
 
#define EMU_IFC_VMONIO0FALL   (0x1UL << 6)
 
#define EMU_IFC_VMONIO0FALL_DEFAULT   (_EMU_IFC_VMONIO0FALL_DEFAULT << 6)
 
#define EMU_IFC_VMONIO0RISE   (0x1UL << 7)
 
#define EMU_IFC_VMONIO0RISE_DEFAULT   (_EMU_IFC_VMONIO0RISE_DEFAULT << 7)
 
#define EMU_IFC_VSCALEDONE   (0x1UL << 25)
 
#define EMU_IFC_VSCALEDONE_DEFAULT   (_EMU_IFC_VSCALEDONE_DEFAULT << 25)
 
#define EMU_IFS_DCDCINBYPASS   (0x1UL << 20)
 
#define EMU_IFS_DCDCINBYPASS_DEFAULT   (_EMU_IFS_DCDCINBYPASS_DEFAULT << 20)
 
#define EMU_IFS_DCDCLNRUNNING   (0x1UL << 19)
 
#define EMU_IFS_DCDCLNRUNNING_DEFAULT   (_EMU_IFS_DCDCLNRUNNING_DEFAULT << 19)
 
#define EMU_IFS_DCDCLPRUNNING   (0x1UL << 18)
 
#define EMU_IFS_DCDCLPRUNNING_DEFAULT   (_EMU_IFS_DCDCLPRUNNING_DEFAULT << 18)
 
#define EMU_IFS_EM23WAKEUP   (0x1UL << 24)
 
#define EMU_IFS_EM23WAKEUP_DEFAULT   (_EMU_IFS_EM23WAKEUP_DEFAULT << 24)
 
#define EMU_IFS_NFETOVERCURRENTLIMIT   (0x1UL << 17)
 
#define EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT   (_EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT << 17)
 
#define EMU_IFS_PFETOVERCURRENTLIMIT   (0x1UL << 16)
 
#define EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT   (_EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT << 16)
 
#define EMU_IFS_TEMP   (0x1UL << 29)
 
#define EMU_IFS_TEMP_DEFAULT   (_EMU_IFS_TEMP_DEFAULT << 29)
 
#define EMU_IFS_TEMPHIGH   (0x1UL << 31)
 
#define EMU_IFS_TEMPHIGH_DEFAULT   (_EMU_IFS_TEMPHIGH_DEFAULT << 31)
 
#define EMU_IFS_TEMPLOW   (0x1UL << 30)
 
#define EMU_IFS_TEMPLOW_DEFAULT   (_EMU_IFS_TEMPLOW_DEFAULT << 30)
 
#define EMU_IFS_VMONALTAVDDFALL   (0x1UL << 2)
 
#define EMU_IFS_VMONALTAVDDFALL_DEFAULT   (_EMU_IFS_VMONALTAVDDFALL_DEFAULT << 2)
 
#define EMU_IFS_VMONALTAVDDRISE   (0x1UL << 3)
 
#define EMU_IFS_VMONALTAVDDRISE_DEFAULT   (_EMU_IFS_VMONALTAVDDRISE_DEFAULT << 3)
 
#define EMU_IFS_VMONAVDDFALL   (0x1UL << 0)
 
#define EMU_IFS_VMONAVDDFALL_DEFAULT   (_EMU_IFS_VMONAVDDFALL_DEFAULT << 0)
 
#define EMU_IFS_VMONAVDDRISE   (0x1UL << 1)
 
#define EMU_IFS_VMONAVDDRISE_DEFAULT   (_EMU_IFS_VMONAVDDRISE_DEFAULT << 1)
 
#define EMU_IFS_VMONDVDDFALL   (0x1UL << 4)
 
#define EMU_IFS_VMONDVDDFALL_DEFAULT   (_EMU_IFS_VMONDVDDFALL_DEFAULT << 4)
 
#define EMU_IFS_VMONDVDDRISE   (0x1UL << 5)
 
#define EMU_IFS_VMONDVDDRISE_DEFAULT   (_EMU_IFS_VMONDVDDRISE_DEFAULT << 5)
 
#define EMU_IFS_VMONFVDDFALL   (0x1UL << 14)
 
#define EMU_IFS_VMONFVDDFALL_DEFAULT   (_EMU_IFS_VMONFVDDFALL_DEFAULT << 14)
 
#define EMU_IFS_VMONFVDDRISE   (0x1UL << 15)
 
#define EMU_IFS_VMONFVDDRISE_DEFAULT   (_EMU_IFS_VMONFVDDRISE_DEFAULT << 15)
 
#define EMU_IFS_VMONIO0FALL   (0x1UL << 6)
 
#define EMU_IFS_VMONIO0FALL_DEFAULT   (_EMU_IFS_VMONIO0FALL_DEFAULT << 6)
 
#define EMU_IFS_VMONIO0RISE   (0x1UL << 7)
 
#define EMU_IFS_VMONIO0RISE_DEFAULT   (_EMU_IFS_VMONIO0RISE_DEFAULT << 7)
 
#define EMU_IFS_VSCALEDONE   (0x1UL << 25)
 
#define EMU_IFS_VSCALEDONE_DEFAULT   (_EMU_IFS_VSCALEDONE_DEFAULT << 25)
 
#define EMU_LOCK_LOCKKEY_DEFAULT   (_EMU_LOCK_LOCKKEY_DEFAULT << 0)
 
#define EMU_LOCK_LOCKKEY_LOCK   (_EMU_LOCK_LOCKKEY_LOCK << 0)
 
#define EMU_LOCK_LOCKKEY_LOCKED   (_EMU_LOCK_LOCKKEY_LOCKED << 0)
 
#define EMU_LOCK_LOCKKEY_UNLOCK   (_EMU_LOCK_LOCKKEY_UNLOCK << 0)
 
#define EMU_LOCK_LOCKKEY_UNLOCKED   (_EMU_LOCK_LOCKKEY_UNLOCKED << 0)
 
#define EMU_PWRCTRL_ANASW   (0x1UL << 5)
 
#define EMU_PWRCTRL_ANASW_AVDD   (_EMU_PWRCTRL_ANASW_AVDD << 5)
 
#define EMU_PWRCTRL_ANASW_DEFAULT   (_EMU_PWRCTRL_ANASW_DEFAULT << 5)
 
#define EMU_PWRCTRL_ANASW_DVDD   (_EMU_PWRCTRL_ANASW_DVDD << 5)
 
#define EMU_PWRCTRL_IMMEDIATEPWRSWITCH   (0x1UL << 13)
 
#define EMU_PWRCTRL_IMMEDIATEPWRSWITCH_DEFAULT   (_EMU_PWRCTRL_IMMEDIATEPWRSWITCH_DEFAULT << 13)
 
#define EMU_PWRCTRL_REGPWRSEL   (0x1UL << 10)
 
#define EMU_PWRCTRL_REGPWRSEL_AVDD   (_EMU_PWRCTRL_REGPWRSEL_AVDD << 10)
 
#define EMU_PWRCTRL_REGPWRSEL_DEFAULT   (_EMU_PWRCTRL_REGPWRSEL_DEFAULT << 10)
 
#define EMU_PWRCTRL_REGPWRSEL_DVDD   (_EMU_PWRCTRL_REGPWRSEL_DVDD << 10)
 
#define EMU_PWRLOCK_LOCKKEY_DEFAULT   (_EMU_PWRLOCK_LOCKKEY_DEFAULT << 0)
 
#define EMU_PWRLOCK_LOCKKEY_LOCK   (_EMU_PWRLOCK_LOCKKEY_LOCK << 0)
 
#define EMU_PWRLOCK_LOCKKEY_LOCKED   (_EMU_PWRLOCK_LOCKKEY_LOCKED << 0)
 
#define EMU_PWRLOCK_LOCKKEY_UNLOCK   (_EMU_PWRLOCK_LOCKKEY_UNLOCK << 0)
 
#define EMU_PWRLOCK_LOCKKEY_UNLOCKED   (_EMU_PWRLOCK_LOCKKEY_UNLOCKED << 0)
 
#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK   (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK << 0)
 
#define EMU_RAM1CTRL_RAMPOWERDOWN_DEFAULT   (_EMU_RAM1CTRL_RAMPOWERDOWN_DEFAULT << 0)
 
#define EMU_RAM1CTRL_RAMPOWERDOWN_NONE   (_EMU_RAM1CTRL_RAMPOWERDOWN_NONE << 0)
 
#define EMU_RAM2CTRL_RAMPOWERDOWN_BLK   (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK << 0)
 
#define EMU_RAM2CTRL_RAMPOWERDOWN_DEFAULT   (_EMU_RAM2CTRL_RAMPOWERDOWN_DEFAULT << 0)
 
#define EMU_RAM2CTRL_RAMPOWERDOWN_NONE   (_EMU_RAM2CTRL_RAMPOWERDOWN_NONE << 0)
 
#define EMU_STATUS_EM4IORET   (0x1UL << 20)
 
#define EMU_STATUS_EM4IORET_DEFAULT   (_EMU_STATUS_EM4IORET_DEFAULT << 20)
 
#define EMU_STATUS_EM4IORET_DISABLED   (_EMU_STATUS_EM4IORET_DISABLED << 20)
 
#define EMU_STATUS_EM4IORET_ENABLED   (_EMU_STATUS_EM4IORET_ENABLED << 20)
 
#define EMU_STATUS_TEMPACTIVE   (0x1UL << 26)
 
#define EMU_STATUS_TEMPACTIVE_DEFAULT   (_EMU_STATUS_TEMPACTIVE_DEFAULT << 26)
 
#define EMU_STATUS_VMONALTAVDD   (0x1UL << 2)
 
#define EMU_STATUS_VMONALTAVDD_DEFAULT   (_EMU_STATUS_VMONALTAVDD_DEFAULT << 2)
 
#define EMU_STATUS_VMONAVDD   (0x1UL << 1)
 
#define EMU_STATUS_VMONAVDD_DEFAULT   (_EMU_STATUS_VMONAVDD_DEFAULT << 1)
 
#define EMU_STATUS_VMONDVDD   (0x1UL << 3)
 
#define EMU_STATUS_VMONDVDD_DEFAULT   (_EMU_STATUS_VMONDVDD_DEFAULT << 3)
 
#define EMU_STATUS_VMONFVDD   (0x1UL << 8)
 
#define EMU_STATUS_VMONFVDD_DEFAULT   (_EMU_STATUS_VMONFVDD_DEFAULT << 8)
 
#define EMU_STATUS_VMONIO0   (0x1UL << 4)
 
#define EMU_STATUS_VMONIO0_DEFAULT   (_EMU_STATUS_VMONIO0_DEFAULT << 4)
 
#define EMU_STATUS_VMONRDY   (0x1UL << 0)
 
#define EMU_STATUS_VMONRDY_DEFAULT   (_EMU_STATUS_VMONRDY_DEFAULT << 0)
 
#define EMU_STATUS_VSCALE_DEFAULT   (_EMU_STATUS_VSCALE_DEFAULT << 16)
 
#define EMU_STATUS_VSCALE_RESV   (_EMU_STATUS_VSCALE_RESV << 16)
 
#define EMU_STATUS_VSCALE_VSCALE0   (_EMU_STATUS_VSCALE_VSCALE0 << 16)
 
#define EMU_STATUS_VSCALE_VSCALE2   (_EMU_STATUS_VSCALE_VSCALE2 << 16)
 
#define EMU_STATUS_VSCALEBUSY   (0x1UL << 18)
 
#define EMU_STATUS_VSCALEBUSY_DEFAULT   (_EMU_STATUS_VSCALEBUSY_DEFAULT << 18)
 
#define EMU_TEMP_TEMP_DEFAULT   (_EMU_TEMP_TEMP_DEFAULT << 0)
 
#define EMU_TEMPLIMITS_EM4WUEN   (0x1UL << 16)
 
#define EMU_TEMPLIMITS_EM4WUEN_DEFAULT   (_EMU_TEMPLIMITS_EM4WUEN_DEFAULT << 16)
 
#define EMU_TEMPLIMITS_TEMPHIGH_DEFAULT   (_EMU_TEMPLIMITS_TEMPHIGH_DEFAULT << 8)
 
#define EMU_TEMPLIMITS_TEMPLOW_DEFAULT   (_EMU_TEMPLIMITS_TEMPLOW_DEFAULT << 0)
 
#define EMU_VMONALTAVDDCTRL_EN   (0x1UL << 0)
 
#define EMU_VMONALTAVDDCTRL_EN_DEFAULT   (_EMU_VMONALTAVDDCTRL_EN_DEFAULT << 0)
 
#define EMU_VMONALTAVDDCTRL_FALLWU   (0x1UL << 3)
 
#define EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT   (_EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT << 3)
 
#define EMU_VMONALTAVDDCTRL_RISEWU   (0x1UL << 2)
 
#define EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT   (_EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT << 2)
 
#define EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT   (_EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT << 12)
 
#define EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT   (_EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT << 8)
 
#define EMU_VMONAVDDCTRL_EN   (0x1UL << 0)
 
#define EMU_VMONAVDDCTRL_EN_DEFAULT   (_EMU_VMONAVDDCTRL_EN_DEFAULT << 0)
 
#define EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT   (_EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT << 12)
 
#define EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT   (_EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT << 8)
 
#define EMU_VMONAVDDCTRL_FALLWU   (0x1UL << 3)
 
#define EMU_VMONAVDDCTRL_FALLWU_DEFAULT   (_EMU_VMONAVDDCTRL_FALLWU_DEFAULT << 3)
 
#define EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT   (_EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT << 20)
 
#define EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT   (_EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT << 16)
 
#define EMU_VMONAVDDCTRL_RISEWU   (0x1UL << 2)
 
#define EMU_VMONAVDDCTRL_RISEWU_DEFAULT   (_EMU_VMONAVDDCTRL_RISEWU_DEFAULT << 2)
 
#define EMU_VMONDVDDCTRL_EN   (0x1UL << 0)
 
#define EMU_VMONDVDDCTRL_EN_DEFAULT   (_EMU_VMONDVDDCTRL_EN_DEFAULT << 0)
 
#define EMU_VMONDVDDCTRL_FALLWU   (0x1UL << 3)
 
#define EMU_VMONDVDDCTRL_FALLWU_DEFAULT   (_EMU_VMONDVDDCTRL_FALLWU_DEFAULT << 3)
 
#define EMU_VMONDVDDCTRL_RISEWU   (0x1UL << 2)
 
#define EMU_VMONDVDDCTRL_RISEWU_DEFAULT   (_EMU_VMONDVDDCTRL_RISEWU_DEFAULT << 2)
 
#define EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT   (_EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT << 12)
 
#define EMU_VMONDVDDCTRL_THRESFINE_DEFAULT   (_EMU_VMONDVDDCTRL_THRESFINE_DEFAULT << 8)
 
#define EMU_VMONIO0CTRL_EN   (0x1UL << 0)
 
#define EMU_VMONIO0CTRL_EN_DEFAULT   (_EMU_VMONIO0CTRL_EN_DEFAULT << 0)
 
#define EMU_VMONIO0CTRL_FALLWU   (0x1UL << 3)
 
#define EMU_VMONIO0CTRL_FALLWU_DEFAULT   (_EMU_VMONIO0CTRL_FALLWU_DEFAULT << 3)
 
#define EMU_VMONIO0CTRL_RETDIS   (0x1UL << 4)
 
#define EMU_VMONIO0CTRL_RETDIS_DEFAULT   (_EMU_VMONIO0CTRL_RETDIS_DEFAULT << 4)
 
#define EMU_VMONIO0CTRL_RISEWU   (0x1UL << 2)
 
#define EMU_VMONIO0CTRL_RISEWU_DEFAULT   (_EMU_VMONIO0CTRL_RISEWU_DEFAULT << 2)
 
#define EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT   (_EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT << 12)
 
#define EMU_VMONIO0CTRL_THRESFINE_DEFAULT   (_EMU_VMONIO0CTRL_THRESFINE_DEFAULT << 8)
 

Macro Definition Documentation

#define _EMU_CMD_EM01VSCALE0_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_CMD

Definition at line 251 of file efr32fg14p_emu.h.

#define _EMU_CMD_EM01VSCALE0_MASK   0x10UL

Bit mask for EMU_EM01VSCALE0

Definition at line 250 of file efr32fg14p_emu.h.

#define _EMU_CMD_EM01VSCALE0_SHIFT   4

Shift value for EMU_EM01VSCALE0

Definition at line 249 of file efr32fg14p_emu.h.

#define _EMU_CMD_EM01VSCALE2_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_CMD

Definition at line 256 of file efr32fg14p_emu.h.

#define _EMU_CMD_EM01VSCALE2_MASK   0x40UL

Bit mask for EMU_EM01VSCALE2

Definition at line 255 of file efr32fg14p_emu.h.

#define _EMU_CMD_EM01VSCALE2_SHIFT   6

Shift value for EMU_EM01VSCALE2

Definition at line 254 of file efr32fg14p_emu.h.

#define _EMU_CMD_EM4UNLATCH_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_CMD

Definition at line 246 of file efr32fg14p_emu.h.

#define _EMU_CMD_EM4UNLATCH_MASK   0x1UL

Bit mask for EMU_EM4UNLATCH

Definition at line 245 of file efr32fg14p_emu.h.

#define _EMU_CMD_EM4UNLATCH_SHIFT   0

Shift value for EMU_EM4UNLATCH

Definition at line 244 of file efr32fg14p_emu.h.

#define _EMU_CMD_MASK   0x00000051UL

Mask for EMU_CMD

Definition at line 242 of file efr32fg14p_emu.h.

#define _EMU_CMD_RESETVALUE   0x00000000UL

Default value for EMU_CMD

Definition at line 241 of file efr32fg14p_emu.h.

#define _EMU_CTRL_EM01LD_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_CTRL

Definition at line 129 of file efr32fg14p_emu.h.

#define _EMU_CTRL_EM01LD_MASK   0x8UL

Bit mask for EMU_EM01LD

Definition at line 128 of file efr32fg14p_emu.h.

#define _EMU_CTRL_EM01LD_SHIFT   3

Shift value for EMU_EM01LD

Definition at line 127 of file efr32fg14p_emu.h.

#define _EMU_CTRL_EM23VSCALE_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_CTRL

Definition at line 138 of file efr32fg14p_emu.h.

#define _EMU_CTRL_EM23VSCALE_MASK   0x300UL

Bit mask for EMU_EM23VSCALE

Definition at line 137 of file efr32fg14p_emu.h.

Referenced by EMU_EM23Init().

#define _EMU_CTRL_EM23VSCALE_RESV   0x00000003UL

Mode RESV for EMU_CTRL

Definition at line 141 of file efr32fg14p_emu.h.

#define _EMU_CTRL_EM23VSCALE_SHIFT   8

Shift value for EMU_EM23VSCALE

Definition at line 136 of file efr32fg14p_emu.h.

Referenced by EMU_EM23Init().

#define _EMU_CTRL_EM23VSCALE_VSCALE0   0x00000002UL

Mode VSCALE0 for EMU_CTRL

Definition at line 140 of file efr32fg14p_emu.h.

#define _EMU_CTRL_EM23VSCALE_VSCALE2   0x00000000UL

Mode VSCALE2 for EMU_CTRL

Definition at line 139 of file efr32fg14p_emu.h.

#define _EMU_CTRL_EM23VSCALEAUTOWSEN_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_CTRL

Definition at line 134 of file efr32fg14p_emu.h.

#define _EMU_CTRL_EM23VSCALEAUTOWSEN_MASK   0x10UL

Bit mask for EMU_EM23VSCALEAUTOWSEN

Definition at line 133 of file efr32fg14p_emu.h.

#define _EMU_CTRL_EM23VSCALEAUTOWSEN_SHIFT   4

Shift value for EMU_EM23VSCALEAUTOWSEN

Definition at line 132 of file efr32fg14p_emu.h.

#define _EMU_CTRL_EM2BLOCK_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_CTRL

Definition at line 119 of file efr32fg14p_emu.h.

#define _EMU_CTRL_EM2BLOCK_MASK   0x2UL

Bit mask for EMU_EM2BLOCK

Definition at line 118 of file efr32fg14p_emu.h.

#define _EMU_CTRL_EM2BLOCK_SHIFT   1

Shift value for EMU_EM2BLOCK

Definition at line 117 of file efr32fg14p_emu.h.

Referenced by EMU_EM2Block(), and EMU_EM2UnBlock().

#define _EMU_CTRL_EM2BODDIS_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_CTRL

Definition at line 124 of file efr32fg14p_emu.h.

#define _EMU_CTRL_EM2BODDIS_MASK   0x4UL

Bit mask for EMU_EM2BODDIS

Definition at line 123 of file efr32fg14p_emu.h.

#define _EMU_CTRL_EM2BODDIS_SHIFT   2

Shift value for EMU_EM2BODDIS

Definition at line 122 of file efr32fg14p_emu.h.

#define _EMU_CTRL_EM4HVSCALE_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_CTRL

Definition at line 148 of file efr32fg14p_emu.h.

#define _EMU_CTRL_EM4HVSCALE_MASK   0x30000UL

Bit mask for EMU_EM4HVSCALE

Definition at line 147 of file efr32fg14p_emu.h.

Referenced by EMU_EM4Init().

#define _EMU_CTRL_EM4HVSCALE_RESV   0x00000003UL

Mode RESV for EMU_CTRL

Definition at line 151 of file efr32fg14p_emu.h.

#define _EMU_CTRL_EM4HVSCALE_SHIFT   16

Shift value for EMU_EM4HVSCALE

Definition at line 146 of file efr32fg14p_emu.h.

Referenced by EMU_EM4Init().

#define _EMU_CTRL_EM4HVSCALE_VSCALE0   0x00000002UL

Mode VSCALE0 for EMU_CTRL

Definition at line 150 of file efr32fg14p_emu.h.

#define _EMU_CTRL_EM4HVSCALE_VSCALE2   0x00000000UL

Mode VSCALE2 for EMU_CTRL

Definition at line 149 of file efr32fg14p_emu.h.

#define _EMU_CTRL_MASK   0x0003031EUL

Mask for EMU_CTRL

Definition at line 115 of file efr32fg14p_emu.h.

#define _EMU_CTRL_RESETVALUE   0x00000000UL

Default value for EMU_CTRL

Definition at line 114 of file efr32fg14p_emu.h.

#define _EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_DCDCCLIMCTRL

Definition at line 897 of file efr32fg14p_emu.h.

#define _EMU_DCDCCLIMCTRL_BYPLIMEN_MASK   0x2000UL

Bit mask for EMU_BYPLIMEN

Definition at line 896 of file efr32fg14p_emu.h.

#define _EMU_DCDCCLIMCTRL_BYPLIMEN_SHIFT   13

Shift value for EMU_BYPLIMEN

Definition at line 895 of file efr32fg14p_emu.h.

Referenced by CHIP_Init(), and EMU_DCDCModeSet().

#define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT   0x00000001UL

Mode DEFAULT for EMU_DCDCCLIMCTRL

Definition at line 892 of file efr32fg14p_emu.h.

#define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_MASK   0x300UL

Bit mask for EMU_CLIMBLANKDLY

Definition at line 891 of file efr32fg14p_emu.h.

#define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_SHIFT   8

Shift value for EMU_CLIMBLANKDLY

Definition at line 890 of file efr32fg14p_emu.h.

#define _EMU_DCDCCLIMCTRL_MASK   0x00002300UL

Mask for EMU_DCDCCLIMCTRL

Definition at line 889 of file efr32fg14p_emu.h.

#define _EMU_DCDCCLIMCTRL_RESETVALUE   0x00000100UL

Default value for EMU_DCDCCLIMCTRL

Definition at line 888 of file efr32fg14p_emu.h.

#define _EMU_DCDCCTRL_DCDCMODE_BYPASS   0x00000000UL

Mode BYPASS for EMU_DCDCCTRL

Definition at line 790 of file efr32fg14p_emu.h.

#define _EMU_DCDCCTRL_DCDCMODE_DEFAULT   0x00000003UL

Mode DEFAULT for EMU_DCDCCTRL

Definition at line 793 of file efr32fg14p_emu.h.

#define _EMU_DCDCCTRL_DCDCMODE_LOWNOISE   0x00000001UL

Mode LOWNOISE for EMU_DCDCCTRL

Definition at line 791 of file efr32fg14p_emu.h.

#define _EMU_DCDCCTRL_DCDCMODE_LOWPOWER   0x00000002UL

Mode LOWPOWER for EMU_DCDCCTRL

Definition at line 792 of file efr32fg14p_emu.h.

#define _EMU_DCDCCTRL_DCDCMODE_MASK   0x3UL

Bit mask for EMU_DCDCMODE

Definition at line 789 of file efr32fg14p_emu.h.

Referenced by EMU_DCDCConductionModeSet(), EMU_DCDCModeSet(), and EMU_EnterEM4().

#define _EMU_DCDCCTRL_DCDCMODE_OFF   0x00000003UL

Mode OFF for EMU_DCDCCTRL

Definition at line 794 of file efr32fg14p_emu.h.

#define _EMU_DCDCCTRL_DCDCMODE_SHIFT   0

Shift value for EMU_DCDCMODE

Definition at line 788 of file efr32fg14p_emu.h.

#define _EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT   0x00000001UL

Mode DEFAULT for EMU_DCDCCTRL

Definition at line 804 of file efr32fg14p_emu.h.

#define _EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER   0x00000001UL

Mode EM23LOWPOWER for EMU_DCDCCTRL

Definition at line 805 of file efr32fg14p_emu.h.

#define _EMU_DCDCCTRL_DCDCMODEEM23_EM23SW   0x00000000UL

Mode EM23SW for EMU_DCDCCTRL

Definition at line 803 of file efr32fg14p_emu.h.

#define _EMU_DCDCCTRL_DCDCMODEEM23_MASK   0x10UL

Bit mask for EMU_DCDCMODEEM23

Definition at line 802 of file efr32fg14p_emu.h.

#define _EMU_DCDCCTRL_DCDCMODEEM23_SHIFT   4

Shift value for EMU_DCDCMODEEM23

Definition at line 801 of file efr32fg14p_emu.h.

#define _EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT   0x00000001UL

Mode DEFAULT for EMU_DCDCCTRL

Definition at line 813 of file efr32fg14p_emu.h.

#define _EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER   0x00000001UL

Mode EM4LOWPOWER for EMU_DCDCCTRL

Definition at line 814 of file efr32fg14p_emu.h.

#define _EMU_DCDCCTRL_DCDCMODEEM4_EM4SW   0x00000000UL

Mode EM4SW for EMU_DCDCCTRL

Definition at line 812 of file efr32fg14p_emu.h.

#define _EMU_DCDCCTRL_DCDCMODEEM4_MASK   0x20UL

Bit mask for EMU_DCDCMODEEM4

Definition at line 811 of file efr32fg14p_emu.h.

#define _EMU_DCDCCTRL_DCDCMODEEM4_SHIFT   5

Shift value for EMU_DCDCMODEEM4

Definition at line 810 of file efr32fg14p_emu.h.

#define _EMU_DCDCCTRL_MASK   0x00000033UL

Mask for EMU_DCDCCTRL

Definition at line 787 of file efr32fg14p_emu.h.

#define _EMU_DCDCCTRL_RESETVALUE   0x00000033UL

Default value for EMU_DCDCCTRL

Definition at line 786 of file efr32fg14p_emu.h.

#define _EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT   0x00000002UL

Mode DEFAULT for EMU_DCDCLNCOMPCTRL

Definition at line 917 of file efr32fg14p_emu.h.

#define _EMU_DCDCLNCOMPCTRL_COMPENC1_MASK   0x300000UL

Bit mask for EMU_COMPENC1

Definition at line 916 of file efr32fg14p_emu.h.

#define _EMU_DCDCLNCOMPCTRL_COMPENC1_SHIFT   20

Shift value for EMU_COMPENC1

Definition at line 915 of file efr32fg14p_emu.h.

#define _EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT   0x00000007UL

Mode DEFAULT for EMU_DCDCLNCOMPCTRL

Definition at line 921 of file efr32fg14p_emu.h.

#define _EMU_DCDCLNCOMPCTRL_COMPENC2_MASK   0x7000000UL

Bit mask for EMU_COMPENC2

Definition at line 920 of file efr32fg14p_emu.h.

#define _EMU_DCDCLNCOMPCTRL_COMPENC2_SHIFT   24

Shift value for EMU_COMPENC2

Definition at line 919 of file efr32fg14p_emu.h.

#define _EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT   0x00000005UL

Mode DEFAULT for EMU_DCDCLNCOMPCTRL

Definition at line 925 of file efr32fg14p_emu.h.

#define _EMU_DCDCLNCOMPCTRL_COMPENC3_MASK   0xF0000000UL

Bit mask for EMU_COMPENC3

Definition at line 924 of file efr32fg14p_emu.h.

#define _EMU_DCDCLNCOMPCTRL_COMPENC3_SHIFT   28

Shift value for EMU_COMPENC3

Definition at line 923 of file efr32fg14p_emu.h.

#define _EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT   0x00000007UL

Mode DEFAULT for EMU_DCDCLNCOMPCTRL

Definition at line 905 of file efr32fg14p_emu.h.

#define _EMU_DCDCLNCOMPCTRL_COMPENR1_MASK   0x7UL

Bit mask for EMU_COMPENR1

Definition at line 904 of file efr32fg14p_emu.h.

#define _EMU_DCDCLNCOMPCTRL_COMPENR1_SHIFT   0

Shift value for EMU_COMPENR1

Definition at line 903 of file efr32fg14p_emu.h.

#define _EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT   0x00000007UL

Mode DEFAULT for EMU_DCDCLNCOMPCTRL

Definition at line 909 of file efr32fg14p_emu.h.

#define _EMU_DCDCLNCOMPCTRL_COMPENR2_MASK   0x1F0UL

Bit mask for EMU_COMPENR2

Definition at line 908 of file efr32fg14p_emu.h.

#define _EMU_DCDCLNCOMPCTRL_COMPENR2_SHIFT   4

Shift value for EMU_COMPENR2

Definition at line 907 of file efr32fg14p_emu.h.

#define _EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT   0x00000004UL

Mode DEFAULT for EMU_DCDCLNCOMPCTRL

Definition at line 913 of file efr32fg14p_emu.h.

#define _EMU_DCDCLNCOMPCTRL_COMPENR3_MASK   0xF000UL

Bit mask for EMU_COMPENR3

Definition at line 912 of file efr32fg14p_emu.h.

#define _EMU_DCDCLNCOMPCTRL_COMPENR3_SHIFT   12

Shift value for EMU_COMPENR3

Definition at line 911 of file efr32fg14p_emu.h.

#define _EMU_DCDCLNCOMPCTRL_MASK   0xF730F1F7UL

Mask for EMU_DCDCLNCOMPCTRL

Definition at line 902 of file efr32fg14p_emu.h.

#define _EMU_DCDCLNCOMPCTRL_RESETVALUE   0x57204077UL

Default value for EMU_DCDCLNCOMPCTRL

Definition at line 901 of file efr32fg14p_emu.h.

#define _EMU_DCDCLNFREQCTRL_MASK   0x1F000007UL

Mask for EMU_DCDCLNFREQCTRL

Definition at line 981 of file efr32fg14p_emu.h.

#define _EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_DCDCLNFREQCTRL

Definition at line 984 of file efr32fg14p_emu.h.

#define _EMU_DCDCLNFREQCTRL_RCOBAND_MASK   0x7UL

Bit mask for EMU_RCOBAND

Definition at line 983 of file efr32fg14p_emu.h.

Referenced by EMU_DCDCConductionModeSet(), EMU_DCDCLnRcoBandSet(), and EMU_DCDCOptimizeSlice().

#define _EMU_DCDCLNFREQCTRL_RCOBAND_SHIFT   0

Shift value for EMU_RCOBAND

Definition at line 982 of file efr32fg14p_emu.h.

Referenced by EMU_DCDCConductionModeSet(), EMU_DCDCLnRcoBandSet(), and EMU_DCDCOptimizeSlice().

#define _EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT   0x00000010UL

Mode DEFAULT for EMU_DCDCLNFREQCTRL

Definition at line 988 of file efr32fg14p_emu.h.

#define _EMU_DCDCLNFREQCTRL_RCOTRIM_MASK   0x1F000000UL

Bit mask for EMU_RCOTRIM

Definition at line 987 of file efr32fg14p_emu.h.

#define _EMU_DCDCLNFREQCTRL_RCOTRIM_SHIFT   24

Shift value for EMU_RCOTRIM

Definition at line 986 of file efr32fg14p_emu.h.

#define _EMU_DCDCLNFREQCTRL_RESETVALUE   0x10000000UL

Default value for EMU_DCDCLNFREQCTRL

Definition at line 980 of file efr32fg14p_emu.h.

#define _EMU_DCDCLNVCTRL_LNATT_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_DCDCLNVCTRL

Definition at line 934 of file efr32fg14p_emu.h.

#define _EMU_DCDCLNVCTRL_LNATT_DIV3   0x00000000UL

Mode DIV3 for EMU_DCDCLNVCTRL

Definition at line 935 of file efr32fg14p_emu.h.

#define _EMU_DCDCLNVCTRL_LNATT_DIV6   0x00000001UL

Mode DIV6 for EMU_DCDCLNVCTRL

Definition at line 936 of file efr32fg14p_emu.h.

#define _EMU_DCDCLNVCTRL_LNATT_MASK   0x2UL

Bit mask for EMU_LNATT

Definition at line 933 of file efr32fg14p_emu.h.

Referenced by EMU_DCDCOutputVoltageSet().

#define _EMU_DCDCLNVCTRL_LNATT_SHIFT   1

Shift value for EMU_LNATT

Definition at line 932 of file efr32fg14p_emu.h.

#define _EMU_DCDCLNVCTRL_LNVREF_DEFAULT   0x00000071UL

Mode DEFAULT for EMU_DCDCLNVCTRL

Definition at line 942 of file efr32fg14p_emu.h.

#define _EMU_DCDCLNVCTRL_LNVREF_MASK   0x7F00UL

Bit mask for EMU_LNVREF

Definition at line 941 of file efr32fg14p_emu.h.

Referenced by EMU_DCDCOutputVoltageSet().

#define _EMU_DCDCLNVCTRL_LNVREF_SHIFT   8

Shift value for EMU_LNVREF

Definition at line 940 of file efr32fg14p_emu.h.

Referenced by EMU_DCDCOutputVoltageSet().

#define _EMU_DCDCLNVCTRL_MASK   0x00007F02UL

Mask for EMU_DCDCLNVCTRL

Definition at line 930 of file efr32fg14p_emu.h.

#define _EMU_DCDCLNVCTRL_RESETVALUE   0x00007100UL

Default value for EMU_DCDCLNVCTRL

Definition at line 929 of file efr32fg14p_emu.h.

#define _EMU_DCDCLPCTRL_LPBLANK_DEFAULT   0x00000001UL

Mode DEFAULT for EMU_DCDCLPCTRL

Definition at line 976 of file efr32fg14p_emu.h.

#define _EMU_DCDCLPCTRL_LPBLANK_MASK   0x6000000UL

Bit mask for EMU_LPBLANK

Definition at line 975 of file efr32fg14p_emu.h.

#define _EMU_DCDCLPCTRL_LPBLANK_SHIFT   25

Shift value for EMU_LPBLANK

Definition at line 974 of file efr32fg14p_emu.h.

#define _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_DCDCLPCTRL

Definition at line 967 of file efr32fg14p_emu.h.

#define _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_MASK   0xF000UL

Bit mask for EMU_LPCMPHYSSELEM234H

Definition at line 966 of file efr32fg14p_emu.h.

#define _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_SHIFT   12

Shift value for EMU_LPCMPHYSSELEM234H

Definition at line 965 of file efr32fg14p_emu.h.

#define _EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT   0x00000001UL

Mode DEFAULT for EMU_DCDCLPCTRL

Definition at line 972 of file efr32fg14p_emu.h.

#define _EMU_DCDCLPCTRL_LPVREFDUTYEN_MASK   0x1000000UL

Bit mask for EMU_LPVREFDUTYEN

Definition at line 971 of file efr32fg14p_emu.h.

#define _EMU_DCDCLPCTRL_LPVREFDUTYEN_SHIFT   24

Shift value for EMU_LPVREFDUTYEN

Definition at line 970 of file efr32fg14p_emu.h.

#define _EMU_DCDCLPCTRL_MASK   0x0700F000UL

Mask for EMU_DCDCLPCTRL

Definition at line 964 of file efr32fg14p_emu.h.

#define _EMU_DCDCLPCTRL_RESETVALUE   0x03000000UL

Default value for EMU_DCDCLPCTRL

Definition at line 963 of file efr32fg14p_emu.h.

#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS0   0x00000000UL

Mode BIAS0 for EMU_DCDCLPEM01CFG

Definition at line 1150 of file efr32fg14p_emu.h.

#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS1   0x00000001UL

Mode BIAS1 for EMU_DCDCLPEM01CFG

Definition at line 1151 of file efr32fg14p_emu.h.

#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS2   0x00000002UL

Mode BIAS2 for EMU_DCDCLPEM01CFG

Definition at line 1152 of file efr32fg14p_emu.h.

#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3   0x00000003UL

Mode BIAS3 for EMU_DCDCLPEM01CFG

Definition at line 1154 of file efr32fg14p_emu.h.

#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_DEFAULT   0x00000003UL

Mode DEFAULT for EMU_DCDCLPEM01CFG

Definition at line 1153 of file efr32fg14p_emu.h.

#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK   0x300UL

Bit mask for EMU_LPCMPBIASEM01

Definition at line 1149 of file efr32fg14p_emu.h.

Referenced by EMU_DCDCInit(), and EMU_DCDCOutputVoltageSet().

#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_SHIFT   8

Shift value for EMU_LPCMPBIASEM01

Definition at line 1148 of file efr32fg14p_emu.h.

Referenced by EMU_DCDCOutputVoltageSet().

#define _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_DCDCLPEM01CFG

Definition at line 1162 of file efr32fg14p_emu.h.

#define _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_MASK   0xF000UL

Bit mask for EMU_LPCMPHYSSELEM01

Definition at line 1161 of file efr32fg14p_emu.h.

#define _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_SHIFT   12

Shift value for EMU_LPCMPHYSSELEM01

Definition at line 1160 of file efr32fg14p_emu.h.

#define _EMU_DCDCLPEM01CFG_MASK   0x0000F300UL

Mask for EMU_DCDCLPEM01CFG

Definition at line 1147 of file efr32fg14p_emu.h.

#define _EMU_DCDCLPEM01CFG_RESETVALUE   0x00000300UL

Default value for EMU_DCDCLPEM01CFG

Definition at line 1146 of file efr32fg14p_emu.h.

#define _EMU_DCDCLPVCTRL_LPATT_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_DCDCLPVCTRL

Definition at line 951 of file efr32fg14p_emu.h.

#define _EMU_DCDCLPVCTRL_LPATT_DIV4   0x00000000UL

Mode DIV4 for EMU_DCDCLPVCTRL

Definition at line 952 of file efr32fg14p_emu.h.

#define _EMU_DCDCLPVCTRL_LPATT_DIV8   0x00000001UL

Mode DIV8 for EMU_DCDCLPVCTRL

Definition at line 953 of file efr32fg14p_emu.h.

#define _EMU_DCDCLPVCTRL_LPATT_MASK   0x1UL

Bit mask for EMU_LPATT

Definition at line 950 of file efr32fg14p_emu.h.

Referenced by EMU_DCDCOutputVoltageSet().

#define _EMU_DCDCLPVCTRL_LPATT_SHIFT   0

Shift value for EMU_LPATT

Definition at line 949 of file efr32fg14p_emu.h.

#define _EMU_DCDCLPVCTRL_LPVREF_DEFAULT   0x000000B4UL

Mode DEFAULT for EMU_DCDCLPVCTRL

Definition at line 959 of file efr32fg14p_emu.h.

#define _EMU_DCDCLPVCTRL_LPVREF_MASK   0x1FEUL

Bit mask for EMU_LPVREF

Definition at line 958 of file efr32fg14p_emu.h.

Referenced by EMU_DCDCOutputVoltageSet().

#define _EMU_DCDCLPVCTRL_LPVREF_SHIFT   1

Shift value for EMU_LPVREF

Definition at line 957 of file efr32fg14p_emu.h.

Referenced by EMU_DCDCOutputVoltageSet().

#define _EMU_DCDCLPVCTRL_MASK   0x000001FFUL

Mask for EMU_DCDCLPVCTRL

Definition at line 947 of file efr32fg14p_emu.h.

#define _EMU_DCDCLPVCTRL_RESETVALUE   0x00000168UL

Default value for EMU_DCDCLPVCTRL

Definition at line 946 of file efr32fg14p_emu.h.

#define _EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_DCDCMISCCTRL

Definition at line 852 of file efr32fg14p_emu.h.

#define _EMU_DCDCMISCCTRL_BYPLIMSEL_MASK   0xF0000UL

Bit mask for EMU_BYPLIMSEL

Definition at line 851 of file efr32fg14p_emu.h.

#define _EMU_DCDCMISCCTRL_BYPLIMSEL_SHIFT   16

Shift value for EMU_BYPLIMSEL

Definition at line 850 of file efr32fg14p_emu.h.

#define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT   0x00000003UL

Mode DEFAULT for EMU_DCDCMISCCTRL

Definition at line 860 of file efr32fg14p_emu.h.

#define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_MASK   0x7000000UL

Bit mask for EMU_LNCLIMILIMSEL

Definition at line 859 of file efr32fg14p_emu.h.

#define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_SHIFT   24

Shift value for EMU_LNCLIMILIMSEL

Definition at line 858 of file efr32fg14p_emu.h.

#define _EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_DCDCMISCCTRL

Definition at line 825 of file efr32fg14p_emu.h.

#define _EMU_DCDCMISCCTRL_LNFORCECCM_MASK   0x1UL

Bit mask for EMU_LNFORCECCM

Definition at line 824 of file efr32fg14p_emu.h.

Referenced by EMU_DCDCInit(), and EMU_DCDCOptimizeSlice().

#define _EMU_DCDCMISCCTRL_LNFORCECCM_SHIFT   0

Shift value for EMU_LNFORCECCM

Definition at line 823 of file efr32fg14p_emu.h.

Referenced by EMU_DCDCLnRcoBandSet().

#define _EMU_DCDCMISCCTRL_LNFORCECCMIMM_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_DCDCMISCCTRL

Definition at line 840 of file efr32fg14p_emu.h.

#define _EMU_DCDCMISCCTRL_LNFORCECCMIMM_MASK   0x20UL

Bit mask for EMU_LNFORCECCMIMM

Definition at line 839 of file efr32fg14p_emu.h.

#define _EMU_DCDCMISCCTRL_LNFORCECCMIMM_SHIFT   5

Shift value for EMU_LNFORCECCMIMM

Definition at line 838 of file efr32fg14p_emu.h.

#define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT   0x00000001UL

Mode DEFAULT for EMU_DCDCMISCCTRL

Definition at line 856 of file efr32fg14p_emu.h.

#define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_MASK   0x700000UL

Bit mask for EMU_LPCLIMILIMSEL

Definition at line 855 of file efr32fg14p_emu.h.

#define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_SHIFT   20

Shift value for EMU_LPCLIMILIMSEL

Definition at line 854 of file efr32fg14p_emu.h.

#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS0   0x00000000UL

Mode BIAS0 for EMU_DCDCMISCCTRL

Definition at line 865 of file efr32fg14p_emu.h.

#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS1   0x00000001UL

Mode BIAS1 for EMU_DCDCMISCCTRL

Definition at line 866 of file efr32fg14p_emu.h.

#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS2   0x00000002UL

Mode BIAS2 for EMU_DCDCMISCCTRL

Definition at line 867 of file efr32fg14p_emu.h.

#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS3   0x00000003UL

Mode BIAS3 for EMU_DCDCMISCCTRL

Definition at line 868 of file efr32fg14p_emu.h.

#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_DCDCMISCCTRL

Definition at line 864 of file efr32fg14p_emu.h.

#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_MASK   0x30000000UL

Bit mask for EMU_LPCMPBIASEM234H

Definition at line 863 of file efr32fg14p_emu.h.

#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_SHIFT   28

Shift value for EMU_LPCMPBIASEM234H

Definition at line 862 of file efr32fg14p_emu.h.

#define _EMU_DCDCMISCCTRL_LPCMPHYSDIS_DEFAULT   0x00000001UL

Mode DEFAULT for EMU_DCDCMISCCTRL

Definition at line 830 of file efr32fg14p_emu.h.

#define _EMU_DCDCMISCCTRL_LPCMPHYSDIS_MASK   0x2UL

Bit mask for EMU_LPCMPHYSDIS

Definition at line 829 of file efr32fg14p_emu.h.

#define _EMU_DCDCMISCCTRL_LPCMPHYSDIS_SHIFT   1

Shift value for EMU_LPCMPHYSDIS

Definition at line 828 of file efr32fg14p_emu.h.

#define _EMU_DCDCMISCCTRL_LPCMPHYSHI_DEFAULT   0x00000001UL

Mode DEFAULT for EMU_DCDCMISCCTRL

Definition at line 835 of file efr32fg14p_emu.h.

#define _EMU_DCDCMISCCTRL_LPCMPHYSHI_MASK   0x4UL

Bit mask for EMU_LPCMPHYSHI

Definition at line 834 of file efr32fg14p_emu.h.

#define _EMU_DCDCMISCCTRL_LPCMPHYSHI_SHIFT   2

Shift value for EMU_LPCMPHYSHI

Definition at line 833 of file efr32fg14p_emu.h.

#define _EMU_DCDCMISCCTRL_MASK   0x377FFF27UL

Mask for EMU_DCDCMISCCTRL

Definition at line 821 of file efr32fg14p_emu.h.

#define _EMU_DCDCMISCCTRL_NFETCNT_DEFAULT   0x00000007UL

Mode DEFAULT for EMU_DCDCMISCCTRL

Definition at line 848 of file efr32fg14p_emu.h.

#define _EMU_DCDCMISCCTRL_NFETCNT_MASK   0xF000UL

Bit mask for EMU_NFETCNT

Definition at line 847 of file efr32fg14p_emu.h.

Referenced by EMU_DCDCOptimizeSlice().

#define _EMU_DCDCMISCCTRL_NFETCNT_SHIFT   12

Shift value for EMU_NFETCNT

Definition at line 846 of file efr32fg14p_emu.h.

Referenced by EMU_DCDCOptimizeSlice().

#define _EMU_DCDCMISCCTRL_PFETCNT_DEFAULT   0x00000007UL

Mode DEFAULT for EMU_DCDCMISCCTRL

Definition at line 844 of file efr32fg14p_emu.h.

#define _EMU_DCDCMISCCTRL_PFETCNT_MASK   0xF00UL

Bit mask for EMU_PFETCNT

Definition at line 843 of file efr32fg14p_emu.h.

Referenced by EMU_DCDCOptimizeSlice().

#define _EMU_DCDCMISCCTRL_PFETCNT_SHIFT   8

Shift value for EMU_PFETCNT

Definition at line 842 of file efr32fg14p_emu.h.

Referenced by EMU_DCDCOptimizeSlice().

#define _EMU_DCDCMISCCTRL_RESETVALUE   0x03107706UL

Default value for EMU_DCDCMISCCTRL

Definition at line 820 of file efr32fg14p_emu.h.

#define _EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_DCDCSYNC

Definition at line 997 of file efr32fg14p_emu.h.

#define _EMU_DCDCSYNC_DCDCCTRLBUSY_MASK   0x1UL

Bit mask for EMU_DCDCCTRLBUSY

Definition at line 996 of file efr32fg14p_emu.h.

#define _EMU_DCDCSYNC_DCDCCTRLBUSY_SHIFT   0

Shift value for EMU_DCDCCTRLBUSY

Definition at line 995 of file efr32fg14p_emu.h.

#define _EMU_DCDCSYNC_MASK   0x00000001UL

Mask for EMU_DCDCSYNC

Definition at line 993 of file efr32fg14p_emu.h.

#define _EMU_DCDCSYNC_RESETVALUE   0x00000000UL

Default value for EMU_DCDCSYNC

Definition at line 992 of file efr32fg14p_emu.h.

#define _EMU_DCDCZDETCTRL_MASK   0x00000370UL

Mask for EMU_DCDCZDETCTRL

Definition at line 877 of file efr32fg14p_emu.h.

#define _EMU_DCDCZDETCTRL_RESETVALUE   0x00000150UL

Default value for EMU_DCDCZDETCTRL

Definition at line 876 of file efr32fg14p_emu.h.

#define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT   0x00000001UL

Mode DEFAULT for EMU_DCDCZDETCTRL

Definition at line 884 of file efr32fg14p_emu.h.

#define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_MASK   0x300UL

Bit mask for EMU_ZDETBLANKDLY

Definition at line 883 of file efr32fg14p_emu.h.

#define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_SHIFT   8

Shift value for EMU_ZDETBLANKDLY

Definition at line 882 of file efr32fg14p_emu.h.

#define _EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT   0x00000005UL

Mode DEFAULT for EMU_DCDCZDETCTRL

Definition at line 880 of file efr32fg14p_emu.h.

#define _EMU_DCDCZDETCTRL_ZDETILIMSEL_MASK   0x70UL

Bit mask for EMU_ZDETILIMSEL

Definition at line 879 of file efr32fg14p_emu.h.

#define _EMU_DCDCZDETCTRL_ZDETILIMSEL_SHIFT   4

Shift value for EMU_ZDETILIMSEL

Definition at line 878 of file efr32fg14p_emu.h.

#define _EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_EM23PERNORETAINCMD

Definition at line 1171 of file efr32fg14p_emu.h.

#define _EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_MASK   0x1UL

Bit mask for EMU_ACMP0UNLOCK

Definition at line 1170 of file efr32fg14p_emu.h.

#define _EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_SHIFT   0

Shift value for EMU_ACMP0UNLOCK

Definition at line 1169 of file efr32fg14p_emu.h.

#define _EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_EM23PERNORETAINCMD

Definition at line 1176 of file efr32fg14p_emu.h.

#define _EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_MASK   0x2UL

Bit mask for EMU_ACMP1UNLOCK

Definition at line 1175 of file efr32fg14p_emu.h.

#define _EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_SHIFT   1

Shift value for EMU_ACMP1UNLOCK

Definition at line 1174 of file efr32fg14p_emu.h.

#define _EMU_EM23PERNORETAINCMD_ADC0UNLOCK_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_EM23PERNORETAINCMD

Definition at line 1201 of file efr32fg14p_emu.h.

#define _EMU_EM23PERNORETAINCMD_ADC0UNLOCK_MASK   0x200UL

Bit mask for EMU_ADC0UNLOCK

Definition at line 1200 of file efr32fg14p_emu.h.

#define _EMU_EM23PERNORETAINCMD_ADC0UNLOCK_SHIFT   9

Shift value for EMU_ADC0UNLOCK

Definition at line 1199 of file efr32fg14p_emu.h.

#define _EMU_EM23PERNORETAINCMD_DAC0UNLOCK_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_EM23PERNORETAINCMD

Definition at line 1191 of file efr32fg14p_emu.h.

#define _EMU_EM23PERNORETAINCMD_DAC0UNLOCK_MASK   0x80UL

Bit mask for EMU_DAC0UNLOCK

Definition at line 1190 of file efr32fg14p_emu.h.

#define _EMU_EM23PERNORETAINCMD_DAC0UNLOCK_SHIFT   7

Shift value for EMU_DAC0UNLOCK

Definition at line 1189 of file efr32fg14p_emu.h.

#define _EMU_EM23PERNORETAINCMD_I2C0UNLOCK_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_EM23PERNORETAINCMD

Definition at line 1186 of file efr32fg14p_emu.h.

#define _EMU_EM23PERNORETAINCMD_I2C0UNLOCK_MASK   0x20UL

Bit mask for EMU_I2C0UNLOCK

Definition at line 1185 of file efr32fg14p_emu.h.

#define _EMU_EM23PERNORETAINCMD_I2C0UNLOCK_SHIFT   5

Shift value for EMU_I2C0UNLOCK

Definition at line 1184 of file efr32fg14p_emu.h.

#define _EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_EM23PERNORETAINCMD

Definition at line 1196 of file efr32fg14p_emu.h.

#define _EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_MASK   0x100UL

Bit mask for EMU_IDAC0UNLOCK

Definition at line 1195 of file efr32fg14p_emu.h.

#define _EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_SHIFT   8

Shift value for EMU_IDAC0UNLOCK

Definition at line 1194 of file efr32fg14p_emu.h.

#define _EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_EM23PERNORETAINCMD

Definition at line 1221 of file efr32fg14p_emu.h.

#define _EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_MASK   0x2000UL

Bit mask for EMU_LESENSE0UNLOCK

Definition at line 1220 of file efr32fg14p_emu.h.

#define _EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_SHIFT   13

Shift value for EMU_LESENSE0UNLOCK

Definition at line 1219 of file efr32fg14p_emu.h.

#define _EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_EM23PERNORETAINCMD

Definition at line 1206 of file efr32fg14p_emu.h.

#define _EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_MASK   0x400UL

Bit mask for EMU_LETIMER0UNLOCK

Definition at line 1205 of file efr32fg14p_emu.h.

#define _EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_SHIFT   10

Shift value for EMU_LETIMER0UNLOCK

Definition at line 1204 of file efr32fg14p_emu.h.

#define _EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_EM23PERNORETAINCMD

Definition at line 1226 of file efr32fg14p_emu.h.

#define _EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_MASK   0x8000UL

Bit mask for EMU_LEUART0UNLOCK

Definition at line 1225 of file efr32fg14p_emu.h.

#define _EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_SHIFT   15

Shift value for EMU_LEUART0UNLOCK

Definition at line 1224 of file efr32fg14p_emu.h.

#define _EMU_EM23PERNORETAINCMD_MASK   0x0000BFA7UL

Mask for EMU_EM23PERNORETAINCMD

Definition at line 1167 of file efr32fg14p_emu.h.

#define _EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_EM23PERNORETAINCMD

Definition at line 1181 of file efr32fg14p_emu.h.

#define _EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_MASK   0x4UL

Bit mask for EMU_PCNT0UNLOCK

Definition at line 1180 of file efr32fg14p_emu.h.

#define _EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_SHIFT   2

Shift value for EMU_PCNT0UNLOCK

Definition at line 1179 of file efr32fg14p_emu.h.

#define _EMU_EM23PERNORETAINCMD_RESETVALUE   0x00000000UL

Default value for EMU_EM23PERNORETAINCMD

Definition at line 1166 of file efr32fg14p_emu.h.

#define _EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_EM23PERNORETAINCMD

Definition at line 1211 of file efr32fg14p_emu.h.

#define _EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_MASK   0x800UL

Bit mask for EMU_WDOG0UNLOCK

Definition at line 1210 of file efr32fg14p_emu.h.

#define _EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_SHIFT   11

Shift value for EMU_WDOG0UNLOCK

Definition at line 1209 of file efr32fg14p_emu.h.

#define _EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_EM23PERNORETAINCMD

Definition at line 1216 of file efr32fg14p_emu.h.

#define _EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_MASK   0x1000UL

Bit mask for EMU_WDOG1UNLOCK

Definition at line 1215 of file efr32fg14p_emu.h.

#define _EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_SHIFT   12

Shift value for EMU_WDOG1UNLOCK

Definition at line 1214 of file efr32fg14p_emu.h.

#define _EMU_EM23PERNORETAINCTRL_ACMP0DIS_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_EM23PERNORETAINCTRL

Definition at line 1299 of file efr32fg14p_emu.h.

#define _EMU_EM23PERNORETAINCTRL_ACMP0DIS_MASK   0x1UL

Bit mask for EMU_ACMP0DIS

Definition at line 1298 of file efr32fg14p_emu.h.

#define _EMU_EM23PERNORETAINCTRL_ACMP0DIS_SHIFT   0

Shift value for EMU_ACMP0DIS

Definition at line 1297 of file efr32fg14p_emu.h.

#define _EMU_EM23PERNORETAINCTRL_ACMP1DIS_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_EM23PERNORETAINCTRL

Definition at line 1304 of file efr32fg14p_emu.h.

#define _EMU_EM23PERNORETAINCTRL_ACMP1DIS_MASK   0x2UL

Bit mask for EMU_ACMP1DIS

Definition at line 1303 of file efr32fg14p_emu.h.

#define _EMU_EM23PERNORETAINCTRL_ACMP1DIS_SHIFT   1

Shift value for EMU_ACMP1DIS

Definition at line 1302 of file efr32fg14p_emu.h.

#define _EMU_EM23PERNORETAINCTRL_ADC0DIS_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_EM23PERNORETAINCTRL

Definition at line 1329 of file efr32fg14p_emu.h.

#define _EMU_EM23PERNORETAINCTRL_ADC0DIS_MASK   0x200UL

Bit mask for EMU_ADC0DIS

Definition at line 1328 of file efr32fg14p_emu.h.

#define _EMU_EM23PERNORETAINCTRL_ADC0DIS_SHIFT   9

Shift value for EMU_ADC0DIS

Definition at line 1327 of file efr32fg14p_emu.h.

#define _EMU_EM23PERNORETAINCTRL_DAC0DIS_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_EM23PERNORETAINCTRL

Definition at line 1319 of file efr32fg14p_emu.h.

#define _EMU_EM23PERNORETAINCTRL_DAC0DIS_MASK   0x80UL

Bit mask for EMU_DAC0DIS

Definition at line 1318 of file efr32fg14p_emu.h.

#define _EMU_EM23PERNORETAINCTRL_DAC0DIS_SHIFT   7

Shift value for EMU_DAC0DIS

Definition at line 1317 of file efr32fg14p_emu.h.

#define _EMU_EM23PERNORETAINCTRL_I2C0DIS_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_EM23PERNORETAINCTRL

Definition at line 1314 of file efr32fg14p_emu.h.

#define _EMU_EM23PERNORETAINCTRL_I2C0DIS_MASK   0x20UL

Bit mask for EMU_I2C0DIS

Definition at line 1313 of file efr32fg14p_emu.h.

#define _EMU_EM23PERNORETAINCTRL_I2C0DIS_SHIFT   5

Shift value for EMU_I2C0DIS

Definition at line 1312 of file efr32fg14p_emu.h.

#define _EMU_EM23PERNORETAINCTRL_IDAC0DIS_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_EM23PERNORETAINCTRL

Definition at line 1324 of file efr32fg14p_emu.h.

#define _EMU_EM23PERNORETAINCTRL_IDAC0DIS_MASK   0x100UL

Bit mask for EMU_IDAC0DIS

Definition at line 1323 of file efr32fg14p_emu.h.

#define _EMU_EM23PERNORETAINCTRL_IDAC0DIS_SHIFT   8

Shift value for EMU_IDAC0DIS

Definition at line 1322 of file efr32fg14p_emu.h.

#define _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_EM23PERNORETAINCTRL

Definition at line 1349 of file efr32fg14p_emu.h.

#define _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_MASK   0x2000UL

Bit mask for EMU_LESENSE0DIS

Definition at line 1348 of file efr32fg14p_emu.h.

#define _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_SHIFT   13

Shift value for EMU_LESENSE0DIS

Definition at line 1347 of file efr32fg14p_emu.h.

#define _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_EM23PERNORETAINCTRL

Definition at line 1334 of file efr32fg14p_emu.h.

#define _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_MASK   0x400UL

Bit mask for EMU_LETIMER0DIS

Definition at line 1333 of file efr32fg14p_emu.h.

#define _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_SHIFT   10

Shift value for EMU_LETIMER0DIS

Definition at line 1332 of file efr32fg14p_emu.h.

#define _EMU_EM23PERNORETAINCTRL_LEUART0DIS_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_EM23PERNORETAINCTRL

Definition at line 1354 of file efr32fg14p_emu.h.

#define _EMU_EM23PERNORETAINCTRL_LEUART0DIS_MASK   0x8000UL

Bit mask for EMU_LEUART0DIS

Definition at line 1353 of file efr32fg14p_emu.h.

#define _EMU_EM23PERNORETAINCTRL_LEUART0DIS_SHIFT   15

Shift value for EMU_LEUART0DIS

Definition at line 1352 of file efr32fg14p_emu.h.

#define _EMU_EM23PERNORETAINCTRL_MASK   0x0000BFA7UL

Mask for EMU_EM23PERNORETAINCTRL

Definition at line 1295 of file efr32fg14p_emu.h.

#define _EMU_EM23PERNORETAINCTRL_PCNT0DIS_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_EM23PERNORETAINCTRL

Definition at line 1309 of file efr32fg14p_emu.h.

#define _EMU_EM23PERNORETAINCTRL_PCNT0DIS_MASK   0x4UL

Bit mask for EMU_PCNT0DIS

Definition at line 1308 of file efr32fg14p_emu.h.

#define _EMU_EM23PERNORETAINCTRL_PCNT0DIS_SHIFT   2

Shift value for EMU_PCNT0DIS

Definition at line 1307 of file efr32fg14p_emu.h.

#define _EMU_EM23PERNORETAINCTRL_RESETVALUE   0x00000000UL

Default value for EMU_EM23PERNORETAINCTRL

Definition at line 1294 of file efr32fg14p_emu.h.

#define _EMU_EM23PERNORETAINCTRL_WDOG0DIS_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_EM23PERNORETAINCTRL

Definition at line 1339 of file efr32fg14p_emu.h.

#define _EMU_EM23PERNORETAINCTRL_WDOG0DIS_MASK   0x800UL

Bit mask for EMU_WDOG0DIS

Definition at line 1338 of file efr32fg14p_emu.h.

#define _EMU_EM23PERNORETAINCTRL_WDOG0DIS_SHIFT   11

Shift value for EMU_WDOG0DIS

Definition at line 1337 of file efr32fg14p_emu.h.

#define _EMU_EM23PERNORETAINCTRL_WDOG1DIS_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_EM23PERNORETAINCTRL

Definition at line 1344 of file efr32fg14p_emu.h.

#define _EMU_EM23PERNORETAINCTRL_WDOG1DIS_MASK   0x1000UL

Bit mask for EMU_WDOG1DIS

Definition at line 1343 of file efr32fg14p_emu.h.

#define _EMU_EM23PERNORETAINCTRL_WDOG1DIS_SHIFT   12

Shift value for EMU_WDOG1DIS

Definition at line 1342 of file efr32fg14p_emu.h.

#define _EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_EM23PERNORETAINSTATUS

Definition at line 1235 of file efr32fg14p_emu.h.

#define _EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_MASK   0x1UL

Bit mask for EMU_ACMP0LOCKED

Definition at line 1234 of file efr32fg14p_emu.h.

#define _EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_SHIFT   0

Shift value for EMU_ACMP0LOCKED

Definition at line 1233 of file efr32fg14p_emu.h.

#define _EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_EM23PERNORETAINSTATUS

Definition at line 1240 of file efr32fg14p_emu.h.

#define _EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_MASK   0x2UL

Bit mask for EMU_ACMP1LOCKED

Definition at line 1239 of file efr32fg14p_emu.h.

#define _EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_SHIFT   1

Shift value for EMU_ACMP1LOCKED

Definition at line 1238 of file efr32fg14p_emu.h.

#define _EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_EM23PERNORETAINSTATUS

Definition at line 1265 of file efr32fg14p_emu.h.

#define _EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_MASK   0x200UL

Bit mask for EMU_ADC0LOCKED

Definition at line 1264 of file efr32fg14p_emu.h.

#define _EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_SHIFT   9

Shift value for EMU_ADC0LOCKED

Definition at line 1263 of file efr32fg14p_emu.h.

#define _EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_EM23PERNORETAINSTATUS

Definition at line 1255 of file efr32fg14p_emu.h.

#define _EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_MASK   0x80UL

Bit mask for EMU_DAC0LOCKED

Definition at line 1254 of file efr32fg14p_emu.h.

#define _EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_SHIFT   7

Shift value for EMU_DAC0LOCKED

Definition at line 1253 of file efr32fg14p_emu.h.

#define _EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_EM23PERNORETAINSTATUS

Definition at line 1250 of file efr32fg14p_emu.h.

#define _EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_MASK   0x20UL

Bit mask for EMU_I2C0LOCKED

Definition at line 1249 of file efr32fg14p_emu.h.

#define _EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_SHIFT   5

Shift value for EMU_I2C0LOCKED

Definition at line 1248 of file efr32fg14p_emu.h.

#define _EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_EM23PERNORETAINSTATUS

Definition at line 1260 of file efr32fg14p_emu.h.

#define _EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_MASK   0x100UL

Bit mask for EMU_IDAC0LOCKED

Definition at line 1259 of file efr32fg14p_emu.h.

#define _EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_SHIFT   8

Shift value for EMU_IDAC0LOCKED

Definition at line 1258 of file efr32fg14p_emu.h.

#define _EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_EM23PERNORETAINSTATUS

Definition at line 1285 of file efr32fg14p_emu.h.

#define _EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_MASK   0x2000UL

Bit mask for EMU_LESENSE0LOCKED

Definition at line 1284 of file efr32fg14p_emu.h.

#define _EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_SHIFT   13

Shift value for EMU_LESENSE0LOCKED

Definition at line 1283 of file efr32fg14p_emu.h.

#define _EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_EM23PERNORETAINSTATUS

Definition at line 1270 of file efr32fg14p_emu.h.

#define _EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_MASK   0x400UL

Bit mask for EMU_LETIMER0LOCKED

Definition at line 1269 of file efr32fg14p_emu.h.

#define _EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_SHIFT   10

Shift value for EMU_LETIMER0LOCKED

Definition at line 1268 of file efr32fg14p_emu.h.

#define _EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_EM23PERNORETAINSTATUS

Definition at line 1290 of file efr32fg14p_emu.h.

#define _EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_MASK   0x8000UL

Bit mask for EMU_LEUART0LOCKED

Definition at line 1289 of file efr32fg14p_emu.h.

#define _EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_SHIFT   15

Shift value for EMU_LEUART0LOCKED

Definition at line 1288 of file efr32fg14p_emu.h.

#define _EMU_EM23PERNORETAINSTATUS_MASK   0x0000BFA7UL

Mask for EMU_EM23PERNORETAINSTATUS

Definition at line 1231 of file efr32fg14p_emu.h.

#define _EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_EM23PERNORETAINSTATUS

Definition at line 1245 of file efr32fg14p_emu.h.

#define _EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_MASK   0x4UL

Bit mask for EMU_PCNT0LOCKED

Definition at line 1244 of file efr32fg14p_emu.h.

#define _EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_SHIFT   2

Shift value for EMU_PCNT0LOCKED

Definition at line 1243 of file efr32fg14p_emu.h.

#define _EMU_EM23PERNORETAINSTATUS_RESETVALUE   0x00000000UL

Default value for EMU_EM23PERNORETAINSTATUS

Definition at line 1230 of file efr32fg14p_emu.h.

#define _EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_EM23PERNORETAINSTATUS

Definition at line 1275 of file efr32fg14p_emu.h.

#define _EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_MASK   0x800UL

Bit mask for EMU_WDOG0LOCKED

Definition at line 1274 of file efr32fg14p_emu.h.

#define _EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_SHIFT   11

Shift value for EMU_WDOG0LOCKED

Definition at line 1273 of file efr32fg14p_emu.h.

#define _EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_EM23PERNORETAINSTATUS

Definition at line 1280 of file efr32fg14p_emu.h.

#define _EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_MASK   0x1000UL

Bit mask for EMU_WDOG1LOCKED

Definition at line 1279 of file efr32fg14p_emu.h.

#define _EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_SHIFT   12

Shift value for EMU_WDOG1LOCKED

Definition at line 1278 of file efr32fg14p_emu.h.

#define _EMU_EM4CTRL_EM4ENTRY_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_EM4CTRL

Definition at line 298 of file efr32fg14p_emu.h.

#define _EMU_EM4CTRL_EM4ENTRY_MASK   0x30000UL

Bit mask for EMU_EM4ENTRY

Definition at line 297 of file efr32fg14p_emu.h.

Referenced by EMU_EnterEM4().

#define _EMU_EM4CTRL_EM4ENTRY_SHIFT   16

Shift value for EMU_EM4ENTRY

Definition at line 296 of file efr32fg14p_emu.h.

Referenced by EMU_EnterEM4().

#define _EMU_EM4CTRL_EM4IORETMODE_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_EM4CTRL

Definition at line 288 of file efr32fg14p_emu.h.

#define _EMU_EM4CTRL_EM4IORETMODE_DISABLE   0x00000000UL

Mode DISABLE for EMU_EM4CTRL

Definition at line 289 of file efr32fg14p_emu.h.

#define _EMU_EM4CTRL_EM4IORETMODE_EM4EXIT   0x00000001UL

Mode EM4EXIT for EMU_EM4CTRL

Definition at line 290 of file efr32fg14p_emu.h.

#define _EMU_EM4CTRL_EM4IORETMODE_MASK   0x30UL

Bit mask for EMU_EM4IORETMODE

Definition at line 287 of file efr32fg14p_emu.h.

Referenced by EMU_EM4Init(), and GPIO_EM4SetPinRetention().

#define _EMU_EM4CTRL_EM4IORETMODE_SHIFT   4

Shift value for EMU_EM4IORETMODE

Definition at line 286 of file efr32fg14p_emu.h.

#define _EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH   0x00000002UL

Mode SWUNLATCH for EMU_EM4CTRL

Definition at line 291 of file efr32fg14p_emu.h.

#define _EMU_EM4CTRL_EM4STATE_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_EM4CTRL

Definition at line 265 of file efr32fg14p_emu.h.

#define _EMU_EM4CTRL_EM4STATE_EM4H   0x00000001UL

Mode EM4H for EMU_EM4CTRL

Definition at line 267 of file efr32fg14p_emu.h.

#define _EMU_EM4CTRL_EM4STATE_EM4S   0x00000000UL

Mode EM4S for EMU_EM4CTRL

Definition at line 266 of file efr32fg14p_emu.h.

#define _EMU_EM4CTRL_EM4STATE_MASK   0x1UL

Bit mask for EMU_EM4STATE

Definition at line 264 of file efr32fg14p_emu.h.

Referenced by EMU_EM4Init(), and EMU_EnterEM4().

#define _EMU_EM4CTRL_EM4STATE_SHIFT   0

Shift value for EMU_EM4STATE

Definition at line 263 of file efr32fg14p_emu.h.

Referenced by EMU_EnterEM4H(), and EMU_EnterEM4S().

#define _EMU_EM4CTRL_MASK   0x0003003FUL

Mask for EMU_EM4CTRL

Definition at line 261 of file efr32fg14p_emu.h.

#define _EMU_EM4CTRL_RESETVALUE   0x00000000UL

Default value for EMU_EM4CTRL

Definition at line 260 of file efr32fg14p_emu.h.

#define _EMU_EM4CTRL_RETAINLFRCO_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_EM4CTRL

Definition at line 274 of file efr32fg14p_emu.h.

#define _EMU_EM4CTRL_RETAINLFRCO_MASK   0x2UL

Bit mask for EMU_RETAINLFRCO

Definition at line 273 of file efr32fg14p_emu.h.

Referenced by EMU_EM4Init().

#define _EMU_EM4CTRL_RETAINLFRCO_SHIFT   1

Shift value for EMU_RETAINLFRCO

Definition at line 272 of file efr32fg14p_emu.h.

#define _EMU_EM4CTRL_RETAINLFXO_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_EM4CTRL

Definition at line 279 of file efr32fg14p_emu.h.

#define _EMU_EM4CTRL_RETAINLFXO_MASK   0x4UL

Bit mask for EMU_RETAINLFXO

Definition at line 278 of file efr32fg14p_emu.h.

Referenced by EMU_EM4Init().

#define _EMU_EM4CTRL_RETAINLFXO_SHIFT   2

Shift value for EMU_RETAINLFXO

Definition at line 277 of file efr32fg14p_emu.h.

#define _EMU_EM4CTRL_RETAINULFRCO_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_EM4CTRL

Definition at line 284 of file efr32fg14p_emu.h.

#define _EMU_EM4CTRL_RETAINULFRCO_MASK   0x8UL

Bit mask for EMU_RETAINULFRCO

Definition at line 283 of file efr32fg14p_emu.h.

Referenced by EMU_EM4Init().

#define _EMU_EM4CTRL_RETAINULFRCO_SHIFT   3

Shift value for EMU_RETAINULFRCO

Definition at line 282 of file efr32fg14p_emu.h.

#define _EMU_IEN_DCDCINBYPASS_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_IEN

Definition at line 714 of file efr32fg14p_emu.h.

#define _EMU_IEN_DCDCINBYPASS_MASK   0x100000UL

Bit mask for EMU_DCDCINBYPASS

Definition at line 713 of file efr32fg14p_emu.h.

#define _EMU_IEN_DCDCINBYPASS_SHIFT   20

Shift value for EMU_DCDCINBYPASS

Definition at line 712 of file efr32fg14p_emu.h.

#define _EMU_IEN_DCDCLNRUNNING_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_IEN

Definition at line 709 of file efr32fg14p_emu.h.

#define _EMU_IEN_DCDCLNRUNNING_MASK   0x80000UL

Bit mask for EMU_DCDCLNRUNNING

Definition at line 708 of file efr32fg14p_emu.h.

#define _EMU_IEN_DCDCLNRUNNING_SHIFT   19

Shift value for EMU_DCDCLNRUNNING

Definition at line 707 of file efr32fg14p_emu.h.

#define _EMU_IEN_DCDCLPRUNNING_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_IEN

Definition at line 704 of file efr32fg14p_emu.h.

#define _EMU_IEN_DCDCLPRUNNING_MASK   0x40000UL

Bit mask for EMU_DCDCLPRUNNING

Definition at line 703 of file efr32fg14p_emu.h.

#define _EMU_IEN_DCDCLPRUNNING_SHIFT   18

Shift value for EMU_DCDCLPRUNNING

Definition at line 702 of file efr32fg14p_emu.h.

#define _EMU_IEN_EM23WAKEUP_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_IEN

Definition at line 719 of file efr32fg14p_emu.h.

#define _EMU_IEN_EM23WAKEUP_MASK   0x1000000UL

Bit mask for EMU_EM23WAKEUP

Definition at line 718 of file efr32fg14p_emu.h.

#define _EMU_IEN_EM23WAKEUP_SHIFT   24

Shift value for EMU_EM23WAKEUP

Definition at line 717 of file efr32fg14p_emu.h.

#define _EMU_IEN_MASK   0xE31FC0FFUL

Mask for EMU_IEN

Definition at line 640 of file efr32fg14p_emu.h.

#define _EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_IEN

Definition at line 699 of file efr32fg14p_emu.h.

#define _EMU_IEN_NFETOVERCURRENTLIMIT_MASK   0x20000UL

Bit mask for EMU_NFETOVERCURRENTLIMIT

Definition at line 698 of file efr32fg14p_emu.h.

#define _EMU_IEN_NFETOVERCURRENTLIMIT_SHIFT   17

Shift value for EMU_NFETOVERCURRENTLIMIT

Definition at line 697 of file efr32fg14p_emu.h.

#define _EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_IEN

Definition at line 694 of file efr32fg14p_emu.h.

#define _EMU_IEN_PFETOVERCURRENTLIMIT_MASK   0x10000UL

Bit mask for EMU_PFETOVERCURRENTLIMIT

Definition at line 693 of file efr32fg14p_emu.h.

#define _EMU_IEN_PFETOVERCURRENTLIMIT_SHIFT   16

Shift value for EMU_PFETOVERCURRENTLIMIT

Definition at line 692 of file efr32fg14p_emu.h.

#define _EMU_IEN_RESETVALUE   0x00000000UL

Default value for EMU_IEN

Definition at line 639 of file efr32fg14p_emu.h.

#define _EMU_IEN_TEMP_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_IEN

Definition at line 729 of file efr32fg14p_emu.h.

#define _EMU_IEN_TEMP_MASK   0x20000000UL

Bit mask for EMU_TEMP

Definition at line 728 of file efr32fg14p_emu.h.

#define _EMU_IEN_TEMP_SHIFT   29

Shift value for EMU_TEMP

Definition at line 727 of file efr32fg14p_emu.h.

#define _EMU_IEN_TEMPHIGH_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_IEN

Definition at line 739 of file efr32fg14p_emu.h.

#define _EMU_IEN_TEMPHIGH_MASK   0x80000000UL

Bit mask for EMU_TEMPHIGH

Definition at line 738 of file efr32fg14p_emu.h.

#define _EMU_IEN_TEMPHIGH_SHIFT   31

Shift value for EMU_TEMPHIGH

Definition at line 737 of file efr32fg14p_emu.h.

#define _EMU_IEN_TEMPLOW_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_IEN

Definition at line 734 of file efr32fg14p_emu.h.

#define _EMU_IEN_TEMPLOW_MASK   0x40000000UL

Bit mask for EMU_TEMPLOW

Definition at line 733 of file efr32fg14p_emu.h.

#define _EMU_IEN_TEMPLOW_SHIFT   30

Shift value for EMU_TEMPLOW

Definition at line 732 of file efr32fg14p_emu.h.

#define _EMU_IEN_VMONALTAVDDFALL_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_IEN

Definition at line 654 of file efr32fg14p_emu.h.

#define _EMU_IEN_VMONALTAVDDFALL_MASK   0x4UL

Bit mask for EMU_VMONALTAVDDFALL

Definition at line 653 of file efr32fg14p_emu.h.

#define _EMU_IEN_VMONALTAVDDFALL_SHIFT   2

Shift value for EMU_VMONALTAVDDFALL

Definition at line 652 of file efr32fg14p_emu.h.

#define _EMU_IEN_VMONALTAVDDRISE_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_IEN

Definition at line 659 of file efr32fg14p_emu.h.

#define _EMU_IEN_VMONALTAVDDRISE_MASK   0x8UL

Bit mask for EMU_VMONALTAVDDRISE

Definition at line 658 of file efr32fg14p_emu.h.

#define _EMU_IEN_VMONALTAVDDRISE_SHIFT   3

Shift value for EMU_VMONALTAVDDRISE

Definition at line 657 of file efr32fg14p_emu.h.

#define _EMU_IEN_VMONAVDDFALL_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_IEN

Definition at line 644 of file efr32fg14p_emu.h.

#define _EMU_IEN_VMONAVDDFALL_MASK   0x1UL

Bit mask for EMU_VMONAVDDFALL

Definition at line 643 of file efr32fg14p_emu.h.

#define _EMU_IEN_VMONAVDDFALL_SHIFT   0

Shift value for EMU_VMONAVDDFALL

Definition at line 642 of file efr32fg14p_emu.h.

#define _EMU_IEN_VMONAVDDRISE_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_IEN

Definition at line 649 of file efr32fg14p_emu.h.

#define _EMU_IEN_VMONAVDDRISE_MASK   0x2UL

Bit mask for EMU_VMONAVDDRISE

Definition at line 648 of file efr32fg14p_emu.h.

#define _EMU_IEN_VMONAVDDRISE_SHIFT   1

Shift value for EMU_VMONAVDDRISE

Definition at line 647 of file efr32fg14p_emu.h.

#define _EMU_IEN_VMONDVDDFALL_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_IEN

Definition at line 664 of file efr32fg14p_emu.h.

#define _EMU_IEN_VMONDVDDFALL_MASK   0x10UL

Bit mask for EMU_VMONDVDDFALL

Definition at line 663 of file efr32fg14p_emu.h.

#define _EMU_IEN_VMONDVDDFALL_SHIFT   4

Shift value for EMU_VMONDVDDFALL

Definition at line 662 of file efr32fg14p_emu.h.

#define _EMU_IEN_VMONDVDDRISE_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_IEN

Definition at line 669 of file efr32fg14p_emu.h.

#define _EMU_IEN_VMONDVDDRISE_MASK   0x20UL

Bit mask for EMU_VMONDVDDRISE

Definition at line 668 of file efr32fg14p_emu.h.

#define _EMU_IEN_VMONDVDDRISE_SHIFT   5

Shift value for EMU_VMONDVDDRISE

Definition at line 667 of file efr32fg14p_emu.h.

#define _EMU_IEN_VMONFVDDFALL_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_IEN

Definition at line 684 of file efr32fg14p_emu.h.

#define _EMU_IEN_VMONFVDDFALL_MASK   0x4000UL

Bit mask for EMU_VMONFVDDFALL

Definition at line 683 of file efr32fg14p_emu.h.

#define _EMU_IEN_VMONFVDDFALL_SHIFT   14

Shift value for EMU_VMONFVDDFALL

Definition at line 682 of file efr32fg14p_emu.h.

#define _EMU_IEN_VMONFVDDRISE_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_IEN

Definition at line 689 of file efr32fg14p_emu.h.

#define _EMU_IEN_VMONFVDDRISE_MASK   0x8000UL

Bit mask for EMU_VMONFVDDRISE

Definition at line 688 of file efr32fg14p_emu.h.

#define _EMU_IEN_VMONFVDDRISE_SHIFT   15

Shift value for EMU_VMONFVDDRISE

Definition at line 687 of file efr32fg14p_emu.h.

#define _EMU_IEN_VMONIO0FALL_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_IEN

Definition at line 674 of file efr32fg14p_emu.h.

#define _EMU_IEN_VMONIO0FALL_MASK   0x40UL

Bit mask for EMU_VMONIO0FALL

Definition at line 673 of file efr32fg14p_emu.h.

#define _EMU_IEN_VMONIO0FALL_SHIFT   6

Shift value for EMU_VMONIO0FALL

Definition at line 672 of file efr32fg14p_emu.h.

#define _EMU_IEN_VMONIO0RISE_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_IEN

Definition at line 679 of file efr32fg14p_emu.h.

#define _EMU_IEN_VMONIO0RISE_MASK   0x80UL

Bit mask for EMU_VMONIO0RISE

Definition at line 678 of file efr32fg14p_emu.h.

#define _EMU_IEN_VMONIO0RISE_SHIFT   7

Shift value for EMU_VMONIO0RISE

Definition at line 677 of file efr32fg14p_emu.h.

#define _EMU_IEN_VSCALEDONE_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_IEN

Definition at line 724 of file efr32fg14p_emu.h.

#define _EMU_IEN_VSCALEDONE_MASK   0x2000000UL

Bit mask for EMU_VSCALEDONE

Definition at line 723 of file efr32fg14p_emu.h.

#define _EMU_IEN_VSCALEDONE_SHIFT   25

Shift value for EMU_VSCALEDONE

Definition at line 722 of file efr32fg14p_emu.h.

#define _EMU_IF_DCDCINBYPASS_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_IF

Definition at line 402 of file efr32fg14p_emu.h.

#define _EMU_IF_DCDCINBYPASS_MASK   0x100000UL

Bit mask for EMU_DCDCINBYPASS

Definition at line 401 of file efr32fg14p_emu.h.

#define _EMU_IF_DCDCINBYPASS_SHIFT   20

Shift value for EMU_DCDCINBYPASS

Definition at line 400 of file efr32fg14p_emu.h.

#define _EMU_IF_DCDCLNRUNNING_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_IF

Definition at line 397 of file efr32fg14p_emu.h.

#define _EMU_IF_DCDCLNRUNNING_MASK   0x80000UL

Bit mask for EMU_DCDCLNRUNNING

Definition at line 396 of file efr32fg14p_emu.h.

#define _EMU_IF_DCDCLNRUNNING_SHIFT   19

Shift value for EMU_DCDCLNRUNNING

Definition at line 395 of file efr32fg14p_emu.h.

#define _EMU_IF_DCDCLPRUNNING_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_IF

Definition at line 392 of file efr32fg14p_emu.h.

#define _EMU_IF_DCDCLPRUNNING_MASK   0x40000UL

Bit mask for EMU_DCDCLPRUNNING

Definition at line 391 of file efr32fg14p_emu.h.

#define _EMU_IF_DCDCLPRUNNING_SHIFT   18

Shift value for EMU_DCDCLPRUNNING

Definition at line 390 of file efr32fg14p_emu.h.

#define _EMU_IF_EM23WAKEUP_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_IF

Definition at line 407 of file efr32fg14p_emu.h.

#define _EMU_IF_EM23WAKEUP_MASK   0x1000000UL

Bit mask for EMU_EM23WAKEUP

Definition at line 406 of file efr32fg14p_emu.h.

#define _EMU_IF_EM23WAKEUP_SHIFT   24

Shift value for EMU_EM23WAKEUP

Definition at line 405 of file efr32fg14p_emu.h.

#define _EMU_IF_MASK   0xE31FC0FFUL

Mask for EMU_IF

Definition at line 328 of file efr32fg14p_emu.h.

#define _EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_IF

Definition at line 387 of file efr32fg14p_emu.h.

#define _EMU_IF_NFETOVERCURRENTLIMIT_MASK   0x20000UL

Bit mask for EMU_NFETOVERCURRENTLIMIT

Definition at line 386 of file efr32fg14p_emu.h.

#define _EMU_IF_NFETOVERCURRENTLIMIT_SHIFT   17

Shift value for EMU_NFETOVERCURRENTLIMIT

Definition at line 385 of file efr32fg14p_emu.h.

#define _EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_IF

Definition at line 382 of file efr32fg14p_emu.h.

#define _EMU_IF_PFETOVERCURRENTLIMIT_MASK   0x10000UL

Bit mask for EMU_PFETOVERCURRENTLIMIT

Definition at line 381 of file efr32fg14p_emu.h.

#define _EMU_IF_PFETOVERCURRENTLIMIT_SHIFT   16

Shift value for EMU_PFETOVERCURRENTLIMIT

Definition at line 380 of file efr32fg14p_emu.h.

#define _EMU_IF_RESETVALUE   0x00000000UL

Default value for EMU_IF

Definition at line 327 of file efr32fg14p_emu.h.

#define _EMU_IF_TEMP_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_IF

Definition at line 417 of file efr32fg14p_emu.h.

#define _EMU_IF_TEMP_MASK   0x20000000UL

Bit mask for EMU_TEMP

Definition at line 416 of file efr32fg14p_emu.h.

#define _EMU_IF_TEMP_SHIFT   29

Shift value for EMU_TEMP

Definition at line 415 of file efr32fg14p_emu.h.

#define _EMU_IF_TEMPHIGH_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_IF

Definition at line 427 of file efr32fg14p_emu.h.

#define _EMU_IF_TEMPHIGH_MASK   0x80000000UL

Bit mask for EMU_TEMPHIGH

Definition at line 426 of file efr32fg14p_emu.h.

#define _EMU_IF_TEMPHIGH_SHIFT   31

Shift value for EMU_TEMPHIGH

Definition at line 425 of file efr32fg14p_emu.h.

#define _EMU_IF_TEMPLOW_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_IF

Definition at line 422 of file efr32fg14p_emu.h.

#define _EMU_IF_TEMPLOW_MASK   0x40000000UL

Bit mask for EMU_TEMPLOW

Definition at line 421 of file efr32fg14p_emu.h.

#define _EMU_IF_TEMPLOW_SHIFT   30

Shift value for EMU_TEMPLOW

Definition at line 420 of file efr32fg14p_emu.h.

#define _EMU_IF_VMONALTAVDDFALL_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_IF

Definition at line 342 of file efr32fg14p_emu.h.

#define _EMU_IF_VMONALTAVDDFALL_MASK   0x4UL

Bit mask for EMU_VMONALTAVDDFALL

Definition at line 341 of file efr32fg14p_emu.h.

#define _EMU_IF_VMONALTAVDDFALL_SHIFT   2

Shift value for EMU_VMONALTAVDDFALL

Definition at line 340 of file efr32fg14p_emu.h.

#define _EMU_IF_VMONALTAVDDRISE_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_IF

Definition at line 347 of file efr32fg14p_emu.h.

#define _EMU_IF_VMONALTAVDDRISE_MASK   0x8UL

Bit mask for EMU_VMONALTAVDDRISE

Definition at line 346 of file efr32fg14p_emu.h.

#define _EMU_IF_VMONALTAVDDRISE_SHIFT   3

Shift value for EMU_VMONALTAVDDRISE

Definition at line 345 of file efr32fg14p_emu.h.

#define _EMU_IF_VMONAVDDFALL_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_IF

Definition at line 332 of file efr32fg14p_emu.h.

#define _EMU_IF_VMONAVDDFALL_MASK   0x1UL

Bit mask for EMU_VMONAVDDFALL

Definition at line 331 of file efr32fg14p_emu.h.

#define _EMU_IF_VMONAVDDFALL_SHIFT   0

Shift value for EMU_VMONAVDDFALL

Definition at line 330 of file efr32fg14p_emu.h.

#define _EMU_IF_VMONAVDDRISE_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_IF

Definition at line 337 of file efr32fg14p_emu.h.

#define _EMU_IF_VMONAVDDRISE_MASK   0x2UL

Bit mask for EMU_VMONAVDDRISE

Definition at line 336 of file efr32fg14p_emu.h.

#define _EMU_IF_VMONAVDDRISE_SHIFT   1

Shift value for EMU_VMONAVDDRISE

Definition at line 335 of file efr32fg14p_emu.h.

#define _EMU_IF_VMONDVDDFALL_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_IF

Definition at line 352 of file efr32fg14p_emu.h.

#define _EMU_IF_VMONDVDDFALL_MASK   0x10UL

Bit mask for EMU_VMONDVDDFALL

Definition at line 351 of file efr32fg14p_emu.h.

#define _EMU_IF_VMONDVDDFALL_SHIFT   4

Shift value for EMU_VMONDVDDFALL

Definition at line 350 of file efr32fg14p_emu.h.

#define _EMU_IF_VMONDVDDRISE_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_IF

Definition at line 357 of file efr32fg14p_emu.h.

#define _EMU_IF_VMONDVDDRISE_MASK   0x20UL

Bit mask for EMU_VMONDVDDRISE

Definition at line 356 of file efr32fg14p_emu.h.

#define _EMU_IF_VMONDVDDRISE_SHIFT   5

Shift value for EMU_VMONDVDDRISE

Definition at line 355 of file efr32fg14p_emu.h.

#define _EMU_IF_VMONFVDDFALL_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_IF

Definition at line 372 of file efr32fg14p_emu.h.

#define _EMU_IF_VMONFVDDFALL_MASK   0x4000UL

Bit mask for EMU_VMONFVDDFALL

Definition at line 371 of file efr32fg14p_emu.h.

#define _EMU_IF_VMONFVDDFALL_SHIFT   14

Shift value for EMU_VMONFVDDFALL

Definition at line 370 of file efr32fg14p_emu.h.

#define _EMU_IF_VMONFVDDRISE_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_IF

Definition at line 377 of file efr32fg14p_emu.h.

#define _EMU_IF_VMONFVDDRISE_MASK   0x8000UL

Bit mask for EMU_VMONFVDDRISE

Definition at line 376 of file efr32fg14p_emu.h.

#define _EMU_IF_VMONFVDDRISE_SHIFT   15

Shift value for EMU_VMONFVDDRISE

Definition at line 375 of file efr32fg14p_emu.h.

#define _EMU_IF_VMONIO0FALL_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_IF

Definition at line 362 of file efr32fg14p_emu.h.

#define _EMU_IF_VMONIO0FALL_MASK   0x40UL

Bit mask for EMU_VMONIO0FALL

Definition at line 361 of file efr32fg14p_emu.h.

#define _EMU_IF_VMONIO0FALL_SHIFT   6

Shift value for EMU_VMONIO0FALL

Definition at line 360 of file efr32fg14p_emu.h.

#define _EMU_IF_VMONIO0RISE_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_IF

Definition at line 367 of file efr32fg14p_emu.h.

#define _EMU_IF_VMONIO0RISE_MASK   0x80UL

Bit mask for EMU_VMONIO0RISE

Definition at line 366 of file efr32fg14p_emu.h.

#define _EMU_IF_VMONIO0RISE_SHIFT   7

Shift value for EMU_VMONIO0RISE

Definition at line 365 of file efr32fg14p_emu.h.

#define _EMU_IF_VSCALEDONE_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_IF

Definition at line 412 of file efr32fg14p_emu.h.

#define _EMU_IF_VSCALEDONE_MASK   0x2000000UL

Bit mask for EMU_VSCALEDONE

Definition at line 411 of file efr32fg14p_emu.h.

#define _EMU_IF_VSCALEDONE_SHIFT   25

Shift value for EMU_VSCALEDONE

Definition at line 410 of file efr32fg14p_emu.h.

#define _EMU_IFC_DCDCINBYPASS_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_IFC

Definition at line 610 of file efr32fg14p_emu.h.

#define _EMU_IFC_DCDCINBYPASS_MASK   0x100000UL

Bit mask for EMU_DCDCINBYPASS

Definition at line 609 of file efr32fg14p_emu.h.

#define _EMU_IFC_DCDCINBYPASS_SHIFT   20

Shift value for EMU_DCDCINBYPASS

Definition at line 608 of file efr32fg14p_emu.h.

#define _EMU_IFC_DCDCLNRUNNING_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_IFC

Definition at line 605 of file efr32fg14p_emu.h.

#define _EMU_IFC_DCDCLNRUNNING_MASK   0x80000UL

Bit mask for EMU_DCDCLNRUNNING

Definition at line 604 of file efr32fg14p_emu.h.

#define _EMU_IFC_DCDCLNRUNNING_SHIFT   19

Shift value for EMU_DCDCLNRUNNING

Definition at line 603 of file efr32fg14p_emu.h.

#define _EMU_IFC_DCDCLPRUNNING_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_IFC

Definition at line 600 of file efr32fg14p_emu.h.

#define _EMU_IFC_DCDCLPRUNNING_MASK   0x40000UL

Bit mask for EMU_DCDCLPRUNNING

Definition at line 599 of file efr32fg14p_emu.h.

#define _EMU_IFC_DCDCLPRUNNING_SHIFT   18

Shift value for EMU_DCDCLPRUNNING

Definition at line 598 of file efr32fg14p_emu.h.

#define _EMU_IFC_EM23WAKEUP_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_IFC

Definition at line 615 of file efr32fg14p_emu.h.

#define _EMU_IFC_EM23WAKEUP_MASK   0x1000000UL

Bit mask for EMU_EM23WAKEUP

Definition at line 614 of file efr32fg14p_emu.h.

#define _EMU_IFC_EM23WAKEUP_SHIFT   24

Shift value for EMU_EM23WAKEUP

Definition at line 613 of file efr32fg14p_emu.h.

#define _EMU_IFC_MASK   0xE31FC0FFUL

Mask for EMU_IFC

Definition at line 536 of file efr32fg14p_emu.h.

#define _EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_IFC

Definition at line 595 of file efr32fg14p_emu.h.

#define _EMU_IFC_NFETOVERCURRENTLIMIT_MASK   0x20000UL

Bit mask for EMU_NFETOVERCURRENTLIMIT

Definition at line 594 of file efr32fg14p_emu.h.

#define _EMU_IFC_NFETOVERCURRENTLIMIT_SHIFT   17

Shift value for EMU_NFETOVERCURRENTLIMIT

Definition at line 593 of file efr32fg14p_emu.h.

#define _EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_IFC

Definition at line 590 of file efr32fg14p_emu.h.

#define _EMU_IFC_PFETOVERCURRENTLIMIT_MASK   0x10000UL

Bit mask for EMU_PFETOVERCURRENTLIMIT

Definition at line 589 of file efr32fg14p_emu.h.

#define _EMU_IFC_PFETOVERCURRENTLIMIT_SHIFT   16

Shift value for EMU_PFETOVERCURRENTLIMIT

Definition at line 588 of file efr32fg14p_emu.h.

#define _EMU_IFC_RESETVALUE   0x00000000UL

Default value for EMU_IFC

Definition at line 535 of file efr32fg14p_emu.h.

#define _EMU_IFC_TEMP_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_IFC

Definition at line 625 of file efr32fg14p_emu.h.

#define _EMU_IFC_TEMP_MASK   0x20000000UL

Bit mask for EMU_TEMP

Definition at line 624 of file efr32fg14p_emu.h.

#define _EMU_IFC_TEMP_SHIFT   29

Shift value for EMU_TEMP

Definition at line 623 of file efr32fg14p_emu.h.

#define _EMU_IFC_TEMPHIGH_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_IFC

Definition at line 635 of file efr32fg14p_emu.h.

#define _EMU_IFC_TEMPHIGH_MASK   0x80000000UL

Bit mask for EMU_TEMPHIGH

Definition at line 634 of file efr32fg14p_emu.h.

#define _EMU_IFC_TEMPHIGH_SHIFT   31

Shift value for EMU_TEMPHIGH

Definition at line 633 of file efr32fg14p_emu.h.

#define _EMU_IFC_TEMPLOW_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_IFC

Definition at line 630 of file efr32fg14p_emu.h.

#define _EMU_IFC_TEMPLOW_MASK   0x40000000UL

Bit mask for EMU_TEMPLOW

Definition at line 629 of file efr32fg14p_emu.h.

#define _EMU_IFC_TEMPLOW_SHIFT   30

Shift value for EMU_TEMPLOW

Definition at line 628 of file efr32fg14p_emu.h.

#define _EMU_IFC_VMONALTAVDDFALL_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_IFC

Definition at line 550 of file efr32fg14p_emu.h.

#define _EMU_IFC_VMONALTAVDDFALL_MASK   0x4UL

Bit mask for EMU_VMONALTAVDDFALL

Definition at line 549 of file efr32fg14p_emu.h.

#define _EMU_IFC_VMONALTAVDDFALL_SHIFT   2

Shift value for EMU_VMONALTAVDDFALL

Definition at line 548 of file efr32fg14p_emu.h.

#define _EMU_IFC_VMONALTAVDDRISE_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_IFC

Definition at line 555 of file efr32fg14p_emu.h.

#define _EMU_IFC_VMONALTAVDDRISE_MASK   0x8UL

Bit mask for EMU_VMONALTAVDDRISE

Definition at line 554 of file efr32fg14p_emu.h.

#define _EMU_IFC_VMONALTAVDDRISE_SHIFT   3

Shift value for EMU_VMONALTAVDDRISE

Definition at line 553 of file efr32fg14p_emu.h.

#define _EMU_IFC_VMONAVDDFALL_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_IFC

Definition at line 540 of file efr32fg14p_emu.h.

#define _EMU_IFC_VMONAVDDFALL_MASK   0x1UL

Bit mask for EMU_VMONAVDDFALL

Definition at line 539 of file efr32fg14p_emu.h.

#define _EMU_IFC_VMONAVDDFALL_SHIFT   0

Shift value for EMU_VMONAVDDFALL

Definition at line 538 of file efr32fg14p_emu.h.

#define _EMU_IFC_VMONAVDDRISE_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_IFC

Definition at line 545 of file efr32fg14p_emu.h.

#define _EMU_IFC_VMONAVDDRISE_MASK   0x2UL

Bit mask for EMU_VMONAVDDRISE

Definition at line 544 of file efr32fg14p_emu.h.

#define _EMU_IFC_VMONAVDDRISE_SHIFT   1

Shift value for EMU_VMONAVDDRISE

Definition at line 543 of file efr32fg14p_emu.h.

#define _EMU_IFC_VMONDVDDFALL_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_IFC

Definition at line 560 of file efr32fg14p_emu.h.

#define _EMU_IFC_VMONDVDDFALL_MASK   0x10UL

Bit mask for EMU_VMONDVDDFALL

Definition at line 559 of file efr32fg14p_emu.h.

#define _EMU_IFC_VMONDVDDFALL_SHIFT   4

Shift value for EMU_VMONDVDDFALL

Definition at line 558 of file efr32fg14p_emu.h.

#define _EMU_IFC_VMONDVDDRISE_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_IFC

Definition at line 565 of file efr32fg14p_emu.h.

#define _EMU_IFC_VMONDVDDRISE_MASK   0x20UL

Bit mask for EMU_VMONDVDDRISE

Definition at line 564 of file efr32fg14p_emu.h.

#define _EMU_IFC_VMONDVDDRISE_SHIFT   5

Shift value for EMU_VMONDVDDRISE

Definition at line 563 of file efr32fg14p_emu.h.

#define _EMU_IFC_VMONFVDDFALL_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_IFC

Definition at line 580 of file efr32fg14p_emu.h.

#define _EMU_IFC_VMONFVDDFALL_MASK   0x4000UL

Bit mask for EMU_VMONFVDDFALL

Definition at line 579 of file efr32fg14p_emu.h.

#define _EMU_IFC_VMONFVDDFALL_SHIFT   14

Shift value for EMU_VMONFVDDFALL

Definition at line 578 of file efr32fg14p_emu.h.

#define _EMU_IFC_VMONFVDDRISE_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_IFC

Definition at line 585 of file efr32fg14p_emu.h.

#define _EMU_IFC_VMONFVDDRISE_MASK   0x8000UL

Bit mask for EMU_VMONFVDDRISE

Definition at line 584 of file efr32fg14p_emu.h.

#define _EMU_IFC_VMONFVDDRISE_SHIFT   15

Shift value for EMU_VMONFVDDRISE

Definition at line 583 of file efr32fg14p_emu.h.

#define _EMU_IFC_VMONIO0FALL_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_IFC

Definition at line 570 of file efr32fg14p_emu.h.

#define _EMU_IFC_VMONIO0FALL_MASK   0x40UL

Bit mask for EMU_VMONIO0FALL

Definition at line 569 of file efr32fg14p_emu.h.

#define _EMU_IFC_VMONIO0FALL_SHIFT   6

Shift value for EMU_VMONIO0FALL

Definition at line 568 of file efr32fg14p_emu.h.

#define _EMU_IFC_VMONIO0RISE_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_IFC

Definition at line 575 of file efr32fg14p_emu.h.

#define _EMU_IFC_VMONIO0RISE_MASK   0x80UL

Bit mask for EMU_VMONIO0RISE

Definition at line 574 of file efr32fg14p_emu.h.

#define _EMU_IFC_VMONIO0RISE_SHIFT   7

Shift value for EMU_VMONIO0RISE

Definition at line 573 of file efr32fg14p_emu.h.

#define _EMU_IFC_VSCALEDONE_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_IFC

Definition at line 620 of file efr32fg14p_emu.h.

#define _EMU_IFC_VSCALEDONE_MASK   0x2000000UL

Bit mask for EMU_VSCALEDONE

Definition at line 619 of file efr32fg14p_emu.h.

#define _EMU_IFC_VSCALEDONE_SHIFT   25

Shift value for EMU_VSCALEDONE

Definition at line 618 of file efr32fg14p_emu.h.

#define _EMU_IFS_DCDCINBYPASS_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_IFS

Definition at line 506 of file efr32fg14p_emu.h.

#define _EMU_IFS_DCDCINBYPASS_MASK   0x100000UL

Bit mask for EMU_DCDCINBYPASS

Definition at line 505 of file efr32fg14p_emu.h.

#define _EMU_IFS_DCDCINBYPASS_SHIFT   20

Shift value for EMU_DCDCINBYPASS

Definition at line 504 of file efr32fg14p_emu.h.

#define _EMU_IFS_DCDCLNRUNNING_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_IFS

Definition at line 501 of file efr32fg14p_emu.h.

#define _EMU_IFS_DCDCLNRUNNING_MASK   0x80000UL

Bit mask for EMU_DCDCLNRUNNING

Definition at line 500 of file efr32fg14p_emu.h.

#define _EMU_IFS_DCDCLNRUNNING_SHIFT   19

Shift value for EMU_DCDCLNRUNNING

Definition at line 499 of file efr32fg14p_emu.h.

#define _EMU_IFS_DCDCLPRUNNING_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_IFS

Definition at line 496 of file efr32fg14p_emu.h.

#define _EMU_IFS_DCDCLPRUNNING_MASK   0x40000UL

Bit mask for EMU_DCDCLPRUNNING

Definition at line 495 of file efr32fg14p_emu.h.

#define _EMU_IFS_DCDCLPRUNNING_SHIFT   18

Shift value for EMU_DCDCLPRUNNING

Definition at line 494 of file efr32fg14p_emu.h.

#define _EMU_IFS_EM23WAKEUP_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_IFS

Definition at line 511 of file efr32fg14p_emu.h.

#define _EMU_IFS_EM23WAKEUP_MASK   0x1000000UL

Bit mask for EMU_EM23WAKEUP

Definition at line 510 of file efr32fg14p_emu.h.

#define _EMU_IFS_EM23WAKEUP_SHIFT   24

Shift value for EMU_EM23WAKEUP

Definition at line 509 of file efr32fg14p_emu.h.

#define _EMU_IFS_MASK   0xE31FC0FFUL

Mask for EMU_IFS

Definition at line 432 of file efr32fg14p_emu.h.

#define _EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_IFS

Definition at line 491 of file efr32fg14p_emu.h.

#define _EMU_IFS_NFETOVERCURRENTLIMIT_MASK   0x20000UL

Bit mask for EMU_NFETOVERCURRENTLIMIT

Definition at line 490 of file efr32fg14p_emu.h.

#define _EMU_IFS_NFETOVERCURRENTLIMIT_SHIFT   17

Shift value for EMU_NFETOVERCURRENTLIMIT

Definition at line 489 of file efr32fg14p_emu.h.

#define _EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_IFS

Definition at line 486 of file efr32fg14p_emu.h.

#define _EMU_IFS_PFETOVERCURRENTLIMIT_MASK   0x10000UL

Bit mask for EMU_PFETOVERCURRENTLIMIT

Definition at line 485 of file efr32fg14p_emu.h.

#define _EMU_IFS_PFETOVERCURRENTLIMIT_SHIFT   16

Shift value for EMU_PFETOVERCURRENTLIMIT

Definition at line 484 of file efr32fg14p_emu.h.

#define _EMU_IFS_RESETVALUE   0x00000000UL

Default value for EMU_IFS

Definition at line 431 of file efr32fg14p_emu.h.

#define _EMU_IFS_TEMP_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_IFS

Definition at line 521 of file efr32fg14p_emu.h.

#define _EMU_IFS_TEMP_MASK   0x20000000UL

Bit mask for EMU_TEMP

Definition at line 520 of file efr32fg14p_emu.h.

#define _EMU_IFS_TEMP_SHIFT   29

Shift value for EMU_TEMP

Definition at line 519 of file efr32fg14p_emu.h.

#define _EMU_IFS_TEMPHIGH_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_IFS

Definition at line 531 of file efr32fg14p_emu.h.

#define _EMU_IFS_TEMPHIGH_MASK   0x80000000UL

Bit mask for EMU_TEMPHIGH

Definition at line 530 of file efr32fg14p_emu.h.

#define _EMU_IFS_TEMPHIGH_SHIFT   31

Shift value for EMU_TEMPHIGH

Definition at line 529 of file efr32fg14p_emu.h.

#define _EMU_IFS_TEMPLOW_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_IFS

Definition at line 526 of file efr32fg14p_emu.h.

#define _EMU_IFS_TEMPLOW_MASK   0x40000000UL

Bit mask for EMU_TEMPLOW

Definition at line 525 of file efr32fg14p_emu.h.

#define _EMU_IFS_TEMPLOW_SHIFT   30

Shift value for EMU_TEMPLOW

Definition at line 524 of file efr32fg14p_emu.h.

#define _EMU_IFS_VMONALTAVDDFALL_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_IFS

Definition at line 446 of file efr32fg14p_emu.h.

#define _EMU_IFS_VMONALTAVDDFALL_MASK   0x4UL

Bit mask for EMU_VMONALTAVDDFALL

Definition at line 445 of file efr32fg14p_emu.h.

#define _EMU_IFS_VMONALTAVDDFALL_SHIFT   2

Shift value for EMU_VMONALTAVDDFALL

Definition at line 444 of file efr32fg14p_emu.h.

#define _EMU_IFS_VMONALTAVDDRISE_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_IFS

Definition at line 451 of file efr32fg14p_emu.h.

#define _EMU_IFS_VMONALTAVDDRISE_MASK   0x8UL

Bit mask for EMU_VMONALTAVDDRISE

Definition at line 450 of file efr32fg14p_emu.h.

#define _EMU_IFS_VMONALTAVDDRISE_SHIFT   3

Shift value for EMU_VMONALTAVDDRISE

Definition at line 449 of file efr32fg14p_emu.h.

#define _EMU_IFS_VMONAVDDFALL_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_IFS

Definition at line 436 of file efr32fg14p_emu.h.

#define _EMU_IFS_VMONAVDDFALL_MASK   0x1UL

Bit mask for EMU_VMONAVDDFALL

Definition at line 435 of file efr32fg14p_emu.h.

#define _EMU_IFS_VMONAVDDFALL_SHIFT   0

Shift value for EMU_VMONAVDDFALL

Definition at line 434 of file efr32fg14p_emu.h.

#define _EMU_IFS_VMONAVDDRISE_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_IFS

Definition at line 441 of file efr32fg14p_emu.h.

#define _EMU_IFS_VMONAVDDRISE_MASK   0x2UL

Bit mask for EMU_VMONAVDDRISE

Definition at line 440 of file efr32fg14p_emu.h.

#define _EMU_IFS_VMONAVDDRISE_SHIFT   1

Shift value for EMU_VMONAVDDRISE

Definition at line 439 of file efr32fg14p_emu.h.

#define _EMU_IFS_VMONDVDDFALL_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_IFS

Definition at line 456 of file efr32fg14p_emu.h.

#define _EMU_IFS_VMONDVDDFALL_MASK   0x10UL

Bit mask for EMU_VMONDVDDFALL

Definition at line 455 of file efr32fg14p_emu.h.

#define _EMU_IFS_VMONDVDDFALL_SHIFT   4

Shift value for EMU_VMONDVDDFALL

Definition at line 454 of file efr32fg14p_emu.h.

#define _EMU_IFS_VMONDVDDRISE_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_IFS

Definition at line 461 of file efr32fg14p_emu.h.

#define _EMU_IFS_VMONDVDDRISE_MASK   0x20UL

Bit mask for EMU_VMONDVDDRISE

Definition at line 460 of file efr32fg14p_emu.h.

#define _EMU_IFS_VMONDVDDRISE_SHIFT   5

Shift value for EMU_VMONDVDDRISE

Definition at line 459 of file efr32fg14p_emu.h.

#define _EMU_IFS_VMONFVDDFALL_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_IFS

Definition at line 476 of file efr32fg14p_emu.h.

#define _EMU_IFS_VMONFVDDFALL_MASK   0x4000UL

Bit mask for EMU_VMONFVDDFALL

Definition at line 475 of file efr32fg14p_emu.h.

#define _EMU_IFS_VMONFVDDFALL_SHIFT   14

Shift value for EMU_VMONFVDDFALL

Definition at line 474 of file efr32fg14p_emu.h.

#define _EMU_IFS_VMONFVDDRISE_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_IFS

Definition at line 481 of file efr32fg14p_emu.h.

#define _EMU_IFS_VMONFVDDRISE_MASK   0x8000UL

Bit mask for EMU_VMONFVDDRISE

Definition at line 480 of file efr32fg14p_emu.h.

#define _EMU_IFS_VMONFVDDRISE_SHIFT   15

Shift value for EMU_VMONFVDDRISE

Definition at line 479 of file efr32fg14p_emu.h.

#define _EMU_IFS_VMONIO0FALL_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_IFS

Definition at line 466 of file efr32fg14p_emu.h.

#define _EMU_IFS_VMONIO0FALL_MASK   0x40UL

Bit mask for EMU_VMONIO0FALL

Definition at line 465 of file efr32fg14p_emu.h.

#define _EMU_IFS_VMONIO0FALL_SHIFT   6

Shift value for EMU_VMONIO0FALL

Definition at line 464 of file efr32fg14p_emu.h.

#define _EMU_IFS_VMONIO0RISE_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_IFS

Definition at line 471 of file efr32fg14p_emu.h.

#define _EMU_IFS_VMONIO0RISE_MASK   0x80UL

Bit mask for EMU_VMONIO0RISE

Definition at line 470 of file efr32fg14p_emu.h.

#define _EMU_IFS_VMONIO0RISE_SHIFT   7

Shift value for EMU_VMONIO0RISE

Definition at line 469 of file efr32fg14p_emu.h.

#define _EMU_IFS_VSCALEDONE_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_IFS

Definition at line 516 of file efr32fg14p_emu.h.

#define _EMU_IFS_VSCALEDONE_MASK   0x2000000UL

Bit mask for EMU_VSCALEDONE

Definition at line 515 of file efr32fg14p_emu.h.

#define _EMU_IFS_VSCALEDONE_SHIFT   25

Shift value for EMU_VSCALEDONE

Definition at line 514 of file efr32fg14p_emu.h.

#define _EMU_LOCK_LOCKKEY_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_LOCK

Definition at line 225 of file efr32fg14p_emu.h.

#define _EMU_LOCK_LOCKKEY_LOCK   0x00000000UL

Mode LOCK for EMU_LOCK

Definition at line 226 of file efr32fg14p_emu.h.

#define _EMU_LOCK_LOCKKEY_LOCKED   0x00000001UL

Mode LOCKED for EMU_LOCK

Definition at line 228 of file efr32fg14p_emu.h.

#define _EMU_LOCK_LOCKKEY_MASK   0xFFFFUL

Bit mask for EMU_LOCKKEY

Definition at line 224 of file efr32fg14p_emu.h.

#define _EMU_LOCK_LOCKKEY_SHIFT   0

Shift value for EMU_LOCKKEY

Definition at line 223 of file efr32fg14p_emu.h.

#define _EMU_LOCK_LOCKKEY_UNLOCK   0x0000ADE8UL

Mode UNLOCK for EMU_LOCK

Definition at line 229 of file efr32fg14p_emu.h.

#define _EMU_LOCK_LOCKKEY_UNLOCKED   0x00000000UL

Mode UNLOCKED for EMU_LOCK

Definition at line 227 of file efr32fg14p_emu.h.

#define _EMU_LOCK_MASK   0x0000FFFFUL

Mask for EMU_LOCK

Definition at line 222 of file efr32fg14p_emu.h.

#define _EMU_LOCK_RESETVALUE   0x00000000UL

Default value for EMU_LOCK

Definition at line 221 of file efr32fg14p_emu.h.

#define _EMU_PWRCTRL_ANASW_AVDD   0x00000000UL

Mode AVDD for EMU_PWRCTRL

Definition at line 765 of file efr32fg14p_emu.h.

#define _EMU_PWRCTRL_ANASW_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_PWRCTRL

Definition at line 764 of file efr32fg14p_emu.h.

#define _EMU_PWRCTRL_ANASW_DVDD   0x00000001UL

Mode DVDD for EMU_PWRCTRL

Definition at line 766 of file efr32fg14p_emu.h.

#define _EMU_PWRCTRL_ANASW_MASK   0x20UL

Bit mask for EMU_ANASW

Definition at line 763 of file efr32fg14p_emu.h.

Referenced by EMU_EnterEM4().

#define _EMU_PWRCTRL_ANASW_SHIFT   5

Shift value for EMU_ANASW

Definition at line 762 of file efr32fg14p_emu.h.

Referenced by EMU_DCDCInit().

#define _EMU_PWRCTRL_IMMEDIATEPWRSWITCH_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_PWRCTRL

Definition at line 782 of file efr32fg14p_emu.h.

#define _EMU_PWRCTRL_IMMEDIATEPWRSWITCH_MASK   0x2000UL

Bit mask for EMU_IMMEDIATEPWRSWITCH

Definition at line 781 of file efr32fg14p_emu.h.

#define _EMU_PWRCTRL_IMMEDIATEPWRSWITCH_SHIFT   13

Shift value for EMU_IMMEDIATEPWRSWITCH

Definition at line 780 of file efr32fg14p_emu.h.

#define _EMU_PWRCTRL_MASK   0x00002420UL

Mask for EMU_PWRCTRL

Definition at line 760 of file efr32fg14p_emu.h.

#define _EMU_PWRCTRL_REGPWRSEL_AVDD   0x00000000UL

Mode AVDD for EMU_PWRCTRL

Definition at line 774 of file efr32fg14p_emu.h.

#define _EMU_PWRCTRL_REGPWRSEL_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_PWRCTRL

Definition at line 773 of file efr32fg14p_emu.h.

#define _EMU_PWRCTRL_REGPWRSEL_DVDD   0x00000001UL

Mode DVDD for EMU_PWRCTRL

Definition at line 775 of file efr32fg14p_emu.h.

#define _EMU_PWRCTRL_REGPWRSEL_MASK   0x400UL

Bit mask for EMU_REGPWRSEL

Definition at line 772 of file efr32fg14p_emu.h.

#define _EMU_PWRCTRL_REGPWRSEL_SHIFT   10

Shift value for EMU_REGPWRSEL

Definition at line 771 of file efr32fg14p_emu.h.

#define _EMU_PWRCTRL_RESETVALUE   0x00000000UL

Default value for EMU_PWRCTRL

Definition at line 759 of file efr32fg14p_emu.h.

#define _EMU_PWRLOCK_LOCKKEY_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_PWRLOCK

Definition at line 747 of file efr32fg14p_emu.h.

#define _EMU_PWRLOCK_LOCKKEY_LOCK   0x00000000UL

Mode LOCK for EMU_PWRLOCK

Definition at line 748 of file efr32fg14p_emu.h.

#define _EMU_PWRLOCK_LOCKKEY_LOCKED   0x00000001UL

Mode LOCKED for EMU_PWRLOCK

Definition at line 750 of file efr32fg14p_emu.h.

#define _EMU_PWRLOCK_LOCKKEY_MASK   0xFFFFUL

Bit mask for EMU_LOCKKEY

Definition at line 746 of file efr32fg14p_emu.h.

#define _EMU_PWRLOCK_LOCKKEY_SHIFT   0

Shift value for EMU_LOCKKEY

Definition at line 745 of file efr32fg14p_emu.h.

#define _EMU_PWRLOCK_LOCKKEY_UNLOCK   0x0000ADE8UL

Mode UNLOCK for EMU_PWRLOCK

Definition at line 751 of file efr32fg14p_emu.h.

#define _EMU_PWRLOCK_LOCKKEY_UNLOCKED   0x00000000UL

Mode UNLOCKED for EMU_PWRLOCK

Definition at line 749 of file efr32fg14p_emu.h.

#define _EMU_PWRLOCK_MASK   0x0000FFFFUL

Mask for EMU_PWRLOCK

Definition at line 744 of file efr32fg14p_emu.h.

#define _EMU_PWRLOCK_RESETVALUE   0x00000000UL

Default value for EMU_PWRLOCK

Definition at line 743 of file efr32fg14p_emu.h.

#define _EMU_RAM0CTRL_MASK   0x00000000UL

Mask for EMU_RAM0CTRL

Definition at line 238 of file efr32fg14p_emu.h.

Referenced by EMU_MemPwrDown().

#define _EMU_RAM0CTRL_RESETVALUE   0x00000000UL

Default value for EMU_RAM0CTRL

Definition at line 237 of file efr32fg14p_emu.h.

#define _EMU_RAM1CTRL_MASK   0x00000001UL

Mask for EMU_RAM1CTRL

Definition at line 1123 of file efr32fg14p_emu.h.

#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK   0x00000001UL

Mode BLK for EMU_RAM1CTRL

Definition at line 1128 of file efr32fg14p_emu.h.

#define _EMU_RAM1CTRL_RAMPOWERDOWN_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_RAM1CTRL

Definition at line 1126 of file efr32fg14p_emu.h.

#define _EMU_RAM1CTRL_RAMPOWERDOWN_MASK   0x1UL

Bit mask for EMU_RAMPOWERDOWN

Definition at line 1125 of file efr32fg14p_emu.h.

#define _EMU_RAM1CTRL_RAMPOWERDOWN_NONE   0x00000000UL

Mode NONE for EMU_RAM1CTRL

Definition at line 1127 of file efr32fg14p_emu.h.

#define _EMU_RAM1CTRL_RAMPOWERDOWN_SHIFT   0

Shift value for EMU_RAMPOWERDOWN

Definition at line 1124 of file efr32fg14p_emu.h.

#define _EMU_RAM1CTRL_RESETVALUE   0x00000000UL

Default value for EMU_RAM1CTRL

Definition at line 1122 of file efr32fg14p_emu.h.

#define _EMU_RAM2CTRL_MASK   0x00000001UL

Mask for EMU_RAM2CTRL

Definition at line 1135 of file efr32fg14p_emu.h.

#define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK   0x00000001UL

Mode BLK for EMU_RAM2CTRL

Definition at line 1140 of file efr32fg14p_emu.h.

#define _EMU_RAM2CTRL_RAMPOWERDOWN_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_RAM2CTRL

Definition at line 1138 of file efr32fg14p_emu.h.

#define _EMU_RAM2CTRL_RAMPOWERDOWN_MASK   0x1UL

Bit mask for EMU_RAMPOWERDOWN

Definition at line 1137 of file efr32fg14p_emu.h.

#define _EMU_RAM2CTRL_RAMPOWERDOWN_NONE   0x00000000UL

Mode NONE for EMU_RAM2CTRL

Definition at line 1139 of file efr32fg14p_emu.h.

#define _EMU_RAM2CTRL_RAMPOWERDOWN_SHIFT   0

Shift value for EMU_RAMPOWERDOWN

Definition at line 1136 of file efr32fg14p_emu.h.

#define _EMU_RAM2CTRL_RESETVALUE   0x00000000UL

Default value for EMU_RAM2CTRL

Definition at line 1134 of file efr32fg14p_emu.h.

#define _EMU_STATUS_EM4IORET_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_STATUS

Definition at line 208 of file efr32fg14p_emu.h.

#define _EMU_STATUS_EM4IORET_DISABLED   0x00000000UL

Mode DISABLED for EMU_STATUS

Definition at line 209 of file efr32fg14p_emu.h.

#define _EMU_STATUS_EM4IORET_ENABLED   0x00000001UL

Mode ENABLED for EMU_STATUS

Definition at line 210 of file efr32fg14p_emu.h.

#define _EMU_STATUS_EM4IORET_MASK   0x100000UL

Bit mask for EMU_EM4IORET

Definition at line 207 of file efr32fg14p_emu.h.

#define _EMU_STATUS_EM4IORET_SHIFT   20

Shift value for EMU_EM4IORET

Definition at line 206 of file efr32fg14p_emu.h.

#define _EMU_STATUS_MASK   0x0417011FUL

Mask for EMU_STATUS

Definition at line 159 of file efr32fg14p_emu.h.

#define _EMU_STATUS_RESETVALUE   0x00000000UL

Default value for EMU_STATUS

Definition at line 158 of file efr32fg14p_emu.h.

#define _EMU_STATUS_TEMPACTIVE_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_STATUS

Definition at line 217 of file efr32fg14p_emu.h.

#define _EMU_STATUS_TEMPACTIVE_MASK   0x4000000UL

Bit mask for EMU_TEMPACTIVE

Definition at line 216 of file efr32fg14p_emu.h.

#define _EMU_STATUS_TEMPACTIVE_SHIFT   26

Shift value for EMU_TEMPACTIVE

Definition at line 215 of file efr32fg14p_emu.h.

#define _EMU_STATUS_VMONALTAVDD_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_STATUS

Definition at line 173 of file efr32fg14p_emu.h.

#define _EMU_STATUS_VMONALTAVDD_MASK   0x4UL

Bit mask for EMU_VMONALTAVDD

Definition at line 172 of file efr32fg14p_emu.h.

#define _EMU_STATUS_VMONALTAVDD_SHIFT   2

Shift value for EMU_VMONALTAVDD

Definition at line 171 of file efr32fg14p_emu.h.

Referenced by EMU_VmonChannelStatusGet().

#define _EMU_STATUS_VMONAVDD_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_STATUS

Definition at line 168 of file efr32fg14p_emu.h.

#define _EMU_STATUS_VMONAVDD_MASK   0x2UL

Bit mask for EMU_VMONAVDD

Definition at line 167 of file efr32fg14p_emu.h.

#define _EMU_STATUS_VMONAVDD_SHIFT   1

Shift value for EMU_VMONAVDD

Definition at line 166 of file efr32fg14p_emu.h.

Referenced by EMU_VmonChannelStatusGet().

#define _EMU_STATUS_VMONDVDD_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_STATUS

Definition at line 178 of file efr32fg14p_emu.h.

#define _EMU_STATUS_VMONDVDD_MASK   0x8UL

Bit mask for EMU_VMONDVDD

Definition at line 177 of file efr32fg14p_emu.h.

#define _EMU_STATUS_VMONDVDD_SHIFT   3

Shift value for EMU_VMONDVDD

Definition at line 176 of file efr32fg14p_emu.h.

Referenced by EMU_VmonChannelStatusGet().

#define _EMU_STATUS_VMONFVDD_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_STATUS

Definition at line 188 of file efr32fg14p_emu.h.

#define _EMU_STATUS_VMONFVDD_MASK   0x100UL

Bit mask for EMU_VMONFVDD

Definition at line 187 of file efr32fg14p_emu.h.

#define _EMU_STATUS_VMONFVDD_SHIFT   8

Shift value for EMU_VMONFVDD

Definition at line 186 of file efr32fg14p_emu.h.

#define _EMU_STATUS_VMONIO0_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_STATUS

Definition at line 183 of file efr32fg14p_emu.h.

#define _EMU_STATUS_VMONIO0_MASK   0x10UL

Bit mask for EMU_VMONIO0

Definition at line 182 of file efr32fg14p_emu.h.

#define _EMU_STATUS_VMONIO0_SHIFT   4

Shift value for EMU_VMONIO0

Definition at line 181 of file efr32fg14p_emu.h.

Referenced by EMU_VmonChannelStatusGet().

#define _EMU_STATUS_VMONRDY_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_STATUS

Definition at line 163 of file efr32fg14p_emu.h.

#define _EMU_STATUS_VMONRDY_MASK   0x1UL

Bit mask for EMU_VMONRDY

Definition at line 162 of file efr32fg14p_emu.h.

#define _EMU_STATUS_VMONRDY_SHIFT   0

Shift value for EMU_VMONRDY

Definition at line 161 of file efr32fg14p_emu.h.

Referenced by EMU_VmonStatusGet().

#define _EMU_STATUS_VSCALE_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_STATUS

Definition at line 192 of file efr32fg14p_emu.h.

#define _EMU_STATUS_VSCALE_MASK   0x30000UL

Bit mask for EMU_VSCALE

Definition at line 191 of file efr32fg14p_emu.h.

Referenced by EMU_VScaleGet(), MSC_ErasePage(), and MSC_Init().

#define _EMU_STATUS_VSCALE_RESV   0x00000003UL

Mode RESV for EMU_STATUS

Definition at line 195 of file efr32fg14p_emu.h.

#define _EMU_STATUS_VSCALE_SHIFT   16

Shift value for EMU_VSCALE

Definition at line 190 of file efr32fg14p_emu.h.

Referenced by EMU_VScaleGet().

#define _EMU_STATUS_VSCALE_VSCALE0   0x00000002UL

Mode VSCALE0 for EMU_STATUS

Definition at line 194 of file efr32fg14p_emu.h.

#define _EMU_STATUS_VSCALE_VSCALE2   0x00000000UL

Mode VSCALE2 for EMU_STATUS

Definition at line 193 of file efr32fg14p_emu.h.

#define _EMU_STATUS_VSCALEBUSY_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_STATUS

Definition at line 203 of file efr32fg14p_emu.h.

#define _EMU_STATUS_VSCALEBUSY_MASK   0x40000UL

Bit mask for EMU_VSCALEBUSY

Definition at line 202 of file efr32fg14p_emu.h.

Referenced by MSC_ErasePage(), and MSC_Init().

#define _EMU_STATUS_VSCALEBUSY_SHIFT   18

Shift value for EMU_VSCALEBUSY

Definition at line 201 of file efr32fg14p_emu.h.

Referenced by EMU_VScaleWait().

#define _EMU_TEMP_MASK   0x000000FFUL

Mask for EMU_TEMP

Definition at line 320 of file efr32fg14p_emu.h.

#define _EMU_TEMP_RESETVALUE   0x00000000UL

Default value for EMU_TEMP

Definition at line 319 of file efr32fg14p_emu.h.

#define _EMU_TEMP_TEMP_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_TEMP

Definition at line 323 of file efr32fg14p_emu.h.

#define _EMU_TEMP_TEMP_MASK   0xFFUL

Bit mask for EMU_TEMP

Definition at line 322 of file efr32fg14p_emu.h.

#define _EMU_TEMP_TEMP_SHIFT   0

Shift value for EMU_TEMP

Definition at line 321 of file efr32fg14p_emu.h.

#define _EMU_TEMPLIMITS_EM4WUEN_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_TEMPLIMITS

Definition at line 315 of file efr32fg14p_emu.h.

#define _EMU_TEMPLIMITS_EM4WUEN_MASK   0x10000UL

Bit mask for EMU_EM4WUEN

Definition at line 314 of file efr32fg14p_emu.h.

#define _EMU_TEMPLIMITS_EM4WUEN_SHIFT   16

Shift value for EMU_EM4WUEN

Definition at line 313 of file efr32fg14p_emu.h.

#define _EMU_TEMPLIMITS_MASK   0x0001FFFFUL

Mask for EMU_TEMPLIMITS

Definition at line 303 of file efr32fg14p_emu.h.

#define _EMU_TEMPLIMITS_RESETVALUE   0x0000FF00UL

Default value for EMU_TEMPLIMITS

Definition at line 302 of file efr32fg14p_emu.h.

#define _EMU_TEMPLIMITS_TEMPHIGH_DEFAULT   0x000000FFUL

Mode DEFAULT for EMU_TEMPLIMITS

Definition at line 310 of file efr32fg14p_emu.h.

#define _EMU_TEMPLIMITS_TEMPHIGH_MASK   0xFF00UL

Bit mask for EMU_TEMPHIGH

Definition at line 309 of file efr32fg14p_emu.h.

Referenced by updateInterrupts().

#define _EMU_TEMPLIMITS_TEMPHIGH_SHIFT   8

Shift value for EMU_TEMPHIGH

Definition at line 308 of file efr32fg14p_emu.h.

Referenced by updateInterrupts().

#define _EMU_TEMPLIMITS_TEMPLOW_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_TEMPLIMITS

Definition at line 306 of file efr32fg14p_emu.h.

#define _EMU_TEMPLIMITS_TEMPLOW_MASK   0xFFUL

Bit mask for EMU_TEMPLOW

Definition at line 305 of file efr32fg14p_emu.h.

Referenced by updateInterrupts().

#define _EMU_TEMPLIMITS_TEMPLOW_SHIFT   0

Shift value for EMU_TEMPLOW

Definition at line 304 of file efr32fg14p_emu.h.

Referenced by updateInterrupts().

#define _EMU_VMONALTAVDDCTRL_EN_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_VMONALTAVDDCTRL

Definition at line 1041 of file efr32fg14p_emu.h.

#define _EMU_VMONALTAVDDCTRL_EN_MASK   0x1UL

Bit mask for EMU_EN

Definition at line 1040 of file efr32fg14p_emu.h.

#define _EMU_VMONALTAVDDCTRL_EN_SHIFT   0

Shift value for EMU_EN

Definition at line 1039 of file efr32fg14p_emu.h.

Referenced by EMU_VmonEnable().

#define _EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_VMONALTAVDDCTRL

Definition at line 1051 of file efr32fg14p_emu.h.

#define _EMU_VMONALTAVDDCTRL_FALLWU_MASK   0x8UL

Bit mask for EMU_FALLWU

Definition at line 1050 of file efr32fg14p_emu.h.

#define _EMU_VMONALTAVDDCTRL_FALLWU_SHIFT   3

Shift value for EMU_FALLWU

Definition at line 1049 of file efr32fg14p_emu.h.

#define _EMU_VMONALTAVDDCTRL_MASK   0x0000FF0DUL

Mask for EMU_VMONALTAVDDCTRL

Definition at line 1037 of file efr32fg14p_emu.h.

#define _EMU_VMONALTAVDDCTRL_RESETVALUE   0x00000000UL

Default value for EMU_VMONALTAVDDCTRL

Definition at line 1036 of file efr32fg14p_emu.h.

#define _EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_VMONALTAVDDCTRL

Definition at line 1046 of file efr32fg14p_emu.h.

#define _EMU_VMONALTAVDDCTRL_RISEWU_MASK   0x4UL

Bit mask for EMU_RISEWU

Definition at line 1045 of file efr32fg14p_emu.h.

#define _EMU_VMONALTAVDDCTRL_RISEWU_SHIFT   2

Shift value for EMU_RISEWU

Definition at line 1044 of file efr32fg14p_emu.h.

#define _EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_VMONALTAVDDCTRL

Definition at line 1059 of file efr32fg14p_emu.h.

#define _EMU_VMONALTAVDDCTRL_THRESCOARSE_MASK   0xF000UL

Bit mask for EMU_THRESCOARSE

Definition at line 1058 of file efr32fg14p_emu.h.

#define _EMU_VMONALTAVDDCTRL_THRESCOARSE_SHIFT   12

Shift value for EMU_THRESCOARSE

Definition at line 1057 of file efr32fg14p_emu.h.

Referenced by EMU_VmonInit().

#define _EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_VMONALTAVDDCTRL

Definition at line 1055 of file efr32fg14p_emu.h.

#define _EMU_VMONALTAVDDCTRL_THRESFINE_MASK   0xF00UL

Bit mask for EMU_THRESFINE

Definition at line 1054 of file efr32fg14p_emu.h.

#define _EMU_VMONALTAVDDCTRL_THRESFINE_SHIFT   8

Shift value for EMU_THRESFINE

Definition at line 1053 of file efr32fg14p_emu.h.

Referenced by EMU_VmonInit().

#define _EMU_VMONAVDDCTRL_EN_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_VMONAVDDCTRL

Definition at line 1006 of file efr32fg14p_emu.h.

#define _EMU_VMONAVDDCTRL_EN_MASK   0x1UL

Bit mask for EMU_EN

Definition at line 1005 of file efr32fg14p_emu.h.

#define _EMU_VMONAVDDCTRL_EN_SHIFT   0

Shift value for EMU_EN

Definition at line 1004 of file efr32fg14p_emu.h.

Referenced by EMU_VmonEnable().

#define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_VMONAVDDCTRL

Definition at line 1024 of file efr32fg14p_emu.h.

#define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_MASK   0xF000UL

Bit mask for EMU_FALLTHRESCOARSE

Definition at line 1023 of file efr32fg14p_emu.h.

#define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_SHIFT   12

Shift value for EMU_FALLTHRESCOARSE

Definition at line 1022 of file efr32fg14p_emu.h.

Referenced by EMU_VmonHystInit(), and EMU_VmonInit().

#define _EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_VMONAVDDCTRL

Definition at line 1020 of file efr32fg14p_emu.h.

#define _EMU_VMONAVDDCTRL_FALLTHRESFINE_MASK   0xF00UL

Bit mask for EMU_FALLTHRESFINE

Definition at line 1019 of file efr32fg14p_emu.h.

#define _EMU_VMONAVDDCTRL_FALLTHRESFINE_SHIFT   8

Shift value for EMU_FALLTHRESFINE

Definition at line 1018 of file efr32fg14p_emu.h.

Referenced by EMU_VmonHystInit(), and EMU_VmonInit().

#define _EMU_VMONAVDDCTRL_FALLWU_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_VMONAVDDCTRL

Definition at line 1016 of file efr32fg14p_emu.h.

#define _EMU_VMONAVDDCTRL_FALLWU_MASK   0x8UL

Bit mask for EMU_FALLWU

Definition at line 1015 of file efr32fg14p_emu.h.

#define _EMU_VMONAVDDCTRL_FALLWU_SHIFT   3

Shift value for EMU_FALLWU

Definition at line 1014 of file efr32fg14p_emu.h.

#define _EMU_VMONAVDDCTRL_MASK   0x00FFFF0DUL

Mask for EMU_VMONAVDDCTRL

Definition at line 1002 of file efr32fg14p_emu.h.

#define _EMU_VMONAVDDCTRL_RESETVALUE   0x00000000UL

Default value for EMU_VMONAVDDCTRL

Definition at line 1001 of file efr32fg14p_emu.h.

#define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_VMONAVDDCTRL

Definition at line 1032 of file efr32fg14p_emu.h.

#define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_MASK   0xF00000UL

Bit mask for EMU_RISETHRESCOARSE

Definition at line 1031 of file efr32fg14p_emu.h.

#define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_SHIFT   20

Shift value for EMU_RISETHRESCOARSE

Definition at line 1030 of file efr32fg14p_emu.h.

Referenced by EMU_VmonHystInit(), and EMU_VmonInit().

#define _EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_VMONAVDDCTRL

Definition at line 1028 of file efr32fg14p_emu.h.

#define _EMU_VMONAVDDCTRL_RISETHRESFINE_MASK   0xF0000UL

Bit mask for EMU_RISETHRESFINE

Definition at line 1027 of file efr32fg14p_emu.h.

#define _EMU_VMONAVDDCTRL_RISETHRESFINE_SHIFT   16

Shift value for EMU_RISETHRESFINE

Definition at line 1026 of file efr32fg14p_emu.h.

Referenced by EMU_VmonHystInit(), and EMU_VmonInit().

#define _EMU_VMONAVDDCTRL_RISEWU_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_VMONAVDDCTRL

Definition at line 1011 of file efr32fg14p_emu.h.

#define _EMU_VMONAVDDCTRL_RISEWU_MASK   0x4UL

Bit mask for EMU_RISEWU

Definition at line 1010 of file efr32fg14p_emu.h.

#define _EMU_VMONAVDDCTRL_RISEWU_SHIFT   2

Shift value for EMU_RISEWU

Definition at line 1009 of file efr32fg14p_emu.h.

#define _EMU_VMONDVDDCTRL_EN_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_VMONDVDDCTRL

Definition at line 1068 of file efr32fg14p_emu.h.

#define _EMU_VMONDVDDCTRL_EN_MASK   0x1UL

Bit mask for EMU_EN

Definition at line 1067 of file efr32fg14p_emu.h.

#define _EMU_VMONDVDDCTRL_EN_SHIFT   0

Shift value for EMU_EN

Definition at line 1066 of file efr32fg14p_emu.h.

Referenced by EMU_VmonEnable().

#define _EMU_VMONDVDDCTRL_FALLWU_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_VMONDVDDCTRL

Definition at line 1078 of file efr32fg14p_emu.h.

#define _EMU_VMONDVDDCTRL_FALLWU_MASK   0x8UL

Bit mask for EMU_FALLWU

Definition at line 1077 of file efr32fg14p_emu.h.

#define _EMU_VMONDVDDCTRL_FALLWU_SHIFT   3

Shift value for EMU_FALLWU

Definition at line 1076 of file efr32fg14p_emu.h.

#define _EMU_VMONDVDDCTRL_MASK   0x0000FF0DUL

Mask for EMU_VMONDVDDCTRL

Definition at line 1064 of file efr32fg14p_emu.h.

#define _EMU_VMONDVDDCTRL_RESETVALUE   0x00000000UL

Default value for EMU_VMONDVDDCTRL

Definition at line 1063 of file efr32fg14p_emu.h.

#define _EMU_VMONDVDDCTRL_RISEWU_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_VMONDVDDCTRL

Definition at line 1073 of file efr32fg14p_emu.h.

#define _EMU_VMONDVDDCTRL_RISEWU_MASK   0x4UL

Bit mask for EMU_RISEWU

Definition at line 1072 of file efr32fg14p_emu.h.

#define _EMU_VMONDVDDCTRL_RISEWU_SHIFT   2

Shift value for EMU_RISEWU

Definition at line 1071 of file efr32fg14p_emu.h.

#define _EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_VMONDVDDCTRL

Definition at line 1086 of file efr32fg14p_emu.h.

#define _EMU_VMONDVDDCTRL_THRESCOARSE_MASK   0xF000UL

Bit mask for EMU_THRESCOARSE

Definition at line 1085 of file efr32fg14p_emu.h.

#define _EMU_VMONDVDDCTRL_THRESCOARSE_SHIFT   12

Shift value for EMU_THRESCOARSE

Definition at line 1084 of file efr32fg14p_emu.h.

Referenced by EMU_VmonInit().

#define _EMU_VMONDVDDCTRL_THRESFINE_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_VMONDVDDCTRL

Definition at line 1082 of file efr32fg14p_emu.h.

#define _EMU_VMONDVDDCTRL_THRESFINE_MASK   0xF00UL

Bit mask for EMU_THRESFINE

Definition at line 1081 of file efr32fg14p_emu.h.

#define _EMU_VMONDVDDCTRL_THRESFINE_SHIFT   8

Shift value for EMU_THRESFINE

Definition at line 1080 of file efr32fg14p_emu.h.

Referenced by EMU_VmonInit().

#define _EMU_VMONIO0CTRL_EN_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_VMONIO0CTRL

Definition at line 1095 of file efr32fg14p_emu.h.

#define _EMU_VMONIO0CTRL_EN_MASK   0x1UL

Bit mask for EMU_EN

Definition at line 1094 of file efr32fg14p_emu.h.

#define _EMU_VMONIO0CTRL_EN_SHIFT   0

Shift value for EMU_EN

Definition at line 1093 of file efr32fg14p_emu.h.

Referenced by EMU_VmonEnable().

#define _EMU_VMONIO0CTRL_FALLWU_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_VMONIO0CTRL

Definition at line 1105 of file efr32fg14p_emu.h.

#define _EMU_VMONIO0CTRL_FALLWU_MASK   0x8UL

Bit mask for EMU_FALLWU

Definition at line 1104 of file efr32fg14p_emu.h.

#define _EMU_VMONIO0CTRL_FALLWU_SHIFT   3

Shift value for EMU_FALLWU

Definition at line 1103 of file efr32fg14p_emu.h.

#define _EMU_VMONIO0CTRL_MASK   0x0000FF1DUL

Mask for EMU_VMONIO0CTRL

Definition at line 1091 of file efr32fg14p_emu.h.

#define _EMU_VMONIO0CTRL_RESETVALUE   0x00000000UL

Default value for EMU_VMONIO0CTRL

Definition at line 1090 of file efr32fg14p_emu.h.

#define _EMU_VMONIO0CTRL_RETDIS_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_VMONIO0CTRL

Definition at line 1110 of file efr32fg14p_emu.h.

#define _EMU_VMONIO0CTRL_RETDIS_MASK   0x10UL

Bit mask for EMU_RETDIS

Definition at line 1109 of file efr32fg14p_emu.h.

#define _EMU_VMONIO0CTRL_RETDIS_SHIFT   4

Shift value for EMU_RETDIS

Definition at line 1108 of file efr32fg14p_emu.h.

#define _EMU_VMONIO0CTRL_RISEWU_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_VMONIO0CTRL

Definition at line 1100 of file efr32fg14p_emu.h.

#define _EMU_VMONIO0CTRL_RISEWU_MASK   0x4UL

Bit mask for EMU_RISEWU

Definition at line 1099 of file efr32fg14p_emu.h.

#define _EMU_VMONIO0CTRL_RISEWU_SHIFT   2

Shift value for EMU_RISEWU

Definition at line 1098 of file efr32fg14p_emu.h.

#define _EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_VMONIO0CTRL

Definition at line 1118 of file efr32fg14p_emu.h.

#define _EMU_VMONIO0CTRL_THRESCOARSE_MASK   0xF000UL

Bit mask for EMU_THRESCOARSE

Definition at line 1117 of file efr32fg14p_emu.h.

#define _EMU_VMONIO0CTRL_THRESCOARSE_SHIFT   12

Shift value for EMU_THRESCOARSE

Definition at line 1116 of file efr32fg14p_emu.h.

Referenced by EMU_VmonInit().

#define _EMU_VMONIO0CTRL_THRESFINE_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_VMONIO0CTRL

Definition at line 1114 of file efr32fg14p_emu.h.

#define _EMU_VMONIO0CTRL_THRESFINE_MASK   0xF00UL

Bit mask for EMU_THRESFINE

Definition at line 1113 of file efr32fg14p_emu.h.

#define _EMU_VMONIO0CTRL_THRESFINE_SHIFT   8

Shift value for EMU_THRESFINE

Definition at line 1112 of file efr32fg14p_emu.h.

Referenced by EMU_VmonInit().

#define EMU_CMD_EM01VSCALE0   (0x1UL << 4)

EM01 Voltage Scale Command to Scale to Voltage Scale Level 0

Definition at line 248 of file efr32fg14p_emu.h.

#define EMU_CMD_EM01VSCALE0_DEFAULT   (_EMU_CMD_EM01VSCALE0_DEFAULT << 4)

Shifted mode DEFAULT for EMU_CMD

Definition at line 252 of file efr32fg14p_emu.h.

#define EMU_CMD_EM01VSCALE2   (0x1UL << 6)

EM01 Voltage Scale Command to Scale to Voltage Scale Level 2

Definition at line 253 of file efr32fg14p_emu.h.

#define EMU_CMD_EM01VSCALE2_DEFAULT   (_EMU_CMD_EM01VSCALE2_DEFAULT << 6)

Shifted mode DEFAULT for EMU_CMD

Definition at line 257 of file efr32fg14p_emu.h.

#define EMU_CMD_EM4UNLATCH   (0x1UL << 0)

EM4 Unlatch

Definition at line 243 of file efr32fg14p_emu.h.

Referenced by EMU_UnlatchPinRetention().

#define EMU_CMD_EM4UNLATCH_DEFAULT   (_EMU_CMD_EM4UNLATCH_DEFAULT << 0)

Shifted mode DEFAULT for EMU_CMD

Definition at line 247 of file efr32fg14p_emu.h.

#define EMU_CTRL_EM01LD   (0x1UL << 3)

Reserved for internal use. Do not change.

Definition at line 126 of file efr32fg14p_emu.h.

#define EMU_CTRL_EM01LD_DEFAULT   (_EMU_CTRL_EM01LD_DEFAULT << 3)

Shifted mode DEFAULT for EMU_CTRL

Definition at line 130 of file efr32fg14p_emu.h.

#define EMU_CTRL_EM23VSCALE_DEFAULT   (_EMU_CTRL_EM23VSCALE_DEFAULT << 8)

Shifted mode DEFAULT for EMU_CTRL

Definition at line 142 of file efr32fg14p_emu.h.

#define EMU_CTRL_EM23VSCALE_RESV   (_EMU_CTRL_EM23VSCALE_RESV << 8)

Shifted mode RESV for EMU_CTRL

Definition at line 145 of file efr32fg14p_emu.h.

#define EMU_CTRL_EM23VSCALE_VSCALE0   (_EMU_CTRL_EM23VSCALE_VSCALE0 << 8)

Shifted mode VSCALE0 for EMU_CTRL

Definition at line 144 of file efr32fg14p_emu.h.

#define EMU_CTRL_EM23VSCALE_VSCALE2   (_EMU_CTRL_EM23VSCALE_VSCALE2 << 8)

Shifted mode VSCALE2 for EMU_CTRL

Definition at line 143 of file efr32fg14p_emu.h.

#define EMU_CTRL_EM23VSCALEAUTOWSEN   (0x1UL << 4)

Automatically Configures Flash, Ram and Frequency to Wakeup From EM2 or EM3 at Low Voltage

Definition at line 131 of file efr32fg14p_emu.h.

#define EMU_CTRL_EM23VSCALEAUTOWSEN_DEFAULT   (_EMU_CTRL_EM23VSCALEAUTOWSEN_DEFAULT << 4)

Shifted mode DEFAULT for EMU_CTRL

Definition at line 135 of file efr32fg14p_emu.h.

#define EMU_CTRL_EM2BLOCK   (0x1UL << 1)

Energy Mode 2 Block

Definition at line 116 of file efr32fg14p_emu.h.

#define EMU_CTRL_EM2BLOCK_DEFAULT   (_EMU_CTRL_EM2BLOCK_DEFAULT << 1)

Shifted mode DEFAULT for EMU_CTRL

Definition at line 120 of file efr32fg14p_emu.h.

#define EMU_CTRL_EM2BODDIS   (0x1UL << 2)

Disable BOD in EM2

Definition at line 121 of file efr32fg14p_emu.h.

#define EMU_CTRL_EM2BODDIS_DEFAULT   (_EMU_CTRL_EM2BODDIS_DEFAULT << 2)

Shifted mode DEFAULT for EMU_CTRL

Definition at line 125 of file efr32fg14p_emu.h.

#define EMU_CTRL_EM4HVSCALE_DEFAULT   (_EMU_CTRL_EM4HVSCALE_DEFAULT << 16)

Shifted mode DEFAULT for EMU_CTRL

Definition at line 152 of file efr32fg14p_emu.h.

#define EMU_CTRL_EM4HVSCALE_RESV   (_EMU_CTRL_EM4HVSCALE_RESV << 16)

Shifted mode RESV for EMU_CTRL

Definition at line 155 of file efr32fg14p_emu.h.

#define EMU_CTRL_EM4HVSCALE_VSCALE0   (_EMU_CTRL_EM4HVSCALE_VSCALE0 << 16)

Shifted mode VSCALE0 for EMU_CTRL

Definition at line 154 of file efr32fg14p_emu.h.

#define EMU_CTRL_EM4HVSCALE_VSCALE2   (_EMU_CTRL_EM4HVSCALE_VSCALE2 << 16)

Shifted mode VSCALE2 for EMU_CTRL

Definition at line 153 of file efr32fg14p_emu.h.

#define EMU_DCDCCLIMCTRL_BYPLIMEN   (0x1UL << 13)

Bypass Current Limit Enable

Definition at line 894 of file efr32fg14p_emu.h.

#define EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT   (_EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT << 13)

Shifted mode DEFAULT for EMU_DCDCCLIMCTRL

Definition at line 898 of file efr32fg14p_emu.h.

#define EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT   (_EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT << 8)

Shifted mode DEFAULT for EMU_DCDCCLIMCTRL

Definition at line 893 of file efr32fg14p_emu.h.

#define EMU_DCDCCTRL_DCDCMODE_BYPASS   (_EMU_DCDCCTRL_DCDCMODE_BYPASS << 0)

Shifted mode BYPASS for EMU_DCDCCTRL

Definition at line 795 of file efr32fg14p_emu.h.

Referenced by EMU_DCDCModeSet().

#define EMU_DCDCCTRL_DCDCMODE_DEFAULT   (_EMU_DCDCCTRL_DCDCMODE_DEFAULT << 0)

Shifted mode DEFAULT for EMU_DCDCCTRL

Definition at line 798 of file efr32fg14p_emu.h.

#define EMU_DCDCCTRL_DCDCMODE_LOWNOISE   (_EMU_DCDCCTRL_DCDCMODE_LOWNOISE << 0)

Shifted mode LOWNOISE for EMU_DCDCCTRL

Definition at line 796 of file efr32fg14p_emu.h.

Referenced by EMU_DCDCModeSet(), and EMU_EnterEM4().

#define EMU_DCDCCTRL_DCDCMODE_LOWPOWER   (_EMU_DCDCCTRL_DCDCMODE_LOWPOWER << 0)

Shifted mode LOWPOWER for EMU_DCDCCTRL

Definition at line 797 of file efr32fg14p_emu.h.

Referenced by EMU_EnterEM4().

#define EMU_DCDCCTRL_DCDCMODE_OFF   (_EMU_DCDCCTRL_DCDCMODE_OFF << 0)

Shifted mode OFF for EMU_DCDCCTRL

Definition at line 799 of file efr32fg14p_emu.h.

Referenced by EMU_DCDCModeSet(), and EMU_DCDCPowerOff().

#define EMU_DCDCCTRL_DCDCMODEEM23   (0x1UL << 4)

DCDC Mode EM23

Definition at line 800 of file efr32fg14p_emu.h.

#define EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT   (_EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT << 4)

Shifted mode DEFAULT for EMU_DCDCCTRL

Definition at line 807 of file efr32fg14p_emu.h.

#define EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER   (_EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER << 4)

Shifted mode EM23LOWPOWER for EMU_DCDCCTRL

Definition at line 808 of file efr32fg14p_emu.h.

#define EMU_DCDCCTRL_DCDCMODEEM23_EM23SW   (_EMU_DCDCCTRL_DCDCMODEEM23_EM23SW << 4)

Shifted mode EM23SW for EMU_DCDCCTRL

Definition at line 806 of file efr32fg14p_emu.h.

#define EMU_DCDCCTRL_DCDCMODEEM4   (0x1UL << 5)

DCDC Mode EM4H

Definition at line 809 of file efr32fg14p_emu.h.

#define EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT   (_EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT << 5)

Shifted mode DEFAULT for EMU_DCDCCTRL

Definition at line 816 of file efr32fg14p_emu.h.

#define EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER   (_EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER << 5)

Shifted mode EM4LOWPOWER for EMU_DCDCCTRL

Definition at line 817 of file efr32fg14p_emu.h.

#define EMU_DCDCCTRL_DCDCMODEEM4_EM4SW   (_EMU_DCDCCTRL_DCDCMODEEM4_EM4SW << 5)

Shifted mode EM4SW for EMU_DCDCCTRL

Definition at line 815 of file efr32fg14p_emu.h.

#define EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT   (_EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT << 20)

Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL

Definition at line 918 of file efr32fg14p_emu.h.

#define EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT   (_EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT << 24)

Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL

Definition at line 922 of file efr32fg14p_emu.h.

#define EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT   (_EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT << 28)

Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL

Definition at line 926 of file efr32fg14p_emu.h.

#define EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT   (_EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT << 0)

Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL

Definition at line 906 of file efr32fg14p_emu.h.

#define EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT   (_EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT << 4)

Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL

Definition at line 910 of file efr32fg14p_emu.h.

#define EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT   (_EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT << 12)

Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL

Definition at line 914 of file efr32fg14p_emu.h.

#define EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT   (_EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT << 0)

Shifted mode DEFAULT for EMU_DCDCLNFREQCTRL

Definition at line 985 of file efr32fg14p_emu.h.

#define EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT   (_EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT << 24)

Shifted mode DEFAULT for EMU_DCDCLNFREQCTRL

Definition at line 989 of file efr32fg14p_emu.h.

#define EMU_DCDCLNVCTRL_LNATT   (0x1UL << 1)

Low Noise Mode Feedback Attenuation

Definition at line 931 of file efr32fg14p_emu.h.

Referenced by EMU_DCDCOutputVoltageSet().

#define EMU_DCDCLNVCTRL_LNATT_DEFAULT   (_EMU_DCDCLNVCTRL_LNATT_DEFAULT << 1)

Shifted mode DEFAULT for EMU_DCDCLNVCTRL

Definition at line 937 of file efr32fg14p_emu.h.

#define EMU_DCDCLNVCTRL_LNATT_DIV3   (_EMU_DCDCLNVCTRL_LNATT_DIV3 << 1)

Shifted mode DIV3 for EMU_DCDCLNVCTRL

Definition at line 938 of file efr32fg14p_emu.h.

#define EMU_DCDCLNVCTRL_LNATT_DIV6   (_EMU_DCDCLNVCTRL_LNATT_DIV6 << 1)

Shifted mode DIV6 for EMU_DCDCLNVCTRL

Definition at line 939 of file efr32fg14p_emu.h.

#define EMU_DCDCLNVCTRL_LNVREF_DEFAULT   (_EMU_DCDCLNVCTRL_LNVREF_DEFAULT << 8)

Shifted mode DEFAULT for EMU_DCDCLNVCTRL

Definition at line 943 of file efr32fg14p_emu.h.

#define EMU_DCDCLPCTRL_LPBLANK_DEFAULT   (_EMU_DCDCLPCTRL_LPBLANK_DEFAULT << 25)

Shifted mode DEFAULT for EMU_DCDCLPCTRL

Definition at line 977 of file efr32fg14p_emu.h.

#define EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_DEFAULT   (_EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_DEFAULT << 12)

Shifted mode DEFAULT for EMU_DCDCLPCTRL

Definition at line 968 of file efr32fg14p_emu.h.

#define EMU_DCDCLPCTRL_LPVREFDUTYEN   (0x1UL << 24)

LP Mode Duty Cycling Enable

Definition at line 969 of file efr32fg14p_emu.h.

#define EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT   (_EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT << 24)

Shifted mode DEFAULT for EMU_DCDCLPCTRL

Definition at line 973 of file efr32fg14p_emu.h.

#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS0   (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS0 << 8)

Shifted mode BIAS0 for EMU_DCDCLPEM01CFG

Definition at line 1155 of file efr32fg14p_emu.h.

#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS1   (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS1 << 8)

Shifted mode BIAS1 for EMU_DCDCLPEM01CFG

Definition at line 1156 of file efr32fg14p_emu.h.

#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS2   (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS2 << 8)

Shifted mode BIAS2 for EMU_DCDCLPEM01CFG

Definition at line 1157 of file efr32fg14p_emu.h.

#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3   (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3 << 8)

Shifted mode BIAS3 for EMU_DCDCLPEM01CFG

Definition at line 1159 of file efr32fg14p_emu.h.

Referenced by EMU_DCDCInit().

#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_DEFAULT   (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_DEFAULT << 8)

Shifted mode DEFAULT for EMU_DCDCLPEM01CFG

Definition at line 1158 of file efr32fg14p_emu.h.

#define EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_DEFAULT   (_EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_DEFAULT << 12)

Shifted mode DEFAULT for EMU_DCDCLPEM01CFG

Definition at line 1163 of file efr32fg14p_emu.h.

#define EMU_DCDCLPVCTRL_LPATT   (0x1UL << 0)

Low Power Feedback Attenuation

Definition at line 948 of file efr32fg14p_emu.h.

Referenced by EMU_DCDCOutputVoltageSet().

#define EMU_DCDCLPVCTRL_LPATT_DEFAULT   (_EMU_DCDCLPVCTRL_LPATT_DEFAULT << 0)

Shifted mode DEFAULT for EMU_DCDCLPVCTRL

Definition at line 954 of file efr32fg14p_emu.h.

#define EMU_DCDCLPVCTRL_LPATT_DIV4   (_EMU_DCDCLPVCTRL_LPATT_DIV4 << 0)

Shifted mode DIV4 for EMU_DCDCLPVCTRL

Definition at line 955 of file efr32fg14p_emu.h.

#define EMU_DCDCLPVCTRL_LPATT_DIV8   (_EMU_DCDCLPVCTRL_LPATT_DIV8 << 0)

Shifted mode DIV8 for EMU_DCDCLPVCTRL

Definition at line 956 of file efr32fg14p_emu.h.

#define EMU_DCDCLPVCTRL_LPVREF_DEFAULT   (_EMU_DCDCLPVCTRL_LPVREF_DEFAULT << 1)

Shifted mode DEFAULT for EMU_DCDCLPVCTRL

Definition at line 960 of file efr32fg14p_emu.h.

#define EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT   (_EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT << 16)

Shifted mode DEFAULT for EMU_DCDCMISCCTRL

Definition at line 853 of file efr32fg14p_emu.h.

#define EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT   (_EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT << 24)

Shifted mode DEFAULT for EMU_DCDCMISCCTRL

Definition at line 861 of file efr32fg14p_emu.h.

#define EMU_DCDCMISCCTRL_LNFORCECCM   (0x1UL << 0)

Force DCDC Into CCM Mode in Low Noise Operation

Definition at line 822 of file efr32fg14p_emu.h.

Referenced by EMU_DCDCConductionModeSet(), and EMU_DCDCInit().

#define EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT   (_EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT << 0)

Shifted mode DEFAULT for EMU_DCDCMISCCTRL

Definition at line 826 of file efr32fg14p_emu.h.

#define EMU_DCDCMISCCTRL_LNFORCECCMIMM   (0x1UL << 5)

Force DCDC Into CCM Mode Immediately, Based on LNFORCECCM

Definition at line 837 of file efr32fg14p_emu.h.

#define EMU_DCDCMISCCTRL_LNFORCECCMIMM_DEFAULT   (_EMU_DCDCMISCCTRL_LNFORCECCMIMM_DEFAULT << 5)

Shifted mode DEFAULT for EMU_DCDCMISCCTRL

Definition at line 841 of file efr32fg14p_emu.h.

#define EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT   (_EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT << 20)

Shifted mode DEFAULT for EMU_DCDCMISCCTRL

Definition at line 857 of file efr32fg14p_emu.h.

#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS0   (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS0 << 28)

Shifted mode BIAS0 for EMU_DCDCMISCCTRL

Definition at line 870 of file efr32fg14p_emu.h.

#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS1   (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS1 << 28)

Shifted mode BIAS1 for EMU_DCDCMISCCTRL

Definition at line 871 of file efr32fg14p_emu.h.

#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS2   (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS2 << 28)

Shifted mode BIAS2 for EMU_DCDCMISCCTRL

Definition at line 872 of file efr32fg14p_emu.h.

#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS3   (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS3 << 28)

Shifted mode BIAS3 for EMU_DCDCMISCCTRL

Definition at line 873 of file efr32fg14p_emu.h.

#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_DEFAULT   (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_DEFAULT << 28)

Shifted mode DEFAULT for EMU_DCDCMISCCTRL

Definition at line 869 of file efr32fg14p_emu.h.

#define EMU_DCDCMISCCTRL_LPCMPHYSDIS   (0x1UL << 1)

Disable LP Mode Hysteresis in the State Machine Control

Definition at line 827 of file efr32fg14p_emu.h.

#define EMU_DCDCMISCCTRL_LPCMPHYSDIS_DEFAULT   (_EMU_DCDCMISCCTRL_LPCMPHYSDIS_DEFAULT << 1)

Shifted mode DEFAULT for EMU_DCDCMISCCTRL

Definition at line 831 of file efr32fg14p_emu.h.

#define EMU_DCDCMISCCTRL_LPCMPHYSHI   (0x1UL << 2)

Comparator Threshold on the High Side

Definition at line 832 of file efr32fg14p_emu.h.

#define EMU_DCDCMISCCTRL_LPCMPHYSHI_DEFAULT   (_EMU_DCDCMISCCTRL_LPCMPHYSHI_DEFAULT << 2)

Shifted mode DEFAULT for EMU_DCDCMISCCTRL

Definition at line 836 of file efr32fg14p_emu.h.

#define EMU_DCDCMISCCTRL_NFETCNT_DEFAULT   (_EMU_DCDCMISCCTRL_NFETCNT_DEFAULT << 12)

Shifted mode DEFAULT for EMU_DCDCMISCCTRL

Definition at line 849 of file efr32fg14p_emu.h.

#define EMU_DCDCMISCCTRL_PFETCNT_DEFAULT   (_EMU_DCDCMISCCTRL_PFETCNT_DEFAULT << 8)

Shifted mode DEFAULT for EMU_DCDCMISCCTRL

Definition at line 845 of file efr32fg14p_emu.h.

#define EMU_DCDCSYNC_DCDCCTRLBUSY   (0x1UL << 0)

DCDC CTRL Register Transfer Busy

Definition at line 994 of file efr32fg14p_emu.h.

Referenced by EMU_DCDCConductionModeSet(), EMU_DCDCModeSet(), and EMU_DCDCPowerOff().

#define EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT   (_EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT << 0)

Shifted mode DEFAULT for EMU_DCDCSYNC

Definition at line 998 of file efr32fg14p_emu.h.

#define EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT   (_EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT << 8)

Shifted mode DEFAULT for EMU_DCDCZDETCTRL

Definition at line 885 of file efr32fg14p_emu.h.

#define EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT   (_EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT << 4)

Shifted mode DEFAULT for EMU_DCDCZDETCTRL

Definition at line 881 of file efr32fg14p_emu.h.

#define EMU_EM23PERNORETAINCMD_ACMP0UNLOCK   (0x1UL << 0)

Clears Status Bit of ACMP0 and Unlocks Access to It

Definition at line 1168 of file efr32fg14p_emu.h.

#define EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_DEFAULT   (_EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_DEFAULT << 0)

Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD

Definition at line 1172 of file efr32fg14p_emu.h.

#define EMU_EM23PERNORETAINCMD_ACMP1UNLOCK   (0x1UL << 1)

Clears Status Bit of ACMP1 and Unlocks Access to It

Definition at line 1173 of file efr32fg14p_emu.h.

#define EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_DEFAULT   (_EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_DEFAULT << 1)

Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD

Definition at line 1177 of file efr32fg14p_emu.h.

#define EMU_EM23PERNORETAINCMD_ADC0UNLOCK   (0x1UL << 9)

Clears Status Bit of ADC0 and Unlocks Access to It

Definition at line 1198 of file efr32fg14p_emu.h.

#define EMU_EM23PERNORETAINCMD_ADC0UNLOCK_DEFAULT   (_EMU_EM23PERNORETAINCMD_ADC0UNLOCK_DEFAULT << 9)

Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD

Definition at line 1202 of file efr32fg14p_emu.h.

#define EMU_EM23PERNORETAINCMD_DAC0UNLOCK   (0x1UL << 7)

Clears Status Bit of DAC0 and Unlocks Access to It

Definition at line 1188 of file efr32fg14p_emu.h.

#define EMU_EM23PERNORETAINCMD_DAC0UNLOCK_DEFAULT   (_EMU_EM23PERNORETAINCMD_DAC0UNLOCK_DEFAULT << 7)

Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD

Definition at line 1192 of file efr32fg14p_emu.h.

#define EMU_EM23PERNORETAINCMD_I2C0UNLOCK   (0x1UL << 5)

Clears Status Bit of I2C0 and Unlocks Access to It

Definition at line 1183 of file efr32fg14p_emu.h.

#define EMU_EM23PERNORETAINCMD_I2C0UNLOCK_DEFAULT   (_EMU_EM23PERNORETAINCMD_I2C0UNLOCK_DEFAULT << 5)

Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD

Definition at line 1187 of file efr32fg14p_emu.h.

#define EMU_EM23PERNORETAINCMD_IDAC0UNLOCK   (0x1UL << 8)

Clears Status Bit of IDAC0 and Unlocks Access to It

Definition at line 1193 of file efr32fg14p_emu.h.

#define EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_DEFAULT   (_EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_DEFAULT << 8)

Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD

Definition at line 1197 of file efr32fg14p_emu.h.

#define EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK   (0x1UL << 13)

Clears Status Bit of LESENSE0 and Unlocks Access to It

Definition at line 1218 of file efr32fg14p_emu.h.

#define EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_DEFAULT   (_EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_DEFAULT << 13)

Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD

Definition at line 1222 of file efr32fg14p_emu.h.

#define EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK   (0x1UL << 10)

Clears Status Bit of LETIMER0 and Unlocks Access to It

Definition at line 1203 of file efr32fg14p_emu.h.

#define EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_DEFAULT   (_EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_DEFAULT << 10)

Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD

Definition at line 1207 of file efr32fg14p_emu.h.

#define EMU_EM23PERNORETAINCMD_LEUART0UNLOCK   (0x1UL << 15)

Clears Status Bit of LEUART0 and Unlocks Access to It

Definition at line 1223 of file efr32fg14p_emu.h.

#define EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_DEFAULT   (_EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_DEFAULT << 15)

Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD

Definition at line 1227 of file efr32fg14p_emu.h.

#define EMU_EM23PERNORETAINCMD_PCNT0UNLOCK   (0x1UL << 2)

Clears Status Bit of PCNT0 and Unlocks Access to It

Definition at line 1178 of file efr32fg14p_emu.h.

#define EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_DEFAULT   (_EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_DEFAULT << 2)

Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD

Definition at line 1182 of file efr32fg14p_emu.h.

#define EMU_EM23PERNORETAINCMD_WDOG0UNLOCK   (0x1UL << 11)

Clears Status Bit of WDOG0 and Unlocks Access to It

Definition at line 1208 of file efr32fg14p_emu.h.

#define EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_DEFAULT   (_EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_DEFAULT << 11)

Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD

Definition at line 1212 of file efr32fg14p_emu.h.

#define EMU_EM23PERNORETAINCMD_WDOG1UNLOCK   (0x1UL << 12)

Clears Status Bit of WDOG1 and Unlocks Access to It

Definition at line 1213 of file efr32fg14p_emu.h.

#define EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_DEFAULT   (_EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_DEFAULT << 12)

Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD

Definition at line 1217 of file efr32fg14p_emu.h.

#define EMU_EM23PERNORETAINCTRL_ACMP0DIS   (0x1UL << 0)

Allow Power Down of ACMP0 During EM23

Definition at line 1296 of file efr32fg14p_emu.h.

#define EMU_EM23PERNORETAINCTRL_ACMP0DIS_DEFAULT   (_EMU_EM23PERNORETAINCTRL_ACMP0DIS_DEFAULT << 0)

Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL

Definition at line 1300 of file efr32fg14p_emu.h.

#define EMU_EM23PERNORETAINCTRL_ACMP1DIS   (0x1UL << 1)

Allow Power Down of ACMP1 During EM23

Definition at line 1301 of file efr32fg14p_emu.h.

#define EMU_EM23PERNORETAINCTRL_ACMP1DIS_DEFAULT   (_EMU_EM23PERNORETAINCTRL_ACMP1DIS_DEFAULT << 1)

Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL

Definition at line 1305 of file efr32fg14p_emu.h.

#define EMU_EM23PERNORETAINCTRL_ADC0DIS   (0x1UL << 9)

Allow Power Down of ADC0 During EM23

Definition at line 1326 of file efr32fg14p_emu.h.

#define EMU_EM23PERNORETAINCTRL_ADC0DIS_DEFAULT   (_EMU_EM23PERNORETAINCTRL_ADC0DIS_DEFAULT << 9)

Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL

Definition at line 1330 of file efr32fg14p_emu.h.

#define EMU_EM23PERNORETAINCTRL_DAC0DIS   (0x1UL << 7)

Allow Power Down of DAC0 During EM23

Definition at line 1316 of file efr32fg14p_emu.h.

#define EMU_EM23PERNORETAINCTRL_DAC0DIS_DEFAULT   (_EMU_EM23PERNORETAINCTRL_DAC0DIS_DEFAULT << 7)

Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL

Definition at line 1320 of file efr32fg14p_emu.h.

#define EMU_EM23PERNORETAINCTRL_I2C0DIS   (0x1UL << 5)

Allow Power Down of I2C0 During EM23

Definition at line 1311 of file efr32fg14p_emu.h.

#define EMU_EM23PERNORETAINCTRL_I2C0DIS_DEFAULT   (_EMU_EM23PERNORETAINCTRL_I2C0DIS_DEFAULT << 5)

Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL

Definition at line 1315 of file efr32fg14p_emu.h.

#define EMU_EM23PERNORETAINCTRL_IDAC0DIS   (0x1UL << 8)

Allow Power Down of IDAC0 During EM23

Definition at line 1321 of file efr32fg14p_emu.h.

#define EMU_EM23PERNORETAINCTRL_IDAC0DIS_DEFAULT   (_EMU_EM23PERNORETAINCTRL_IDAC0DIS_DEFAULT << 8)

Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL

Definition at line 1325 of file efr32fg14p_emu.h.

#define EMU_EM23PERNORETAINCTRL_LESENSE0DIS   (0x1UL << 13)

Allow Power Down of LESENSE0 During EM23

Definition at line 1346 of file efr32fg14p_emu.h.

#define EMU_EM23PERNORETAINCTRL_LESENSE0DIS_DEFAULT   (_EMU_EM23PERNORETAINCTRL_LESENSE0DIS_DEFAULT << 13)

Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL

Definition at line 1350 of file efr32fg14p_emu.h.

#define EMU_EM23PERNORETAINCTRL_LETIMER0DIS   (0x1UL << 10)

Allow Power Down of LETIMER0 During EM23

Definition at line 1331 of file efr32fg14p_emu.h.

#define EMU_EM23PERNORETAINCTRL_LETIMER0DIS_DEFAULT   (_EMU_EM23PERNORETAINCTRL_LETIMER0DIS_DEFAULT << 10)

Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL

Definition at line 1335 of file efr32fg14p_emu.h.

#define EMU_EM23PERNORETAINCTRL_LEUART0DIS   (0x1UL << 15)

Allow Power Down of LEUART0 During EM23

Definition at line 1351 of file efr32fg14p_emu.h.

#define EMU_EM23PERNORETAINCTRL_LEUART0DIS_DEFAULT   (_EMU_EM23PERNORETAINCTRL_LEUART0DIS_DEFAULT << 15)

Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL

Definition at line 1355 of file efr32fg14p_emu.h.

#define EMU_EM23PERNORETAINCTRL_PCNT0DIS   (0x1UL << 2)

Allow Power Down of PCNT0 During EM23

Definition at line 1306 of file efr32fg14p_emu.h.

#define EMU_EM23PERNORETAINCTRL_PCNT0DIS_DEFAULT   (_EMU_EM23PERNORETAINCTRL_PCNT0DIS_DEFAULT << 2)

Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL

Definition at line 1310 of file efr32fg14p_emu.h.

#define EMU_EM23PERNORETAINCTRL_WDOG0DIS   (0x1UL << 11)

Allow Power Down of WDOG0 During EM23

Definition at line 1336 of file efr32fg14p_emu.h.

#define EMU_EM23PERNORETAINCTRL_WDOG0DIS_DEFAULT   (_EMU_EM23PERNORETAINCTRL_WDOG0DIS_DEFAULT << 11)

Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL

Definition at line 1340 of file efr32fg14p_emu.h.

#define EMU_EM23PERNORETAINCTRL_WDOG1DIS   (0x1UL << 12)

Allow Power Down of WDOG1 During EM23

Definition at line 1341 of file efr32fg14p_emu.h.

#define EMU_EM23PERNORETAINCTRL_WDOG1DIS_DEFAULT   (_EMU_EM23PERNORETAINCTRL_WDOG1DIS_DEFAULT << 12)

Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL

Definition at line 1345 of file efr32fg14p_emu.h.

#define EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED   (0x1UL << 0)

Indicates If ACMP0 Powered Down During EM23

Definition at line 1232 of file efr32fg14p_emu.h.

#define EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_DEFAULT   (_EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_DEFAULT << 0)

Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS

Definition at line 1236 of file efr32fg14p_emu.h.

#define EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED   (0x1UL << 1)

Indicates If ACMP1 Powered Down During EM23

Definition at line 1237 of file efr32fg14p_emu.h.

#define EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_DEFAULT   (_EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_DEFAULT << 1)

Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS

Definition at line 1241 of file efr32fg14p_emu.h.

#define EMU_EM23PERNORETAINSTATUS_ADC0LOCKED   (0x1UL << 9)

Indicates If ADC0 Powered Down During EM23

Definition at line 1262 of file efr32fg14p_emu.h.

#define EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_DEFAULT   (_EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_DEFAULT << 9)

Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS

Definition at line 1266 of file efr32fg14p_emu.h.

#define EMU_EM23PERNORETAINSTATUS_DAC0LOCKED   (0x1UL << 7)

Indicates If DAC0 Powered Down During EM23

Definition at line 1252 of file efr32fg14p_emu.h.

#define EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_DEFAULT   (_EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_DEFAULT << 7)

Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS

Definition at line 1256 of file efr32fg14p_emu.h.

#define EMU_EM23PERNORETAINSTATUS_I2C0LOCKED   (0x1UL << 5)

Indicates If I2C0 Powered Down During EM23

Definition at line 1247 of file efr32fg14p_emu.h.

#define EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_DEFAULT   (_EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_DEFAULT << 5)

Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS

Definition at line 1251 of file efr32fg14p_emu.h.

#define EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED   (0x1UL << 8)

Indicates If IDAC0 Powered Down During EM23

Definition at line 1257 of file efr32fg14p_emu.h.

#define EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_DEFAULT   (_EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_DEFAULT << 8)

Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS

Definition at line 1261 of file efr32fg14p_emu.h.

#define EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED   (0x1UL << 13)

Indicates If LESENSE0 Powered Down During EM23

Definition at line 1282 of file efr32fg14p_emu.h.

#define EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_DEFAULT   (_EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_DEFAULT << 13)

Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS

Definition at line 1286 of file efr32fg14p_emu.h.

#define EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED   (0x1UL << 10)

Indicates If LETIMER0 Powered Down During EM23

Definition at line 1267 of file efr32fg14p_emu.h.

#define EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_DEFAULT   (_EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_DEFAULT << 10)

Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS

Definition at line 1271 of file efr32fg14p_emu.h.

#define EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED   (0x1UL << 15)

Indicates If LEUART0 Powered Down During EM23

Definition at line 1287 of file efr32fg14p_emu.h.

#define EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_DEFAULT   (_EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_DEFAULT << 15)

Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS

Definition at line 1291 of file efr32fg14p_emu.h.

#define EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED   (0x1UL << 2)

Indicates If PCNT0 Powered Down During EM23

Definition at line 1242 of file efr32fg14p_emu.h.

#define EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_DEFAULT   (_EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_DEFAULT << 2)

Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS

Definition at line 1246 of file efr32fg14p_emu.h.

#define EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED   (0x1UL << 11)

Indicates If WDOG0 Powered Down During EM23

Definition at line 1272 of file efr32fg14p_emu.h.

#define EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_DEFAULT   (_EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_DEFAULT << 11)

Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS

Definition at line 1276 of file efr32fg14p_emu.h.

#define EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED   (0x1UL << 12)

Indicates If WDOG1 Powered Down During EM23

Definition at line 1277 of file efr32fg14p_emu.h.

#define EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_DEFAULT   (_EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_DEFAULT << 12)

Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS

Definition at line 1281 of file efr32fg14p_emu.h.

#define EMU_EM4CTRL_EM4ENTRY_DEFAULT   (_EMU_EM4CTRL_EM4ENTRY_DEFAULT << 16)

Shifted mode DEFAULT for EMU_EM4CTRL

Definition at line 299 of file efr32fg14p_emu.h.

#define EMU_EM4CTRL_EM4IORETMODE_DEFAULT   (_EMU_EM4CTRL_EM4IORETMODE_DEFAULT << 4)

Shifted mode DEFAULT for EMU_EM4CTRL

Definition at line 292 of file efr32fg14p_emu.h.

#define EMU_EM4CTRL_EM4IORETMODE_DISABLE   (_EMU_EM4CTRL_EM4IORETMODE_DISABLE << 4)

Shifted mode DISABLE for EMU_EM4CTRL

Definition at line 293 of file efr32fg14p_emu.h.

Referenced by GPIO_EM4SetPinRetention().

#define EMU_EM4CTRL_EM4IORETMODE_EM4EXIT   (_EMU_EM4CTRL_EM4IORETMODE_EM4EXIT << 4)

Shifted mode EM4EXIT for EMU_EM4CTRL

Definition at line 294 of file efr32fg14p_emu.h.

Referenced by GPIO_EM4SetPinRetention().

#define EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH   (_EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH << 4)

Shifted mode SWUNLATCH for EMU_EM4CTRL

Definition at line 295 of file efr32fg14p_emu.h.

#define EMU_EM4CTRL_EM4STATE   (0x1UL << 0)

Energy Mode 4 State

Definition at line 262 of file efr32fg14p_emu.h.

#define EMU_EM4CTRL_EM4STATE_DEFAULT   (_EMU_EM4CTRL_EM4STATE_DEFAULT << 0)

Shifted mode DEFAULT for EMU_EM4CTRL

Definition at line 268 of file efr32fg14p_emu.h.

#define EMU_EM4CTRL_EM4STATE_EM4H   (_EMU_EM4CTRL_EM4STATE_EM4H << 0)

Shifted mode EM4H for EMU_EM4CTRL

Definition at line 270 of file efr32fg14p_emu.h.

Referenced by EMU_EM4Init(), and EMU_EnterEM4().

#define EMU_EM4CTRL_EM4STATE_EM4S   (_EMU_EM4CTRL_EM4STATE_EM4S << 0)

Shifted mode EM4S for EMU_EM4CTRL

Definition at line 269 of file efr32fg14p_emu.h.

Referenced by EMU_EnterEM4().

#define EMU_EM4CTRL_RETAINLFRCO   (0x1UL << 1)

LFRCO Retain During EM4

Definition at line 271 of file efr32fg14p_emu.h.

Referenced by EMU_EM4Init().

#define EMU_EM4CTRL_RETAINLFRCO_DEFAULT   (_EMU_EM4CTRL_RETAINLFRCO_DEFAULT << 1)

Shifted mode DEFAULT for EMU_EM4CTRL

Definition at line 275 of file efr32fg14p_emu.h.

#define EMU_EM4CTRL_RETAINLFXO   (0x1UL << 2)

LFXO Retain During EM4

Definition at line 276 of file efr32fg14p_emu.h.

Referenced by EMU_EM4Init().

#define EMU_EM4CTRL_RETAINLFXO_DEFAULT   (_EMU_EM4CTRL_RETAINLFXO_DEFAULT << 2)

Shifted mode DEFAULT for EMU_EM4CTRL

Definition at line 280 of file efr32fg14p_emu.h.

#define EMU_EM4CTRL_RETAINULFRCO   (0x1UL << 3)

ULFRCO Retain During EM4S

Definition at line 281 of file efr32fg14p_emu.h.

Referenced by EMU_EM4Init().

#define EMU_EM4CTRL_RETAINULFRCO_DEFAULT   (_EMU_EM4CTRL_RETAINULFRCO_DEFAULT << 3)

Shifted mode DEFAULT for EMU_EM4CTRL

Definition at line 285 of file efr32fg14p_emu.h.

#define EMU_IEN_DCDCINBYPASS   (0x1UL << 20)

DCDCINBYPASS Interrupt Enable

Definition at line 711 of file efr32fg14p_emu.h.

#define EMU_IEN_DCDCINBYPASS_DEFAULT   (_EMU_IEN_DCDCINBYPASS_DEFAULT << 20)

Shifted mode DEFAULT for EMU_IEN

Definition at line 715 of file efr32fg14p_emu.h.

#define EMU_IEN_DCDCLNRUNNING   (0x1UL << 19)

DCDCLNRUNNING Interrupt Enable

Definition at line 706 of file efr32fg14p_emu.h.

#define EMU_IEN_DCDCLNRUNNING_DEFAULT   (_EMU_IEN_DCDCLNRUNNING_DEFAULT << 19)

Shifted mode DEFAULT for EMU_IEN

Definition at line 710 of file efr32fg14p_emu.h.

#define EMU_IEN_DCDCLPRUNNING   (0x1UL << 18)

DCDCLPRUNNING Interrupt Enable

Definition at line 701 of file efr32fg14p_emu.h.

#define EMU_IEN_DCDCLPRUNNING_DEFAULT   (_EMU_IEN_DCDCLPRUNNING_DEFAULT << 18)

Shifted mode DEFAULT for EMU_IEN

Definition at line 705 of file efr32fg14p_emu.h.

#define EMU_IEN_EM23WAKEUP   (0x1UL << 24)

EM23WAKEUP Interrupt Enable

Definition at line 716 of file efr32fg14p_emu.h.

#define EMU_IEN_EM23WAKEUP_DEFAULT   (_EMU_IEN_EM23WAKEUP_DEFAULT << 24)

Shifted mode DEFAULT for EMU_IEN

Definition at line 720 of file efr32fg14p_emu.h.

#define EMU_IEN_NFETOVERCURRENTLIMIT   (0x1UL << 17)

NFETOVERCURRENTLIMIT Interrupt Enable

Definition at line 696 of file efr32fg14p_emu.h.

#define EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT   (_EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT << 17)

Shifted mode DEFAULT for EMU_IEN

Definition at line 700 of file efr32fg14p_emu.h.

#define EMU_IEN_PFETOVERCURRENTLIMIT   (0x1UL << 16)

PFETOVERCURRENTLIMIT Interrupt Enable

Definition at line 691 of file efr32fg14p_emu.h.

#define EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT   (_EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT << 16)

Shifted mode DEFAULT for EMU_IEN

Definition at line 695 of file efr32fg14p_emu.h.

#define EMU_IEN_TEMP   (0x1UL << 29)

TEMP Interrupt Enable

Definition at line 726 of file efr32fg14p_emu.h.

#define EMU_IEN_TEMP_DEFAULT   (_EMU_IEN_TEMP_DEFAULT << 29)

Shifted mode DEFAULT for EMU_IEN

Definition at line 730 of file efr32fg14p_emu.h.

#define EMU_IEN_TEMPHIGH   (0x1UL << 31)

TEMPHIGH Interrupt Enable

Definition at line 736 of file efr32fg14p_emu.h.

Referenced by updateInterrupts().

#define EMU_IEN_TEMPHIGH_DEFAULT   (_EMU_IEN_TEMPHIGH_DEFAULT << 31)

Shifted mode DEFAULT for EMU_IEN

Definition at line 740 of file efr32fg14p_emu.h.

#define EMU_IEN_TEMPLOW   (0x1UL << 30)

TEMPLOW Interrupt Enable

Definition at line 731 of file efr32fg14p_emu.h.

Referenced by updateInterrupts().

#define EMU_IEN_TEMPLOW_DEFAULT   (_EMU_IEN_TEMPLOW_DEFAULT << 30)

Shifted mode DEFAULT for EMU_IEN

Definition at line 735 of file efr32fg14p_emu.h.

#define EMU_IEN_VMONALTAVDDFALL   (0x1UL << 2)

VMONALTAVDDFALL Interrupt Enable

Definition at line 651 of file efr32fg14p_emu.h.

#define EMU_IEN_VMONALTAVDDFALL_DEFAULT   (_EMU_IEN_VMONALTAVDDFALL_DEFAULT << 2)

Shifted mode DEFAULT for EMU_IEN

Definition at line 655 of file efr32fg14p_emu.h.

#define EMU_IEN_VMONALTAVDDRISE   (0x1UL << 3)

VMONALTAVDDRISE Interrupt Enable

Definition at line 656 of file efr32fg14p_emu.h.

#define EMU_IEN_VMONALTAVDDRISE_DEFAULT   (_EMU_IEN_VMONALTAVDDRISE_DEFAULT << 3)

Shifted mode DEFAULT for EMU_IEN

Definition at line 660 of file efr32fg14p_emu.h.

#define EMU_IEN_VMONAVDDFALL   (0x1UL << 0)

VMONAVDDFALL Interrupt Enable

Definition at line 641 of file efr32fg14p_emu.h.

#define EMU_IEN_VMONAVDDFALL_DEFAULT   (_EMU_IEN_VMONAVDDFALL_DEFAULT << 0)

Shifted mode DEFAULT for EMU_IEN

Definition at line 645 of file efr32fg14p_emu.h.

#define EMU_IEN_VMONAVDDRISE   (0x1UL << 1)

VMONAVDDRISE Interrupt Enable

Definition at line 646 of file efr32fg14p_emu.h.

#define EMU_IEN_VMONAVDDRISE_DEFAULT   (_EMU_IEN_VMONAVDDRISE_DEFAULT << 1)

Shifted mode DEFAULT for EMU_IEN

Definition at line 650 of file efr32fg14p_emu.h.

#define EMU_IEN_VMONDVDDFALL   (0x1UL << 4)

VMONDVDDFALL Interrupt Enable

Definition at line 661 of file efr32fg14p_emu.h.

#define EMU_IEN_VMONDVDDFALL_DEFAULT   (_EMU_IEN_VMONDVDDFALL_DEFAULT << 4)

Shifted mode DEFAULT for EMU_IEN

Definition at line 665 of file efr32fg14p_emu.h.

#define EMU_IEN_VMONDVDDRISE   (0x1UL << 5)

VMONDVDDRISE Interrupt Enable

Definition at line 666 of file efr32fg14p_emu.h.

#define EMU_IEN_VMONDVDDRISE_DEFAULT   (_EMU_IEN_VMONDVDDRISE_DEFAULT << 5)

Shifted mode DEFAULT for EMU_IEN

Definition at line 670 of file efr32fg14p_emu.h.

#define EMU_IEN_VMONFVDDFALL   (0x1UL << 14)

VMONFVDDFALL Interrupt Enable

Definition at line 681 of file efr32fg14p_emu.h.

#define EMU_IEN_VMONFVDDFALL_DEFAULT   (_EMU_IEN_VMONFVDDFALL_DEFAULT << 14)

Shifted mode DEFAULT for EMU_IEN

Definition at line 685 of file efr32fg14p_emu.h.

#define EMU_IEN_VMONFVDDRISE   (0x1UL << 15)

VMONFVDDRISE Interrupt Enable

Definition at line 686 of file efr32fg14p_emu.h.

#define EMU_IEN_VMONFVDDRISE_DEFAULT   (_EMU_IEN_VMONFVDDRISE_DEFAULT << 15)

Shifted mode DEFAULT for EMU_IEN

Definition at line 690 of file efr32fg14p_emu.h.

#define EMU_IEN_VMONIO0FALL   (0x1UL << 6)

VMONIO0FALL Interrupt Enable

Definition at line 671 of file efr32fg14p_emu.h.

#define EMU_IEN_VMONIO0FALL_DEFAULT   (_EMU_IEN_VMONIO0FALL_DEFAULT << 6)

Shifted mode DEFAULT for EMU_IEN

Definition at line 675 of file efr32fg14p_emu.h.

#define EMU_IEN_VMONIO0RISE   (0x1UL << 7)

VMONIO0RISE Interrupt Enable

Definition at line 676 of file efr32fg14p_emu.h.

#define EMU_IEN_VMONIO0RISE_DEFAULT   (_EMU_IEN_VMONIO0RISE_DEFAULT << 7)

Shifted mode DEFAULT for EMU_IEN

Definition at line 680 of file efr32fg14p_emu.h.

#define EMU_IEN_VSCALEDONE   (0x1UL << 25)

VSCALEDONE Interrupt Enable

Definition at line 721 of file efr32fg14p_emu.h.

#define EMU_IEN_VSCALEDONE_DEFAULT   (_EMU_IEN_VSCALEDONE_DEFAULT << 25)

Shifted mode DEFAULT for EMU_IEN

Definition at line 725 of file efr32fg14p_emu.h.

#define EMU_IF_DCDCINBYPASS   (0x1UL << 20)

DCDC is in Bypass

Definition at line 399 of file efr32fg14p_emu.h.

Referenced by EMU_DCDCConductionModeSet().

#define EMU_IF_DCDCINBYPASS_DEFAULT   (_EMU_IF_DCDCINBYPASS_DEFAULT << 20)

Shifted mode DEFAULT for EMU_IF

Definition at line 403 of file efr32fg14p_emu.h.

#define EMU_IF_DCDCLNRUNNING   (0x1UL << 19)

LN Mode is Running

Definition at line 394 of file efr32fg14p_emu.h.

Referenced by EMU_DCDCModeSet().

#define EMU_IF_DCDCLNRUNNING_DEFAULT   (_EMU_IF_DCDCLNRUNNING_DEFAULT << 19)

Shifted mode DEFAULT for EMU_IF

Definition at line 398 of file efr32fg14p_emu.h.

#define EMU_IF_DCDCLPRUNNING   (0x1UL << 18)

LP Mode is Running

Definition at line 389 of file efr32fg14p_emu.h.

#define EMU_IF_DCDCLPRUNNING_DEFAULT   (_EMU_IF_DCDCLPRUNNING_DEFAULT << 18)

Shifted mode DEFAULT for EMU_IF

Definition at line 393 of file efr32fg14p_emu.h.

#define EMU_IF_EM23WAKEUP   (0x1UL << 24)

Wakeup IRQ From EM2 and EM3

Definition at line 404 of file efr32fg14p_emu.h.

#define EMU_IF_EM23WAKEUP_DEFAULT   (_EMU_IF_EM23WAKEUP_DEFAULT << 24)

Shifted mode DEFAULT for EMU_IF

Definition at line 408 of file efr32fg14p_emu.h.

#define EMU_IF_NFETOVERCURRENTLIMIT   (0x1UL << 17)

NFET Current Limit Hit

Definition at line 384 of file efr32fg14p_emu.h.

#define EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT   (_EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT << 17)

Shifted mode DEFAULT for EMU_IF

Definition at line 388 of file efr32fg14p_emu.h.

#define EMU_IF_PFETOVERCURRENTLIMIT   (0x1UL << 16)

PFET Current Limit Hit

Definition at line 379 of file efr32fg14p_emu.h.

#define EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT   (_EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT << 16)

Shifted mode DEFAULT for EMU_IF

Definition at line 383 of file efr32fg14p_emu.h.

#define EMU_IF_TEMP   (0x1UL << 29)

New Temperature Measurement Valid

Definition at line 414 of file efr32fg14p_emu.h.

#define EMU_IF_TEMP_DEFAULT   (_EMU_IF_TEMP_DEFAULT << 29)

Shifted mode DEFAULT for EMU_IF

Definition at line 418 of file efr32fg14p_emu.h.

#define EMU_IF_TEMPHIGH   (0x1UL << 31)

Temperature High Limit Reached

Definition at line 424 of file efr32fg14p_emu.h.

Referenced by TEMPDRV_IRQHandler().

#define EMU_IF_TEMPHIGH_DEFAULT   (_EMU_IF_TEMPHIGH_DEFAULT << 31)

Shifted mode DEFAULT for EMU_IF

Definition at line 428 of file efr32fg14p_emu.h.

#define EMU_IF_TEMPLOW   (0x1UL << 30)

Temperature Low Limit Reached

Definition at line 419 of file efr32fg14p_emu.h.

Referenced by TEMPDRV_IRQHandler().

#define EMU_IF_TEMPLOW_DEFAULT   (_EMU_IF_TEMPLOW_DEFAULT << 30)

Shifted mode DEFAULT for EMU_IF

Definition at line 423 of file efr32fg14p_emu.h.

#define EMU_IF_VMONALTAVDDFALL   (0x1UL << 2)

Alternate VMON AVDD Channel Fall

Definition at line 339 of file efr32fg14p_emu.h.

#define EMU_IF_VMONALTAVDDFALL_DEFAULT   (_EMU_IF_VMONALTAVDDFALL_DEFAULT << 2)

Shifted mode DEFAULT for EMU_IF

Definition at line 343 of file efr32fg14p_emu.h.

#define EMU_IF_VMONALTAVDDRISE   (0x1UL << 3)

Alternate VMON AVDD Channel Rise

Definition at line 344 of file efr32fg14p_emu.h.

#define EMU_IF_VMONALTAVDDRISE_DEFAULT   (_EMU_IF_VMONALTAVDDRISE_DEFAULT << 3)

Shifted mode DEFAULT for EMU_IF

Definition at line 348 of file efr32fg14p_emu.h.

#define EMU_IF_VMONAVDDFALL   (0x1UL << 0)

VMON AVDD Channel Fall

Definition at line 329 of file efr32fg14p_emu.h.

#define EMU_IF_VMONAVDDFALL_DEFAULT   (_EMU_IF_VMONAVDDFALL_DEFAULT << 0)

Shifted mode DEFAULT for EMU_IF

Definition at line 333 of file efr32fg14p_emu.h.

#define EMU_IF_VMONAVDDRISE   (0x1UL << 1)

VMON AVDD Channel Rise

Definition at line 334 of file efr32fg14p_emu.h.

#define EMU_IF_VMONAVDDRISE_DEFAULT   (_EMU_IF_VMONAVDDRISE_DEFAULT << 1)

Shifted mode DEFAULT for EMU_IF

Definition at line 338 of file efr32fg14p_emu.h.

#define EMU_IF_VMONDVDDFALL   (0x1UL << 4)

VMON DVDD Channel Fall

Definition at line 349 of file efr32fg14p_emu.h.

#define EMU_IF_VMONDVDDFALL_DEFAULT   (_EMU_IF_VMONDVDDFALL_DEFAULT << 4)

Shifted mode DEFAULT for EMU_IF

Definition at line 353 of file efr32fg14p_emu.h.

#define EMU_IF_VMONDVDDRISE   (0x1UL << 5)

VMON DVDD Channel Rise

Definition at line 354 of file efr32fg14p_emu.h.

#define EMU_IF_VMONDVDDRISE_DEFAULT   (_EMU_IF_VMONDVDDRISE_DEFAULT << 5)

Shifted mode DEFAULT for EMU_IF

Definition at line 358 of file efr32fg14p_emu.h.

#define EMU_IF_VMONFVDDFALL   (0x1UL << 14)

VMON VDDFLASH Channel Fall

Definition at line 369 of file efr32fg14p_emu.h.

#define EMU_IF_VMONFVDDFALL_DEFAULT   (_EMU_IF_VMONFVDDFALL_DEFAULT << 14)

Shifted mode DEFAULT for EMU_IF

Definition at line 373 of file efr32fg14p_emu.h.

#define EMU_IF_VMONFVDDRISE   (0x1UL << 15)

VMON VDDFLASH Channel Rise

Definition at line 374 of file efr32fg14p_emu.h.

#define EMU_IF_VMONFVDDRISE_DEFAULT   (_EMU_IF_VMONFVDDRISE_DEFAULT << 15)

Shifted mode DEFAULT for EMU_IF

Definition at line 378 of file efr32fg14p_emu.h.

#define EMU_IF_VMONIO0FALL   (0x1UL << 6)

VMON IOVDD0 Channel Fall

Definition at line 359 of file efr32fg14p_emu.h.

#define EMU_IF_VMONIO0FALL_DEFAULT   (_EMU_IF_VMONIO0FALL_DEFAULT << 6)

Shifted mode DEFAULT for EMU_IF

Definition at line 363 of file efr32fg14p_emu.h.

#define EMU_IF_VMONIO0RISE   (0x1UL << 7)

VMON IOVDD0 Channel Rise

Definition at line 364 of file efr32fg14p_emu.h.

#define EMU_IF_VMONIO0RISE_DEFAULT   (_EMU_IF_VMONIO0RISE_DEFAULT << 7)

Shifted mode DEFAULT for EMU_IF

Definition at line 368 of file efr32fg14p_emu.h.

#define EMU_IF_VSCALEDONE   (0x1UL << 25)

Voltage Scale Steps Done IRQ

Definition at line 409 of file efr32fg14p_emu.h.

#define EMU_IF_VSCALEDONE_DEFAULT   (_EMU_IF_VSCALEDONE_DEFAULT << 25)

Shifted mode DEFAULT for EMU_IF

Definition at line 413 of file efr32fg14p_emu.h.

#define EMU_IFC_DCDCINBYPASS   (0x1UL << 20)

Clear DCDCINBYPASS Interrupt Flag

Definition at line 607 of file efr32fg14p_emu.h.

Referenced by EMU_DCDCConductionModeSet().

#define EMU_IFC_DCDCINBYPASS_DEFAULT   (_EMU_IFC_DCDCINBYPASS_DEFAULT << 20)

Shifted mode DEFAULT for EMU_IFC

Definition at line 611 of file efr32fg14p_emu.h.

#define EMU_IFC_DCDCLNRUNNING   (0x1UL << 19)

Clear DCDCLNRUNNING Interrupt Flag

Definition at line 602 of file efr32fg14p_emu.h.

Referenced by EMU_DCDCModeSet().

#define EMU_IFC_DCDCLNRUNNING_DEFAULT   (_EMU_IFC_DCDCLNRUNNING_DEFAULT << 19)

Shifted mode DEFAULT for EMU_IFC

Definition at line 606 of file efr32fg14p_emu.h.

#define EMU_IFC_DCDCLPRUNNING   (0x1UL << 18)

Clear DCDCLPRUNNING Interrupt Flag

Definition at line 597 of file efr32fg14p_emu.h.

#define EMU_IFC_DCDCLPRUNNING_DEFAULT   (_EMU_IFC_DCDCLPRUNNING_DEFAULT << 18)

Shifted mode DEFAULT for EMU_IFC

Definition at line 601 of file efr32fg14p_emu.h.

#define EMU_IFC_EM23WAKEUP   (0x1UL << 24)

Clear EM23WAKEUP Interrupt Flag

Definition at line 612 of file efr32fg14p_emu.h.

#define EMU_IFC_EM23WAKEUP_DEFAULT   (_EMU_IFC_EM23WAKEUP_DEFAULT << 24)

Shifted mode DEFAULT for EMU_IFC

Definition at line 616 of file efr32fg14p_emu.h.

#define EMU_IFC_NFETOVERCURRENTLIMIT   (0x1UL << 17)

Clear NFETOVERCURRENTLIMIT Interrupt Flag

Definition at line 592 of file efr32fg14p_emu.h.

#define EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT   (_EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT << 17)

Shifted mode DEFAULT for EMU_IFC

Definition at line 596 of file efr32fg14p_emu.h.

#define EMU_IFC_PFETOVERCURRENTLIMIT   (0x1UL << 16)

Clear PFETOVERCURRENTLIMIT Interrupt Flag

Definition at line 587 of file efr32fg14p_emu.h.

#define EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT   (_EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT << 16)

Shifted mode DEFAULT for EMU_IFC

Definition at line 591 of file efr32fg14p_emu.h.

#define EMU_IFC_TEMP   (0x1UL << 29)

Clear TEMP Interrupt Flag

Definition at line 622 of file efr32fg14p_emu.h.

#define EMU_IFC_TEMP_DEFAULT   (_EMU_IFC_TEMP_DEFAULT << 29)

Shifted mode DEFAULT for EMU_IFC

Definition at line 626 of file efr32fg14p_emu.h.

#define EMU_IFC_TEMPHIGH   (0x1UL << 31)

Clear TEMPHIGH Interrupt Flag

Definition at line 632 of file efr32fg14p_emu.h.

Referenced by disableInterrupts(), and TEMPDRV_IRQHandler().

#define EMU_IFC_TEMPHIGH_DEFAULT   (_EMU_IFC_TEMPHIGH_DEFAULT << 31)

Shifted mode DEFAULT for EMU_IFC

Definition at line 636 of file efr32fg14p_emu.h.

#define EMU_IFC_TEMPLOW   (0x1UL << 30)

Clear TEMPLOW Interrupt Flag

Definition at line 627 of file efr32fg14p_emu.h.

Referenced by disableInterrupts(), and TEMPDRV_IRQHandler().

#define EMU_IFC_TEMPLOW_DEFAULT   (_EMU_IFC_TEMPLOW_DEFAULT << 30)

Shifted mode DEFAULT for EMU_IFC

Definition at line 631 of file efr32fg14p_emu.h.

#define EMU_IFC_VMONALTAVDDFALL   (0x1UL << 2)

Clear VMONALTAVDDFALL Interrupt Flag

Definition at line 547 of file efr32fg14p_emu.h.

#define EMU_IFC_VMONALTAVDDFALL_DEFAULT   (_EMU_IFC_VMONALTAVDDFALL_DEFAULT << 2)

Shifted mode DEFAULT for EMU_IFC

Definition at line 551 of file efr32fg14p_emu.h.

#define EMU_IFC_VMONALTAVDDRISE   (0x1UL << 3)

Clear VMONALTAVDDRISE Interrupt Flag

Definition at line 552 of file efr32fg14p_emu.h.

#define EMU_IFC_VMONALTAVDDRISE_DEFAULT   (_EMU_IFC_VMONALTAVDDRISE_DEFAULT << 3)

Shifted mode DEFAULT for EMU_IFC

Definition at line 556 of file efr32fg14p_emu.h.

#define EMU_IFC_VMONAVDDFALL   (0x1UL << 0)

Clear VMONAVDDFALL Interrupt Flag

Definition at line 537 of file efr32fg14p_emu.h.

#define EMU_IFC_VMONAVDDFALL_DEFAULT   (_EMU_IFC_VMONAVDDFALL_DEFAULT << 0)

Shifted mode DEFAULT for EMU_IFC

Definition at line 541 of file efr32fg14p_emu.h.

#define EMU_IFC_VMONAVDDRISE   (0x1UL << 1)

Clear VMONAVDDRISE Interrupt Flag

Definition at line 542 of file efr32fg14p_emu.h.

#define EMU_IFC_VMONAVDDRISE_DEFAULT   (_EMU_IFC_VMONAVDDRISE_DEFAULT << 1)

Shifted mode DEFAULT for EMU_IFC

Definition at line 546 of file efr32fg14p_emu.h.

#define EMU_IFC_VMONDVDDFALL   (0x1UL << 4)

Clear VMONDVDDFALL Interrupt Flag

Definition at line 557 of file efr32fg14p_emu.h.

#define EMU_IFC_VMONDVDDFALL_DEFAULT   (_EMU_IFC_VMONDVDDFALL_DEFAULT << 4)

Shifted mode DEFAULT for EMU_IFC

Definition at line 561 of file efr32fg14p_emu.h.

#define EMU_IFC_VMONDVDDRISE   (0x1UL << 5)

Clear VMONDVDDRISE Interrupt Flag

Definition at line 562 of file efr32fg14p_emu.h.

#define EMU_IFC_VMONDVDDRISE_DEFAULT   (_EMU_IFC_VMONDVDDRISE_DEFAULT << 5)

Shifted mode DEFAULT for EMU_IFC

Definition at line 566 of file efr32fg14p_emu.h.

#define EMU_IFC_VMONFVDDFALL   (0x1UL << 14)

Clear VMONFVDDFALL Interrupt Flag

Definition at line 577 of file efr32fg14p_emu.h.

#define EMU_IFC_VMONFVDDFALL_DEFAULT   (_EMU_IFC_VMONFVDDFALL_DEFAULT << 14)

Shifted mode DEFAULT for EMU_IFC

Definition at line 581 of file efr32fg14p_emu.h.

#define EMU_IFC_VMONFVDDRISE   (0x1UL << 15)

Clear VMONFVDDRISE Interrupt Flag

Definition at line 582 of file efr32fg14p_emu.h.

#define EMU_IFC_VMONFVDDRISE_DEFAULT   (_EMU_IFC_VMONFVDDRISE_DEFAULT << 15)

Shifted mode DEFAULT for EMU_IFC

Definition at line 586 of file efr32fg14p_emu.h.

#define EMU_IFC_VMONIO0FALL   (0x1UL << 6)

Clear VMONIO0FALL Interrupt Flag

Definition at line 567 of file efr32fg14p_emu.h.

#define EMU_IFC_VMONIO0FALL_DEFAULT   (_EMU_IFC_VMONIO0FALL_DEFAULT << 6)

Shifted mode DEFAULT for EMU_IFC

Definition at line 571 of file efr32fg14p_emu.h.

#define EMU_IFC_VMONIO0RISE   (0x1UL << 7)

Clear VMONIO0RISE Interrupt Flag

Definition at line 572 of file efr32fg14p_emu.h.

#define EMU_IFC_VMONIO0RISE_DEFAULT   (_EMU_IFC_VMONIO0RISE_DEFAULT << 7)

Shifted mode DEFAULT for EMU_IFC

Definition at line 576 of file efr32fg14p_emu.h.

#define EMU_IFC_VSCALEDONE   (0x1UL << 25)

Clear VSCALEDONE Interrupt Flag

Definition at line 617 of file efr32fg14p_emu.h.

#define EMU_IFC_VSCALEDONE_DEFAULT   (_EMU_IFC_VSCALEDONE_DEFAULT << 25)

Shifted mode DEFAULT for EMU_IFC

Definition at line 621 of file efr32fg14p_emu.h.

#define EMU_IFS_DCDCINBYPASS   (0x1UL << 20)

Set DCDCINBYPASS Interrupt Flag

Definition at line 503 of file efr32fg14p_emu.h.

#define EMU_IFS_DCDCINBYPASS_DEFAULT   (_EMU_IFS_DCDCINBYPASS_DEFAULT << 20)

Shifted mode DEFAULT for EMU_IFS

Definition at line 507 of file efr32fg14p_emu.h.

#define EMU_IFS_DCDCLNRUNNING   (0x1UL << 19)

Set DCDCLNRUNNING Interrupt Flag

Definition at line 498 of file efr32fg14p_emu.h.

#define EMU_IFS_DCDCLNRUNNING_DEFAULT   (_EMU_IFS_DCDCLNRUNNING_DEFAULT << 19)

Shifted mode DEFAULT for EMU_IFS

Definition at line 502 of file efr32fg14p_emu.h.

#define EMU_IFS_DCDCLPRUNNING   (0x1UL << 18)

Set DCDCLPRUNNING Interrupt Flag

Definition at line 493 of file efr32fg14p_emu.h.

#define EMU_IFS_DCDCLPRUNNING_DEFAULT   (_EMU_IFS_DCDCLPRUNNING_DEFAULT << 18)

Shifted mode DEFAULT for EMU_IFS

Definition at line 497 of file efr32fg14p_emu.h.

#define EMU_IFS_EM23WAKEUP   (0x1UL << 24)

Set EM23WAKEUP Interrupt Flag

Definition at line 508 of file efr32fg14p_emu.h.

#define EMU_IFS_EM23WAKEUP_DEFAULT   (_EMU_IFS_EM23WAKEUP_DEFAULT << 24)

Shifted mode DEFAULT for EMU_IFS

Definition at line 512 of file efr32fg14p_emu.h.

#define EMU_IFS_NFETOVERCURRENTLIMIT   (0x1UL << 17)

Set NFETOVERCURRENTLIMIT Interrupt Flag

Definition at line 488 of file efr32fg14p_emu.h.

#define EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT   (_EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT << 17)

Shifted mode DEFAULT for EMU_IFS

Definition at line 492 of file efr32fg14p_emu.h.

#define EMU_IFS_PFETOVERCURRENTLIMIT   (0x1UL << 16)

Set PFETOVERCURRENTLIMIT Interrupt Flag

Definition at line 483 of file efr32fg14p_emu.h.

#define EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT   (_EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT << 16)

Shifted mode DEFAULT for EMU_IFS

Definition at line 487 of file efr32fg14p_emu.h.